JPS62179033A - Ic microprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to integrated circuit microprocessors, and more particularly to the field of breakpoints in computer programs used to analyze or program programs. Regarding the field of hardware that gives.

[Prior art and its problems]

Many techniques are used to analyze the performance of computer programs, particularly during their development.

This is mainly called "debugging". This debugging process is an important part of the development of computer programs; for example, the time required to debug may exceed the time required to write the program.

Techniques used to debug computer programs include interrupting the program at predetermined events and then examining, for example, the contents of registers. One such event is the occurrence of a predetermined address that references a computer program or data.

A "breakpoint" occurs when an address generated by the computer matches one of the predetermined addresses. Then, computer operation is interrupted and analysis is performed.

One way to implement breakpoint interrupts is to modify the computer program itself. That is, the program is interrupted at a predetermined address in the program. Although this method is relatively inexpensive, it has the disadvantage that breakpoints cannot be set at addresses that reference data.

Another method is to use hardware external to the computer or microprocessor to perform breakpoint interrupts. This hardware compares the computer-generated address to a predetermined address and provides a breakpoint or interrupt signal. but,
This method is generally expensive and requires a significant amount of printed circuit board area. Furthermore, fast processors cannot respond fast enough to generate a "real-time" breakpoint. A significant problem also arises when a microprocessor includes within itself an address translation device, such as a memory management device. The addresses generated by the computer that are accessible to the user are physical addresses typically connected to random-access memory. That is, the virtual addresses used by the programmer cannot be used for this purpose. Therefore, it is difficult to set breakpoints based on physical addresses.

As described below, the present invention provides a breakpoint device that solves the above problems, and furthermore, it can increase the selection of breakpoints.

[Summary of the invention]

The present invention provides a breakpoint signaling device useful for debugging computer programs. This apparatus is particularly useful in integrated circuit microprocessors formed on a single substrate.

This microprocessor includes an address generator that generates a virtual address for referencing program instructions or data, a virtual address bus,
Address translation II, which converts virtual addresses on the bus to physical addresses, and program
It includes a translation device that translates instructions and an arithmetic device that manipulates data according to the translated instructions. The apparatus also includes a first register for storing a predetermined address at which a breakpoint occurs in the form of a virtual address. Additionally, a second register is used to store control bits that allow the user to select predetermined conditions for the breakpoint, such as whether the breakpoint should occur on reference to the computer program or data. . The comparison device compares the address generated by the computer (current virtual address) with a predetermined virtual address. The first logic unit determines whether the current virtual address is a reference to a program instruction or data by examining address control signals. This first logic device is also controlled by control bits stored in a second register.

A gating device used to provide a breakpoint signal and interrupt operation of the computer is connected to the comparison device and the output of the first logic device.

The entire device is formed on the same substrate as the microprocessor.

Further, the device is configured to perform a step for determining whether the current virtual address corresponds to the reference represented by the predetermined address, or whether the reference represented by the predetermined address corresponds to the reference created by the virtual address. Contains 2 logical units. Therefore, this allows the width of a given breakpoint address to be set by the control bits stored in the second register.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

〔Example〕

The breakpoint device is particularly suitable for use in a microprocessor that includes an address translation device f manufactured integrally with the microprocessor. Typically, in such cases, the virtual address is inaccessible to the user, making it difficult to set breakpoints. In this embodiment, the breakpoint device is integrally formed on the same substrate as the microprocessor and its address translation device.

In the following description, it will be clear to those skilled in the art that various specific descriptions such as the number of bits are provided to aid understanding of the present invention, and that the present invention is not limited to these descriptions.

In other instances, well-known structures will not be described in detail so as not to obscure the present invention.

In this embodiment, the microprocessor 10 of FIG. 1 is formed on a single silicon substrate using a complementary metal-oxide single conductor (0MO8) process. Although any one of a number of well-known CMOS processes may be used, it will be apparent that the invention may be implemented with other technologies, such as n-channel, bipolar, SO8, etc.

In FIG. 1, a single chip number microprocessor 10
f-1, a bus interface device 14, an instruction decoder device 16, an execution device 18, and an address translation device 20, the breakpoint circuit 30 is the subject of the present invention.
Contained within 0.

A 32-bit microprocessor is connected to external random access memory 13. The bus device 14 is
It includes buffers for transmitting 32-bit addresses and for receiving and transmitting 32-bit data. Within the microprocessor, the bus device includes a prefetch device that fetches instructions from memory 13 and a prefetch queue device that communicates with the instruction device of the instruction decoder. , and waits in the device 16. Generally, the arithmetic and logic unit of the execution unit 18 executes the instructions.

In the illustrated microarchitecture, the address translation device l:j: provides two address translation functions.

One relates to the segment-distributor register and the other relates to the page-discriminator φ cache memory. This is the bus φ interface device Pt
, 14. This function is disclosed in US Patent Application No. 744β89 filed on June 13, 1985, which was assigned to the applicant of the present invention, and the title of the invention is ``Microprocessor - System Memory Management. 1. The breakpoint circuit is connected by a bus 19 between the segment descriptor register and the page descriptor cache memory.

Virtual addresses are transmitted by this bus. These virtual addresses are easily accessible to programmers, whereas physical addresses are not. Furthermore, as mentioned above, it is difficult to provide breakpoints based on physical addresses.6 A control device (not shown) is connected to the devices shown in FIG. 1 to perform overall control. .

In FIG. 2, the breakpoint circuit 30 of FIG. 1 includes a 32-bit register/comparator 3.4t. In this embodiment, the register and comparator are integrated into a single circuit. One stage of this register/comparator is shown in FIG. Register/comparator 34 stores a predetermined address at which a breakpoint occurs (sometimes referred to as a breakpoint address as described below). Register and comparator 34 compares the stored breakpoint address to a virtual address generated by the microprocessor (sometimes referred to as the current virtual address or current address, as described below). If load signal 35 is present, the 32-bit breakpoint address is loaded into register/comparator 34 (by bus 19a). Register and comparator 34 then compares the breakpoint address with the address of each current f: on bus 19 and provides a 1-Hit'' signal on line 46 if there is a match. The two least significant bits of the breakpoint address in register and comparator 34 are not useful as part of this comparison for reasons explained below, but are
A) Sent to 38.

The instruction decoder 16 of FIG. 1 translates predetermined instructions to the microprocessor as a load register/comparator 34 command, thereby allowing a user to load the register/comparator 34 with a breakpoint address. Further, another instruction allows the user to read the address stored in the register/comparator 34.

In this embodiment, four register/comparators 34 are used to allow storage of four different breakpoint addresses. Each register and comparator 34 is associated with a register 32 that stores control bits for each breakpoint address, as described below. For illustrative purposes, the circuit of FIG.
and only one second register 32 is shown.

However, it will be apparent to those skilled in the art that multiple registers and comparators 32 and 34 may be used and may be interrupted at any one of nine breakpoint-addresses.

Control register 32 stores four control bits for each breakpoint address. One bit determines whether the breakpoint address data ti represents a reference to a computer program. In the case of references, two control bits are useful in determining the width of the breakpoint. In this embodiment, breakpoints are 2, 2, or 4 bytes wide. Also, for data breakpoints, one more control bit is used to interrupt only on the emptying cycle or on either the read or write cycle.

In the register/comparator 34, the microprocessor 1
The predetermined instruction to zero is translated by device 16, thereby allowing the user to load shifter 32.

Enable logic circuit 36 is connected to receive bus control signals. These lines indicate whether the current address is a reference to program or data;
In the case of a data reference, it also includes a control signal that determines whether it is a read cycle only or a read or write cycle. Enable logic circuit 36 transfers these control signals to register 32.
If the memory cycle matches the cycle selected by the user, the enable clock is sent to AND gate 40. Ordinary logic circuits are used for this purpose.

As mentioned above, the breakpoints are 1.2 or 4.
This width, which is byte wide and selected by the user, is stored in register 32. The 2 bits required for this selection are PLA38
sent to. Additionally, as previously discussed, the two least significant bits stored in register and comparator 34 are
sent to. Timing and control signals from line 20 are also sent to PLA3B. PLAs are not user programmable; they are permanently programmed at the factory. PLA uses the logic shown in later sections. The use of PLA is
In the present invention, there is not much loss. That is, other logic circuits may be used instead of PLA.

In FIG. 4a, a relatively wide breakpoint φ address reference 70 (eg, 4 bytes) is shown. The current memory virtual address is reference 7
Only part of 0 can be referenced. However, the fourth
In the case of a narrow breakpoint address reference, such as reference T4 shown in Figure b, the relatively wide virtual address reference encompasses a narrower breakpoint address reference 74. In the two cases shown in Figures 4a and 4b, P
Solved by LA38. As mentioned above, whether the current memory address reference is within the wide breakpoint address reference or whether the narrow breakpoint Φ address reference falls within the wide current memory address reference. You can use logic circuitry to determine whether or not. If either of these situations occurs, a "match" signal is generated on line 52.

AND gate 40 receives three inputs: a hit signal from register and comparator 34, an enable clock from logic circuit 36 (7), and a match signal from circuit 38. The hit signal is 30 of the current virtual address.
Occurs when the 30 most significant bits of the breakpoint address match the 30 most significant address bits of the stored breakpoint address. The output of gate 40 provides a breakpoint signal that is used to interrupt operation of the microprocessor.

The single stage of register/comparator 34 shown in FIG.
It includes a static memory cell 55 and a comparator 54. The bus 719a, 19b carries a single address bit and its concatenation. The hit line 46 connects to a comparator 54 and a P-channel transistor 56. - Used to precharge line 46 before a bus cycle; line 46 also connects to the membrane of register and comparator 34;

The differentially connected l-inverters form a conventional flip-flop or static memory cell 55. This cell is connected to line 19a when the load signal is present on line 35.

19b. When the register is partially loaded, the potential of the load signal drops and lines 19a, 1
Effectively separates cell 55 from 9b. Thereafter, when the current virtual address appears on these lines and the φ1 signal is present, the contents of cell 55 are transferred to bus 1 by comparator 54.
It is compared with the address of 9. If there is no match on either VC of the 32-bit pair being compared, line 46 is discharged, preventing AND gate 40 of FIG. 2 from being enabled. The circuit of FIG. 3 is shown in more detail in the aforementioned application in which the circuit is used as part of a content addressable memory.

When using, the user must set the four lowest breakpoints and
Determine the addresses and determine whether these addresses are program or data references, if data references, the width of the references, and whether the breakpoints are on read cycles only or on read 1 to or write cycles. Choose what happens. Specific instructions then allow the user to load up to four breakpoint addresses into register and comparator 34 and set control bits for each breakpoint in register 32. Subsequently, on each virtual address bus cycle, a comparison is made in register/comparator 34 and logic circuit 3
6.38 determines whether the user selected state exists. If the address matches and the condition is met, a breakpoint signal is generated at gate 40.

Unlike the conventional methods described above, real-time breakpoint signals are generated. Also, since the comparison is performed while the virtual address is on the bus, and there is little propagation delay, interrupt signals can be generated at appropriate times.

As mentioned above, we have described an improved breakpoint device, which allows virtual addresses to
This is particularly useful in a single TUB O microprocessor where the physical address of the chip is translated into a "chip" physical address.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the entire microarchitecture of a microprocessor in which the device of the present invention is used, Fig. 2 is a block diagram showing the breakpoint device of the invention, and Fig. 3 is a block diagram of Fig. 2. Figure 4a shows the case where the memory reference represented by a given (breakpoint) address is wider than the memory address reference. FIG. 4b shows the case where the memory reference represented by a predetermined (breakpoint) address is narrower than the memory address reference. 13--random memory, 14-1111 bus interface device, 16-φ-instruction fist decoding device, ia--execution device, 20--
・Address translation device, 30...
Breakpoint circuit, 32... 4-bit debug register, 34... register/comparator, 36...
... Enable logic circuit, 38... PLA, 54
... Comparator.

Claims (10)

[Claims] (1) An address generator that generates virtual addresses for program instructions and data references, a virtual address bus, an address translation device that converts virtual addresses on the bus into physical addresses, and a program In an integrated circuit microprocessor formed on a single substrate that includes a translation device for translating instructions and an arithmetic unit for manipulating data according to the translated instructions: a second register for storing control bits; a comparison device connected to said first register and for comparing at least a portion of said stored address with a current address on said bus; a first logic device for determining whether an address is a reference for a program instruction or data; a first logic device coupled to said second register to sense at least one of said stored control bits; and; a gate device connected to the comparison device and the first logic device and supplying a breakpoint signal; the first and second registers, the comparison device, the first logic device and the gate device are connected to the substrate. established in
An integrated circuit microprocessor for providing breakpoint signals, characterized in that a real-time breakpoint signal is provided to said microprocessor. (2) The microprocessor according to claim 1, wherein the translation device translates a certain instruction to enable loading of the first register from the bus. (3) The microprocessor according to claim 2, wherein the translation device translates a predetermined instruction to enable loading of the second register. (4) In the microprocessor according to claim 3, the other of the control bits stored in the second register is set when the breakpoint is set only in the read cycle, or in either the read or write cycle.
A microprocessor characterized in that it determines what occurs with respect to a reference. (5) A microprocessor according to claim 3, wherein certain bits of the control bits stored in the second register determine the width of the address at which the breakpoint occurs; narrower than the stored address, whether the reference represented by the stored address includes a reference to the current address, or (ii) the current address is narrower than the stored address; A microprocessor comprising a second logic device for determining whether the current address reference, which is broader than the address reference, includes a reference represented by the stored address. (6) an address generator that generates virtual addresses for program instructions and data references; a virtual address bus; an address translation device that converts virtual addresses on the bus into physical addresses; In an integrated circuit microprocessor formed on a single substrate that includes a translation device for translating instructions and an arithmetic unit for manipulating data according to the translated instructions: - a first register for storing an address); a second register for storing control bits, at least some of the control bits determining the width of the breakpoint address; and a second register for storing control bits; a comparator connected to and for comparing at least a portion of said stored virtual address with a current virtual address on said bus; said current virtual address being included in the reference represented by said breakpoint address; a first logical device connected to the first and second registers; ; connected to the comparator and the first logic device;
a gate device for supplying the breakpoint signal, the first and second registers, a comparator, a second
An integrated circuit microprocessor for providing breakpoint signals, characterized in that logic devices and gate devices are provided on the substrate and real-time breakpoint signals are provided to the microprocessor. (7) The microprocessor according to claim 6, wherein the translation device translates a certain instruction to enable loading of the first register. (8) The microprocessor according to claim 7, wherein the translation device translates a predetermined instruction to enable loading of the second register. (9) The microprocessor according to claim 8, further comprising a second logical device that determines whether the current virtual address is a program or data reference, and the second logical device is a second logical device. A microprocessor connected to a register to sense at least one of the stored control bits, and further characterized in that said second logic device provides an output to a gating device. (10) In the microprocessor according to claim 9, the control bit stored in the second register determines whether a breakpoint occurs on a reference for data only in a read cycle, or in a read or write cycle. A microprocessor characterized by determining.