JPS62169540U

JPS62169540U -

Info

Publication number: JPS62169540U
Application number: JP1986055997U
Authority: JP
Priority date: 1986-04-16
Filing date: 1986-04-16
Publication date: 1987-10-27

Description

[Brief explanation of the drawing]

第１図は本考案の実施例のブロツク図、第２図
は第１図のタイミング図、第３図は従来例を示す
ブロツク図、第４図は第３図のタイミング図。１：シーケンサ、２：クロツク信号発生器、３
：デイレー回路、４，１１：ラツチ、５：アドレ
スメモリ、６：ランダム・アクセス・メモリ。 FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing diagram of FIG. 1, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a timing diagram of FIG. 3. 1: Sequencer, 2: Clock signal generator, 3
: delay circuit, 4, 11: latch, 5: address memory, 6: random access memory.

Claims

[Scope of utility model registration request]

For the real-time switching function of the delay timing of the clock signal, the clock signal output and the delay value switching timing are monitored, and the logic means for controlling the timing to latch the next cycle timing is provided. A timing generator that makes it possible to reduce the width of the area where clock timing settings are prohibited.