JPS6216695A - Device for signal interpolation of color difference line sequential video signal - Google Patents

Abstract

PURPOSE:To prevent the voluntary deterioration of picture quality by taking the average of corresponding picture elements between adjacent two scanning lines, forming a luminance signal and interpolating the omission of a color difference signal with the corresponded picture element of a horizontal scanning line just before. CONSTITUTION:As for the input picture data, the luminance signal Y is inputted to a terminal 400 and a chroma signal C to a terminal 400. The luminance signal given to the terminal 400 is supplied to an averaging circuit 404 and a 1H delay circuit 406, and at the averaging circuit 404, the addition average of the corresponded picture elements between the adjacent two scanning lines is taken. And is case of a frame video signal, a connection state shown in figure is formed by a switch 412, and in case of a field video signal, it is constituted so as to switch alternately the switch 412 according to a vertical synchronizing signal. On the other hand, the color difference signal is added each of 1H delay circuits 422 and 432 and when the omission of the color difference signal is recognized, switches 428 and 438 are switched and the corresponded picture element at the scanning line just before is outputted.

Description

TECHNICAL FIELD The present invention relates to a video signal conversion device, and more particularly to a signal interpolation device for color difference line sequential video signals.

BACKGROUND ART The color difference line sequential color video signal system is used in electronic still cameras and color difference line sequential color televisions. As is well known, in this method, two types of color difference signals appear alternately for each horizontal scanning line. For example, in some systems, if one scanning line contains one color difference signal RY, the next scanning line that follows it contains the other color difference signal B-Y.

For example, on a magnetic disk used as a recording medium in a certain electronic still camera system, one field of video signals is recorded on one track. On the other hand, in general video monitor devices and hard copy recording devices, an interlaced scanning method of two fields and one frame is generally used. Therefore, when reproducing a video signal from such a magnetic disk and displaying the video on a video monitor device or recording it on a recording medium as a hard copy, it is necessary to convert the field video signal to a frame video signal. .

A common method usually adopted for such field-to-frame conversion involves creating the first and second fields using the same field video signal. In other words, in this method, one field video signal is used to create a first field video signal, and the same field video signal is used to create a second field video signal that is incremented by the first field video signal. .

At this time, the missing one of the luminance signal of the second field and the two types of color difference signals that appear sequentially in the horizontal scanning lines must be interpolated by some method.

However, with interpolation methods in which both the luminance signal and chrominance signal are individually delayed between horizontal scanning lines, the smoothness deteriorates at the edge portions of the image where the level of the luminance signal or chrominance signal changes significantly. Furthermore, the occurrence of false colors may be emphasized due to interpolation of missing portions of the signal, resulting in a reduction in image quality. In other words, in the color difference line sequential method, color difference signals of the same type alternately appear only in every other horizontal scanning line, so false colors are likely to occur. Therefore, it is required to interpolate the signal missing portion of the color difference line sequential video signal without causing such a deterioration in image quality.

OBJECTS In view of these demands, it is an object of the present invention to provide a signal interpolation device for color difference line sequential video signals without significantly reducing image quality.

DISCLOSURE OF THE INVENTION According to the present invention, there is provided an input means for receiving an input video signal including a luminance signal and a color difference signal formed alternately in horizontal scanning line sequence; and a frame consisting of a first and a second field from the input video signal. In a signal interpolation device for a color-difference sequential video signal including a signal interpolation means for forming a video signal, an input video signal is repeatedly input to the input means over a plurality of field periods; Using the luminance signal of the video signal, in the second field, luminance signal interpolation is performed to form the luminance signal of the frame video signal by averaging the luminance signals of corresponding pixels between two adjacent horizontal scanning lines. and the color difference signals of the first and second fields of the frame video signal are configured to replace the color difference signals missing in the horizontal scan line of the input video signal with the color difference of the corresponding pixel in the horizontal scan line immediately before the horizontal scan line. Description of Embodiment of Color Difference Formed by Interpolating Signals Next, an embodiment of the signal interpolation device for color difference line sequential video signals according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, an embodiment in which the present invention is applied to an image print recording device is shown. The image is then reproduced as a hard copy on an image recording medium 12 such as color photographic paper.

In this embodiment, a video signal is recorded on the magnetic disk 10 for one field per track.

This video signal is a one color difference line sequential signal, and the luminance signal and the color difference signal may be FM modulated and recorded on a track, for example. These signals are 1 in 1 field.
It may be a so-called field video signal that makes up a frame, or a so-called frame video signal that makes up one frame with two fields. In the case of a frame video signal, this fact is indicated by a data signal superimposed on the video signal. Advantageously, this data signal is multiplexed onto a video signal in a differential phase shift keying (DPSK) format.

This device has a magnetic disk reading section 14 as a video signal input device. This reads the video signal from the magnetic disk 10, demodulates it, and outputs the brightness (Y) signal and color tone (Y) signal.
C) This is a circuit that separates a signal and a synchronization (SYNC) signal and outputs the former to the signal line 16 and the latter to the signal line 18. In addition, the above-mentioned [1PSK data signal is also read by the reading unit 14, and if a magnetic disk on which a frame video signal is recorded is used, a control line 96 to that effect is used.
It is reported to the overall control unit 26 via. In this embodiment, the color tone signal is in the form of a line-sequential color difference signal. Instead of or in addition to the magnetic disk reading section 14, other video signal input devices such as a magnetic tape reader or a receiving device from a communication line may be provided.

The luminance signal and the color tone signal are converted into corresponding digital data by the analog-to-digital converter (A11G) 20, and input to the interpolator 82 through the signal line 80. The interpolation unit 82 is a circuit that interpolates missing portions of the luminance signal and color difference signal through predetermined arithmetic processing as described later. The signal at the output 88 is output to the decoding section 90.

The decoding unit 80 converts the interpolated video signal into three separated color signals,
For example, it is converted into three primary color signals RGB and outputted to the output 92.

The RGB signals of the output 82 are stored in the frame memory 22 through the switch 24 whose switching is controlled by the overall control section 26. The frame memory 22 consists of two storage units 22A and 22B as shown in the figure.
Video signal data is selectively written to either one by the switch 24.

In this embodiment, the frame memories 22A and 22B are RAMs each having a capacity to store video signal data for one frame. The address of the storage location is controlled by an address counter 84. Further, a memory control signal including write or read control is supplied from the overall control section 26 through a signal line 30.

Address counter 94 consists of two units 94A and 94B corresponding to memories 22A and 22B.

Those step clocks are input to the input synchronization unit 30 in the case of writing.
In the case of reading, the signal is supplied from the output synchronizer 50 through the switch circuit 68. The address counter 84 is
As will be described later, the manner of incrementing differs depending on whether the memory 22 is written or read. The switching and the switching of the switch circuit 66 are controlled by the control line 8 from the overall control section 2B.
It takes place through 7.

The synchronization signal 5YNC separated from the reading section 14 is input to the input synchronization section 30. The synchronization unit 30 receives a synchronization signal 5YN
G to pixel clock PCLK, horizontal synchronization signal H3YNC
: This circuit has a phase-locked loop that creates a synchronization signal such as a vertical synchronization signal VSYNC and outputs it to the output 100, and performs synchronization control of a reading system for reading video signals from the magnetic disk 10. The synchronization signal at output 100 is provided to ADO 20 , interpolator 82 and archer 90 , and to address counter 94 through switch 66 .

On the read output side of the frame memory 22, video signal data is selectively input from the two units to the input 33 of the shift register 102 (FIG. 2) through a switch 32 whose switching is also controlled by the overall control section 26. The image processing section 34 is a central device part of this embodiment.

The overall control section 26 controls the reading section 14 and the input synchronization section 30 through the control line 3B, and the interpolation section 82 and the decoding section 90 through the control line 98.

Switches 24 and 32 are controlled in operation by general control section 26, as symbolically shown by control line 112 in FIG. If so, the other switch 32 or 24 is controlled to be connected to the other memory switch 22B or 22A. That is, when video signal data is written into one memory unit 22A or 22B, the other memory unit I-228 or 22A is controlled so that video signal data is read out.

Referring to FIG. 2, the shift register 102 receives video signal data read out in parallel from either memory unit 22A or 22B through the switch 32,
The output synchronizer 50 is also a parallel-to-serial conversion circuit that responds to the synchronization signal 5YNC received through the control line 52 and sequentially outputs it in series to its output 104. This output 104 is connected to the output image processing section 34.

The output image processing section 34 includes a correction section 106 that performs various image processing such as adjusting the color balance, white balance, gradation, and density of the reproduced image. The present embodiment also includes a scanning line interpolation unit 108 that performs scanning line interpolation, which will be described later. In this image processing, an image processing command input from the operation display section 70 is decoded by the overall control section 2B, a corresponding control signal is applied to the control input 68, and the video signal data is performed in accordance with this.

Referring to FIG. 3, the correction section 10G includes a color correction section 300,
Tone correction section 302 and negative/positive (N/P) inversion section 3
It has 04. The color correction section 300 includes a shift register 10
This is an image processing circuit that receives the output 104 of 2 and corrects the color balance and white balance of the image based on the video signal. Conditions for the correction are set from the overall control section 26 through the control line 68. This condition is based on the operation display section 70
Settings can be made for each frame of the image by operating .

An output 300 of the color correction section 300 is connected to a tone correction section 302. The gradation correction unit 302 is an image processing circuit that corrects the density and gradation of an image based on a video signal. The conditions for the correction are also set from the overall system mg 62e through the control line 68, and can be set for each frame of the image by operating the operation display section 70.

The output 308 of the gradation correction section 302 is
10 to the output line 110 and on the other hand N/P
It is connected to the reversing section 304. NIP inversion layer 0
This is an image processing circuit that inverts the image quality signal of the input 308 and performs gradation correction to match the negative sensitivity characteristics and gradations of photographic paper as the image recording medium 12. The characteristic conditions are also set by operating the operation display section 70 through the control line 88 from the overall control section 28.

The switch 310 is a control w from the overall control section 2B in FIG.
! As symbolically shown at 1j112, the operation is controlled by the control section 28. When reproducing an image of the video signal on the video monitor device 48, the switch 310 takes the illustrated connection state, and the video signal of the output 308 of the gradation correction section 300 is directly output to the output 110. Also recording CRT 4
When playing back to 2, take the opposite connection state as shown and
The video signal of the output 312 of the /P inverter 304 is the output 110
is output to.

The output 110 of the correction section 1 (16) is connected via a switch 114 to the input 116 of the scanning line interpolation section 108 and the input 38 of the digital to analog converter (DAC) 4B.

As shown in FIG. 4, the scanning line interpolation unit 108 includes an averaging circuit 320 and a delay circuit (IHDL) 3 in this embodiment.
22, with input 116 connected to the inputs of these two circuits and switch 324. An output 324 of delay circuit 158 is connected to the other input of averaging circuit 320. The delay circuit 322 is a circuit that sequentially receives video signals at the input 116, delays them by one horizontal scanning period (IH), and sequentially outputs them to the output 326.

The averaging circuit 320 receives video signals sequentially received from two inputs 116 and 326 and is shifted by an IH period from each other.
This is a circuit that performs simple addition and averaging for each corresponding pixel position.

Its output 328 is connected to output line 38 through switch 324.
It is connected to the. The switch 324 is the output synchronizer 50
Horizontal synchronization signal H3YNC received through signal line 52 from
This is a switch whose connection state changes alternately in synchronization with the

Returning to FIG. 2, one output 38 of the image processing section 34 is connected to a switching circuit 118 and a digital ψ analog conversion section (DA
C) It is connected through 40 to a color signal input terminal 44 of a video output device for recording, such as a CRT 42 for recording. The other output 38 is connected to a color signal input terminal 49 of a video monitor device 48 through another DAC 4B. As symbolically shown by a control line 112, the switching circuit 118 selectively selects the three-separated color video signal appearing at the output 3B of the image processing section 34 and outputs it to the output 37 under the control of the overall control section 28. This is a switch circuit.

A synchronizing signal output 52 of an output synchronizing section 50 is connected to the synchronizing signal input terminals of the recording CRT 42 and the monitor device 48. These recording CRT 42 and video monitor device 48 constitute a video output device that visualizes frame video signals.

The output synchronization section 50 has a free-running reference oscillator (not shown) and generates various locks including a synchronization signal 5YNG and a pixel clock PCLK for mainly controlling the recording system of this apparatus. These clocks are sent from the output 54 to the image processing section 34, shift register 102. A clock for incrementing the address counter 94, which is supplied to the DAC:40.46, is generated at the output 51. Output synchronization section 50
is under the control of the overall control unit 26 via a control line 28.

Switches 114 and 310 (FIG. 3) connect control line 11
As symbolically shown at 2, the zero switch whose operation is controlled by the overall control section 26 is placed in the illustrated connection position when outputting an interlaced video signal to the monitor device 48. Further, when outputting video signals to the recording CRT 42 in sequential scanning, that is, in a non-interlaced manner, the connection position is opposite to that shown in the drawing.

As the video monitor device 48, a conventional color CRT video display device is advantageously used. The three-separated color video signal data read out from the frame memory 22 under the control of the control section 28 is processed by the image processing section 34 and supplied to the monitor device 48 in interlaced scanning of two fields and one frame. The speed of the signal is the normal television signal rate, e.g.
A 1780 second interlace with a scan line count of 25 is advantageously applied. A monitor device that is compatible with such a normal color TV signal system is advantageously applied from the standpoint of device configuration and economy. It is also advantageous in that the image is displayed in the same state as the reproduced image displayed on a monitor device normally available to the user.

As the recording GRT 42, a high brightness black and white CRT is advantageously used. The three-separated color signal processed by the image processing unit 34 is
The recording CRT 42 is supplied with non-interlaced data.

In this embodiment, this video signal is of a non-interlace type with a number of scanning lines of 1050 and a frame period of 1115 seconds.

However, the scanning line interpolator 108 may not be provided and the signal line 118 may be directly connected to the input 38 of the DAC 40. In that case, non-interlacing with a number of scan lines of 525 and a frame period of 1/30 seconds is advantageously applied.

The output period of each color separation signal may be, for example, about 1 second for one color separation screen. This output period depends on the light emitting characteristics of the CRT 42, the photosensitive characteristics of the recording medium 12, and the like. For example, the overall control unit 26 reads out the video signal of the R color screen from the frame memory 22, displays it on the recording CRT 42 for about 1 second, similarly displays the G color screen for about 1 second, and finally displays the B color screen. Image recording control is performed so that the image is displayed for about one second.

The video displayed on the display screen 56 of the recording ORT 42 does not suffer from visual difficulties such as flicker. Rather, a non-interlaced method without the possibility of causing scanning line bearing is desirable from the viewpoint of rask elimination. The non-interlaced method is also advantageous in that image processing such as vertical interpolation processing for preventing false colors in images can be easily performed, as will be described later.

In this embodiment, the video signal read out from the frame memory 22 in the order of scanning lines is doubled in the number of scanning lines by the scanning line interpolation unit 108, and is converted into a non-interchangeable signal with a frame period of 1/15 seconds with a number of 1050 scanning lines. C for recording as a race screen
Replayed on RT 42.

The display screen 56 of the recording CRT 42 is connected to the photographing lens 58.
A frame image photographed at , and displayed on the screen 56 is imaged on the photosensitive surface of the recording medium 12 . A color filter 60 for separating three colors is disposed behind the lens 58, and is configured to be alternatively arranged on the optical axis of the lens 58.

Selection of this filter 60 and feeding of the recording medium 12 are performed by a paper feed filter control section 62. The paper feed filter control section 62 is connected to the overall control section 26 via a drive circuit 84.
controlled by These constitute a hard copy forming device that visualizes a frame image and forms a hard copy on the recording medium 12.The overall control unit 26 is a control device that controls and unifies the operation of the entire device, and for example, A processing device such as a microprocessor is advantageously applied. An operation display unit 70 is connected to the control unit 28 and includes a human-powered device such as a keyboard through which the operator inputs instructions to the device, and a display device for displaying the internal status and instructions of the device to the operator. has been done.

The overall control unit 26 includes the frame memory 22 and the image processing unit 3.
4 and other parts of the apparatus, the magnetic disk 10 also reads the video signal, and sequentially records it on the recording medium 12 as a reproduced color image. More specifically, the video signal recorded on one track of the magnetic disk 10 is read by the reading section 14.
is read and demodulated. Missing signals in the luminance signal, chroma signal, and synchronization signal included in the video signal are interpolated by the interpolation section 82, and the interpolation section 82 supplies the interpolated signals to the decoding section 90. This will be explained in detail later.

The interpolated signal is converted into a three-separated color (primary color) signal by the decoding unit 90, and is stored in either frame memory 22A or 2.
It is stored in 2B. At that time, the write position address is
The address counter 84 counts the step clock supplied from the input synchronizer 30 through the switching circuit 66, and is applied to the memory 22A or 22B.

For example, when a video signal for one frame is stored in the memory 22A, it is read out to the image processing unit 34 in a predetermined order, and is recorded on the monitor device 48 at an interlaced TV signal rate. The signals are outputted to the GRT 42 as three-separated color frame video signals using non-interlaced scanning.

The operator operates the operation display unit 70 while looking at the display screen of the monitor device 48, and issues image processing commands as necessary to adjust various image processing control parameters such as the density, color balance, and white balance of the reproduced image. Enter. These commands are decoded by the control unit 28, and adjustment parameters of the image processing unit 34 are primarily controlled in accordance with the commands. The video signal data that has been appropriately image-processed in this way is output 36.
and output to 38.

Until now, the overall control section 26 has been
is controlled to feed the recording medium 12 and set the unrecorded photosensitive surface at the exposure position. Further, the three color separation filters 60 are sequentially and selectively inserted into the optical axis of the lens 58. This selective insertion is performed by the image processing unit 34 by switching the switching circuit 118.
This is done in accordance with the selective output of the three-separated color video signal from the CRT 42 for recording. In this way, three separated color images are sequentially photographed and recorded on the photosensitive surface of the recording member 12, and when these are developed, a color hard copy of one frame image is recorded. It is shown in FIG. Among the image data input from the ADC 20 through the signal line 80, the luminance signal Y is input to the terminal 400, and the chroma signal C is input to the terminal 402.

The terminal 400 is connected to an averaging circuit 404 and a delay circuit (IHD).
L) 406. Delay circuit 40B
The output 408 of is connected to the other input of the averaging circuit 404. The delay circuit 406 is a circuit that sequentially receives the luminance signal at the input 400, delays it by one horizontal scanning period (IH), and sequentially outputs the signal to the output 408.

The averaging circuit 404 is a circuit that simply adds and averages the luminance signals sequentially received from the two inputs 400 and 408 for each corresponding pixel position. Its output 410 is connected to switch 41
2 to the terminal 414. switch 41
2, the connection state is switched by a switching signal received from the overall control unit 26 through the control line 112a. When the reading unit 14 identifies that the magnetic disk 10 is recording a frame video signal based on the DPSK data signal of the magnetic disk 10, the control unit 26 connects the switch 412 to the control line 112a in the illustrated connection state. In the case of a field video signal, a switch 412 is supplied in response to a vertical synchronization signal VSYNC.
Provides a switching signal that alternates between the two. Furthermore, input 4
00 is connected to output 414 through the other connection position of switch 412.

A chroma signal C is input to the terminal 402. Terminal 402
is connected to an input 424 of a delay circuit 422 via a switch 420 responsive to a horizontal synchronization signal HSYNC provided from the output 100 of the input synchronizer 30.

The delay circuit 422 is a circuit that sequentially receives chroma signals at an input 424, delays them by an IH period, and sequentially outputs them to an output 426. Its output 426 is connected to switch 420
It is connected to output 430 through a switch 428 similar to . Input 424 of delay circuit 422 is also connected to output 430 via the other connection position of switch 428 .

Similarly, the other connected position of switch 420 is connected to input 434 of delay circuit 432. Delay circuit 422
receives chroma signals sequentially at input 434 and converts them into 1) 1
This is a circuit that sequentially outputs to the output 436 with a delay of a certain period. Its output 43B is connected to output 440 through a switch 438 similar to switch 428. Input 434 of delay circuit 432 is also connected to output 440 via the other connection position of switch 438 .

Output terminals 414, 430 and 440 of this circuit are connected to the decoding section 80.

The switch 420 is a switch whose connection state is alternately switched in synchronization with the horizontal synchronization signal HSYNC received from the input synchronization section 30 through the control line 100. In this example,
The chroma signals take the form of R-Y and B-Y color difference signals and arrive at terminal 402 in line sequential fashion.

The switch 420 selects R out of such color difference line sequential signals.
The connection state is controlled so that the -Y signal is input to the circuit on the delay circuit 422 side, and the B-Y signal is input to the circuit on the delay circuit 432 side.

The switches 428 and 438 also receive a horizontal synchronization signal H9YNC from the input synchronization section 30 through the control line 100.
This is a switch whose connection state is alternately switched between the illustrated state and the opposite state in synchronization with the above.

In this embodiment, color difference line sequential video signals of the same image are repeatedly read from the magnetic disk 10 over each field period. When the overall control section 26 identifies through the reading section 14 that the video signal of the magnetic disk 10 is a frame video signal, it fixes the switch 412 of the interpolation section 82 in the illustrated connected state.

Therefore, the luminance signal Y is passed to the decoding unit 80 from the output 414 in the same form for both the first and second fields. On the other hand, chroma signal C is transmitted through switches 420, 428 and 438.
Since it alternately takes the illustrated state and the opposite state in synchronization with the horizontal synchronizing signal H3YNC, the same color difference signal R-Y is successively output for two horizontal scanning lines at the output 430. At 440, the same color difference signal B-Y is successively output for each two horizontal scanning lines. In this way, the luminance signal is outputted as is, and the color difference signal is outputted as an output 88 to the decoding unit 80, with the missing portion interpolated line-sequentially.

When the video signal of the magnetic disk IO is a field video signal, the overall control section 2B synchronizes the switch 412 of the interpolation section 82 with the vertical synchronization signal VSYNG so that it takes an alternate connection state. Switches 420.428 and 438
is in synchronization with the horizontal synchronization signal H3YNC and the state shown in the figure,
This and the opposite state are alternated. Therefore, in both the first and second fields, the interpolation section 82 interpolates the missing portions of the luminance signal and chroma signal in units of one horizontal scanning line.

More specifically, as illustrated in FIG. 8A from the first to the sixth horizontal scanning lines, the color difference line sequential video signal supplied to the input 80 of the interpolation unit 82 has the color difference of the portion indicated by the dotted rectangle. Signal is missing. Note that in the figure, subscripts indicate the numbers of horizontal scanning lines.

First, regarding the luminance signal, the luminance signal of the first field uses the luminance signal Y obtained at the input 400 as it is, and the luminance signal of the second field uses the n-th luminance signal obtained at the input 400.
It is assumed that the simple average of the luminance signal Yn-1 of the pixel on the first horizontal scanning line and the luminance signal Yn of the corresponding pixel on the n-th horizontal scanning line is taken. Therefore, the luminance signal of the second field becomes as shown in FIG. Furthermore, the 6th B
In the figure and FIG. 6C, signals surrounded by solid rectangles are interpolated signals.

Next, regarding the chroma signal, as in the case of the frame video signal described above, the same color difference signal R-Y is outputted at the output 430.
Each horizontal scanning line of the book is output, and the same color difference signal B-Y is outputted to the output 440 for every two horizontal scanning lines. This is the same for the first field and the second field.

Therefore, the luminance signal of the first field becomes as shown in FIG. 6B, and the luminance signal of the second field becomes as shown in FIG. 8C, and both are the same.

The video signal with the missing portion interpolated in this way is sent to the decoding unit 90
The signals are converted into three-separated color signals and stored in the memory 22.

In this way, in this embodiment, the chroma signals are the first and second chroma signals.
The same two consecutive scanning lines are used for each field, and for the luminance signal, the first field is left unchanged.
The second field is formed by simply averaging the corresponding pixels of two successive scanning lines. Therefore, one color error is small, the edges of the image change smoothly, and a video signal with relatively high sharpness is formed.

If the chroma signal were configured to undergo averaging processing in the same way, the chroma signal would appear line-sequentially, so the color error due to averaging would become large, and other circuit elements such as a delay circuit would be required for this purpose. The circuit configuration becomes complicated. However, according to this embodiment, it is possible to record and display images of good quality without such noticeable color errors or complication of the circuit.

The overall control unit 26 includes the frame memory 22 and the image processing unit 3.
4 and other parts of the apparatus are controlled to read video signals from the magnetic disk 10 and sequentially record them on the recording medium 12 as reproduced color images. More specifically, the video signal recorded on one track of the magnetic disk 10 is read by the reading section 14.
is repeatedly read and demodulated, and finally stored in either frame memory 22A or 22 in the form of three separated color signals.
It is stored in B. At this time, the address of the write position is incremented by the address counter 94 using the step clock from the input synchronization section 30, and is output to the memory 22A or 22B.

Therefore, in this embodiment, as described above, the missing portions of the 1-field video signal are interpolated by the complementary 1'lJT section 82, and the interpolated portions are stored in the corresponding storage location of the frame memory 22A or 22B.

For example, when a video signal for one frame is stored in the memory 22A, it is read out to the image processing unit 34 in a predetermined order to be described later, and is stored in the video signal device 48 at the TV signal rate. CRT 42 is non-interlaced,
Each is output as a three-separated color frame video signal.

When displaying an image on the monitor device 48, the control unit 26 sets the sweepers 310 and 114 to the illustrated connection positions, and also sets the address counter 94 to increment according to interlaced scanning. So address counter 9
4 steps forward so that the video signal data is sequentially read out from the storage location of the memory 22A or 22B by interlaced scanning. The stepping claw 2 for this purpose is supplied from the output 51 of the output synchronization section 50 through the switching circuit 88. The reading is
The writing is performed from the memory 22A or 22B which is not being written at that time.

This reading is repeated sequentially for every other scanning line,
Video signals are read out using interlaced scanning for the two fields. Therefore, the output 33 of frame memory 22
, the video signals of the first and second fields are read out in increments. Note that the reading of the video signal of the first horizontal scanning line of the second field is started from the pixel that has advanced to the pixel position corresponding to the 0.5H period at the end of reading of the video signal of the final scanning line of the first field. Address counter 94 is set so that

This incremented video signal is transferred to the shift register 1.
02, the signal is converted into a serial signal and provided to the correction unit 10B. The correction unit 106 performs color correction and gradation correction on this video signal according to the conditions set at that time,
Output from switch 310 to output 110. This is fed through switch 114 to DAC: 4B, T)A
It is converted into an analog signal by the C48 and visually displayed on the monitor device.

The operator operates the operation display unit 70 while looking at the display screen of the monitor device 48, and issues image processing commands to adjust various image processing control parameters such as the density, gradation, color balance, and white balance of the reproduced image. Enter as necessary. These commands are decoded by the control unit 2B and sent to the control line 88.
is applied to the correction unit 106 of the image processing unit 34. The adjustment parameters are controlled accordingly. Video signal data that has been appropriately image-processed in this way is output to the output 110.

Instructions for recording onto the recording medium 12 are input from the operation display section 70. When outputting an image to the recording CRT 42, the control section 2B sets the switches 310 and 114 to the opposite connection position as shown. At the same time, the address counter 94 determines the storage location of the video signal data in the memory 22.
is set to advance according to sequential scanning, that is, non-interlaced scanning. Therefore, the address counter 94 increments so as to sequentially read out the video signal data from the storage location of the memory 22A or 22B in a non-interlaced scanning manner. A step clock for this purpose is supplied from the output synchronization section 50. Reading is performed from the memory that is not being written at that time) 22
This is done from A or 22B.

This readout is repeated sequentially for each scanning line, and the video signal is read out in non-interlaced scanning with two fields as one frame. Therefore, one frame of video signal is read out to the output 33 of the frame memory 22 in a non-interlaced manner.

This video signal is converted into a serial signal by the shift register 102 and provided to the correction section 106.

Correction@toe performs color correction and gradation correction on this video signal, and performs N/P inversion and related gradation correction by the N/P inversion section 304. The thus corrected video signal is output from the switch 310. The signal is output to the output 110 and input to the scanning line interpolation unit 108 through the switch 114.

In this embodiment, the aforementioned scanning line doubling is performed in the scanning line interpolation unit 108 to form a non-interlaced video signal with a frame period of 1/15 seconds using 1050 scanning lines.

Referring to FIG. 4, the switch 324 is connected to the output synchronizer 50.
The connection state is alternately switched in response to the horizontal synchronizing signal H9YNC supplied from the terminal. Therefore, the IH video signal that appeared at the input 116 during a certain IH period is directly output to the output 36, and during the next IH, the video signal that appeared at the input 11B during the previous IH period is transferred to the IH by the delay circuit 322. Input 1 to the current IH period with the delayed one
The simple average of the video signal appearing in 16 is calculated by the averaging circuit 32.
What is taken at 0 is output. This is repeated alternately, doubling the horizontal scan line.

The non-interlaced scanning video signal in which the number of scanning lines has been increased in this manner is inputted from the output 36 to the switching circuit 118. At this time, the overall control unit 26 causes the switching circuit 118 to select a video signal of one separated color, for example, an R video signal. As a result, the R video signal among the video signals output from the image processing section 34 is supplied to the recording CRT 42 via the DAC 40, and is visualized on the screen 5B.

Until now, the overall control section 26 has been
is controlled to feed the recording medium 12 and set the unrecorded photosensitive surface at the exposure position. Further, one of the three color separation filters 60 is selectively inserted into the optical axis of the lens 58. This filter is naturally transmitted from the image processing section 34 to the recording CRT.
The one that matches the separated color video signal output to 42 is selected. In this way, one separated color image is recorded as a latent image on the photosensitive surface of the recording member 12.

Next, the overall control unit 26 repeats the same operation without feeding the recording medium 12, causes the switching circuit 118 to select another color of the three separated colors, and records video signals of the other two colors. output to CRT 42. As a result, those images are photographed and recorded in the same frame on the recording member 12. When this is later developed, a color hard copy recording of one frame image is completed. Such sequential scanning results in a recorded image with good rask erasure without the possibility of scan line bearing.

Note that the configuration may be such that the scanning line interpolation unit 108 is not provided;
In this case, the number of scanning lines is not increased; in other words, in this embodiment, a non-interlaced recording image with a frame period of 1730 seconds is formed using 525 scanning lines.

In addition to the image recording method using two CRTs, this device
For example, laser recording method, liquid crystal recording method, thermal recording method,
It can also be effectively applied to various image recording methods such as inkjet methods and electrophotographic methods.

Effects As described above, according to the present invention, the same two consecutive scanning lines are used for both the first and second fields for the chroma signal, and for the luminance signal, the first field is left unchanged, and the second field is left unchanged. It is formed by simply averaging the corresponding pixels of two consecutive scanning lines. Therefore, with a relatively simple circuit configuration, a frame video signal with little color error, smooth changes in image error, and relatively high sharpness is formed, and images of good quality can be recorded.
It can be displayed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a part of an embodiment in which the present invention is applied to an image print recording device, and FIG. 2 is a schematic block diagram showing the remaining part of the embodiment of the image print recording device according to the present invention. 3 is a block diagram showing an example of the configuration of the correction section shown in FIG. 1; FIG. 4 is a block diagram showing an example of the configuration of the scanning line interpolation section shown in FIG. 1; 1 is a block diagram showing an example of the configuration of the interpolation section shown in FIG. 1, and FIGS. FIG. 7 is an explanatory diagram illustrating interpolation of a video signal of one field and a video signal of a second field for first to sixth horizontal scanning lines; Explanation of symbols for main parts 10: Magnetic disk 12, Recording medium 22, Frame memory 2B, Overall control section 34, Image processing section 42, Recording CRT 4E1. ,Video monitoring device 50, ,Output synchronization unit 82, ,Interpolation unit Patent applicant: Fuji Photo Film Co., Ltd. Agent: Kodori Toshio

Claims (1)

[Claims] 1. Input means for receiving an input video signal including a luminance signal and a color difference signal formed alternately in horizontal scanning line sequence; and a frame consisting of first and second fields from the input video signal. A signal interpolation device for color-difference sequential video signals including signal interpolation means for forming a video signal, wherein the input video signal is repeatedly input to the input means over a plurality of field periods, and the signal interpolation means includes a first In the second field, the luminance signal of the input video signal is used, and in the second field, the luminance signal of the frame video signal is calculated by averaging the luminance signals of corresponding pixels between two adjacent horizontal scanning lines. A luminance signal interpolation means for forming the color difference signals of the first and second fields of the frame video signal is configured to replace the color difference signals missing in the horizontal scanning line of the input video signal with the color difference signals of the horizontal scanning line immediately before the horizontal scanning line. 1. A signal interpolation device for a color difference line sequential video signal, comprising a color difference signal interpolation means for forming a color difference signal by interpolating with color difference signals of corresponding pixels in a line. 2. The apparatus according to claim 1, characterized in that the frame video signal is sequentially scanned and outputted to a hard copy forming means for forming a hard copy of an image according to the frame video signal. signal interpolation device. 3. The signal interpolation device according to claim 1, wherein the frame video signal is visualized by interlaced scanning on a video monitor means. 4. The signal interpolation device according to claim 1, wherein the input video signal is recorded on a magnetic disk, and the input means reads the input video signal from the magnetic disk.