JPS6216289A - Read only memory - Google Patents

Abstract

PURPOSE:To unitedly input a chip selecting signal with an address signal and to decrease the number of terminals of ROM by sharing both terminals for selecting the address and the chip. CONSTITUTION:At terminals I0-I7 of a case 1 of a ROM, address signals A17A16...A1A0 are impressed ranging to timings t0-t2, and a part A17A16 of the address signal and chip selecting signals CS1-CS3 are impressed at the timing t2. Thus, the chip selecting signal can be unitedly inputted with the address signal, and the number of the terminals can be decreased by the sharing of the terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only memory, and more particularly to a read-only memory using an address multiplexing method with a chip selection mode and a chip non-selection mode.

[Conventional technology]

In a read-only memory (hereinafter referred to as ROM), an address multiplexing method is sometimes used to reduce the number of address signal input terminals. In addition, recently it has become common for one CPU to use multiple RUMts, so in order to select one of them with the chip selection signal, the chip selection mode and chip non-selection mode can be switched using the chip selection signal. There is a ROM that allows you to

Conventional ROMs have separate address signal input terminals and chip selection signal input terminals.

[Problem that the invention seeks to solve]

Chip selection (
If it could be handled in conjunction with the address signal of the IT t-ROM, multiple ROMs could be used together with one address signal whose number of bits is the sum of the number of bits of both signals, but conventional ROM! Since both signals are input from different terminals, it is inconvenient that both signal input lines cannot be connected in the same way. Furthermore, although the address multiplexing method is used to completely reduce the number of terminals, the number of terminals serving as chip selection signal input terminals remains the same.

As explained above, the conventional RO has a chip selection mode and a chip non-selection mode and uses an address multiplexing method.
M has the disadvantage that it is inconvenient to handle the chip selection signal together with the address signal, and also has the disadvantage that the number of terminals as for the chip selection signal input terminal remains the same as before.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, to provide a ROM'i in which a chip selection signal can be inputted together with an address signal, and which has a small number of terminals.

[Means for solving problems]

The read-only memory of the present invention has a chip selection mode and a chip non-selection mode and uses an address multiplexing method, and is configured so that an address signal input terminal is commonly used as a chip selection signal input terminal.

〔Example〕

, Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram for explaining the operation of an embodiment of the present invention.

This embodiment is a ROM having a storage capacity of 256 words x 8 bits, and has eight terminals I, -F for inputting address signals and chip selection signals.

256X1024=2 so the address signal is 18
Bits and Nasi, this trick (A17 A16...A
t A6). As an example, assume that the chip selection signal is 3 bits, which is expressed as (C83・cs, -C8,)
It is expressed as

Address signal (A1.A, 6...AI AO)
and terminals via an 8-bit bus (not shown). ~I7 to timing t0 as shown in FIG.
・Enter in 11-1 and 03 times. The chip selection signal (C81, C8tomi, C51) is the address signal (A
The timing t2 corresponds to the digit above the most significant digit of I, Al, ... At Aa).
Input from terminal work 2 to work 4. The input chip selection signal (C8s
・CS, ・C8,), that is, timing 1. to terminal I
,~Step 4 The embodiment of the nine-bargain where the patterns of the signals inputted from Since this ROM uses a method of sharing the address signal input terminal with the chip selection signal input terminal, when inputting the address signal and chip selection signal from the data bus, the chip selection signal can be treated as part of the address signal. In addition, the data bus that inputs these signals can be directly connected to the address signal input terminal, so there is no need for external parts, and the number of terminals can be reduced. This has the advantage that an inexpensive case can be used.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the operation of an embodiment of the present invention. 1, -47: Yoko (/1/7 Att ------At Aa): Attles 7g9αtsu3・C52・C3t) -Natsutsu selection number tθ~! 2:y imi > 7°′ grass I flash

Claims (1)

[Claims] A read-only memory that has a chip selection mode and a chip non-selection mode and uses an address multiplexing method, characterized in that an address signal input terminal is shared as a chip selection signal input terminal. .