JPS62160518A - Reset signal control circuit - Google Patents

Abstract

PURPOSE:To prevent an MPU (central processing unit) from being reset on the way of operation even if a power failure is restored to apply an external power, by providing a means which inhibits a reset signal to the MPU when the MPU is operated during the power failure. CONSTITUTION:If a power failure occurs, a detecting circuit 5 detects the reduction of the supply voltage to set an FF 3 and sets an MPU 3 to the stand-by mode. When a user hooks off a handset at this time for the purpose of performing data communication, the MPU 2 and the FF 3 are reset. If an external power source is restored when the MPU 2 is operated at this power failure time, the power-on reset function is operated as normal, and a signal (g) goes to '0', and an output signal (f) of an OR circuit 6 goes to '1'. However, a NAND gate 1 is set to the reset inhibiting state by the output of the FF 3, and the reset signal is not outputted to the MPU 2, and consequently, the executing operation of the MPU is not released.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reset signal control circuit in a device incorporating a microprocessor or the like.

Conventional Technology Conventionally, computer systems and various devices incorporating microprocessors have built-in backup batteries, so that important data can be erased even if a power outage or power line disconnection occurs during operation. Some devices are designed to prevent this from happening. In other words,
For example, when the external power supply is cut off, the CPU (Central Processing Unit) shifts from normal operating mode to data retention mode, and retains the data in the memory device without accepting commands from the outside until the external power supply is restored. The data retention mode was maintained.

By the way, generally when this type of device is turned on,
It was necessary to set the CPU to an initial setting state in which all unnecessary data was erased. Therefore, when external power is applied, a reset signal is always sent to the CPU and the CPU is set to an initial setting state, that is, a power-on reset configuration is adopted.

Problems to be Solved by the Invention In such a device, if you want to perform a certain operation during the data retention mode, for example, a multi-function telephone that has an automatic dialing function, a data terminal, and a document creation function to create document data to be sent, etc. If you want to operate only the telephone function and its automatic dialing function with the power switch turned off because no external power is applied to the device or the document creation function is unnecessary, use the backup This is possible if the CPU is operated using a battery.

However, in such a configuration, since the power-on reset configuration is used as described above, there is a delay while searching for the data of the desired dial number and while sending dial pulses to the telephone line according to the data. When an external power supply is applied due to restoration of a power outage, etc., there is a possibility that the CPU will be set and the operation will be interrupted midway, which is very inconvenient.

The present invention has been made in view of the above problems, and prevents the CPU from being reset even if external power is applied during a certain operation in data retention mode. The purpose of the present invention is to provide a reset signal control circuit that can perform the following functions.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a storage means for storing power drop information based on a data retention mode (hereinafter referred to as standby mode) shift command signal generated when the external power supply is cut off. , prevents the input of a reset signal to the microprocessor in a state where power drop information is stored in the storage means, and prevents input of a reset signal to the microprocessor in a state where power drop information is not stored in the storage means; A gate means is provided to allow the power supply to pass, and the power supply drop information in the storage means is erased in accordance with an output signal of the gate means.

Effect: With this configuration, when the power is turned off, power drop information is stored in the storage means, and the gate means enters the passing state, allowing the MPU to be reset and telephone operations to be performed even in standby mode. When starting the operation, a reset signal is once applied to the MPU, and at that time, the power drop information in the storage means is erased, the gate means is cut off, and the reset signal is not applied during the operation. You can choose not to add Uke.

Embodiments Hereinafter, embodiments in which the reset signal control circuit of the present invention is used in a multi-function telephone device will be described with reference to the drawings. FIG. 1 shows a reset signal control circuit and peripheral devices in this embodiment-1.

1 is a NAND gate inserted into the reset signal line.

2 is a microprocessor (hereinafter referred to as MPU). MPU2 has a reset signal (hereinafter referred to as RESET)
An input terminal is provided to which a reset signal line from the N.A.N.D. gate 1 is connected. The MPU 2 also has input terminals such as a standby mode transition command signal (hereinafter referred to as 5 TBY) input terminal and a non-maskable interrupt signal (hereinafter referred to as NMI) input terminal. Furthermore, the MPU 2 is internally equipped with 110 ports, and one of the terminals of the I10 ports serves as an output terminal for a signal (hereinafter referred to as 5TBYOUT) instructing transition to standby mode.

3 is a flip-flop circuit that stores the standby mode, and the set input terminal S is the 5TBYOU of MPU2.
The reset input terminal R is connected to the T output terminal, and the reset input terminal R is connected to the MPU2
It is connected to the reset signal line leading to the RESET input terminal of. Also, the output terminal Q of the flip-flop circuit 3
is connected to control circuit 1, and its inverted output terminal is connected to M
It is connected to the 5TBY input terminal of PU2.

4 is a battery for data retention and operation during power outages, and supplies power to each circuit. Reference numeral 5 denotes a voltage drop detection circuit (hereinafter referred to as a detection circuit) that detects a voltage drop in the external power supply, and upon detecting a voltage drop, transmits an interrupt signal to the NMI terminal of the MPU 2. 6 is an OR circuit, which receives a power-on reset signal from the power supply circuit, and a standby state m;
receives an operation request signal input by the user.Then, its output signal line is connected to the input side of the NAND gate 1.However, the input side of the OR circuit 6 is illogical. .

Next, a multifunction telephone device equipped with a reset signal control circuit according to this embodiment will be explained based on FIG. In addition to its function as a telephone device, this multifunctional telephone device has functions such as a data terminal device and a document creation device for creating documents to be sent to the other party.

7 is a NAND gate 1° flip-flop circuit 3, as explained above. This is a reset signal control circuit including an OR circuit 6. 8 includes the aforementioned detection circuit 5, and the power supply line PW1. This is a power supply circuit for supplying power supply voltage to each part of this device via PW2. The power line PWI is
MPU2. Reset control circuit 7. Telephone circuit 10. RAM
17° and the keyboard 25. A backup battery 4 is connected to the power line PWI. On the other hand, the power line PW2 supplies power voltage to other devices. 9 is a power switch of this device, which is the 0 switch of the external power supply supplied to the power supply circuit 8.
Perform N10FF.

1o is a telephone circuit to which a telephone line is connected and performs operations such as sending out a dial signal, amplifying a voice signal, and generating a ring tone under the control of the MPU 2. A MODEM circuit 11 operates in a data communication mode and modulates a carrier signal with data sent from the MPU 2. The input/output signal line of the MODEM circuit 11 is connected to the telephone circuit 1o.

12 is the I10 port provided in the MPU 2 as described above and used exclusively for telephone circuit control. Also,
13.14 is the CPU (central processing unit), RAM (random access memory), and ROM provided in MPUZ.
(read-only memory).

16 and 17 are ROs for storing programs related to each function, document data created in document creation mode, document data sent via telephone line, etc.
M, and RAM.

18 is an I10 port for outputting print data to an externally attached printer, and 19 is an I10 port provided for data input/output with other devices via an R8232C terminal.
There are 10 boats.

20 controls a floppy disk drive device 21;
This is a disk drive control circuit for writing and reading data to and from the device. 22 is a CRT control circuit for displaying created documents, a list of stored telephone numbers, etc. on the CRT display device 23;

A keyboard 24 is used for issuing operation commands to the apparatus or inputting document data when creating a document. 25 is a keyboard equipped with a numeric keypad dedicated to inputting numerical data and function keys for issuing operation commands. 26 is a handset connected to the telephone line 10.

The operation of the multifunction telephone device configured with the reset signal control circuit as described above will be explained below based on the timing diagram of FIG.

It is assumed that the power switch 9 is now turned on, external power is supplied, and normal power supply voltage is applied to the MPU 2 and other devices. It is assumed that this device is performing normal operation in an operation mode such as document creation.

If a power outage occurs at this time, the detection circuit 5 detects that the power supply voltage has decreased, and as shown in FIG.
The signal a input to the MI terminal is set to O to instruct the MPU 2 to perform interrupt processing. After MPU2 performs the necessary processing based on this interrupt signal, it enters standby mode at 5T.
Set BYOUT output to 1. The flip/70-tub circuit 3 is set by the rise of this output, and the output of the inverting output terminal Q becomes O, causing the MPU 2 to go into standby mode. In standby mode, the MPH1 does not back up document data, etc. and waits for power to be restored. At the same time, the output d of the output terminal Q becomes 1, the NAND gate 1 is closed, and the MPU 2 becomes in a resettable state. In this state, the MPU 2 cannot output a control signal to the outside and performs internal memory retention.

Here, when the user feels the need to talk to the other party for data communication and picks up the handset 26, the telephone circuit 1
The operation request signal e from 0 becomes 0, and the output f of the OR circuit 1 becomes 1. Since the NAND gate 1 is closed, its output is the inverse of f, that is, 0.

When h becomes O, the MPU 2 is reset. At the same time, the flip-flop circuit 3 is reset, the output C becomes 1, and the standby mode of the MPU 2 is released. The MPU 2 then starts operating and performs various operations in the telephone mode according to the program.

Also, by resetting the flip-flop circuit 3, Q
The output d becomes 0, and the NAND gate 1 is released, that is, reset is prohibited.

During such a power outage operation, for example, even if the telephone function is working as in this example, when the external power is restored, the power-on reset function will work as usual, the signal g will become O, and the output of the OR circuit 6 will be activated. The signal f becomes 1. However, NAND
The gate 1 is in a reset prohibited state due to the output of the flip-flop circuit 3, and a reset signal is not output to the MPU 2, so that the signal remains at 1. Therefore, the operation being executed by the MPU 2 is not canceled and continues to operate.

However, the output a of the detection circuit 5 becomes 1, indicating that the external power supply has been restored, and the normal operation continues without performing an interrupt operation.

If the call ends before the external power is restored, the rMPU
2i; again set the 5TBYOUT (7) signal to 1,
The flip-flop circuit 3 will be set.

Effects of the Invention As described above, the present invention provides a storage means for storing power drop information in response to a data retention mode shift command signal generated when an external power supply is turned off, and a storage device in which the power drop information is stored in the storage means. Gate means is provided for blocking the input of a reset signal to the microprocessor and for passing the reset signal to the microprocessor in a state in which power drop information is not stored in the storage means, and according to the output signal of the gate means. By configuring the storage means to erase the power drop information, when the external power supply is turned off, the gate means enters a passing state, and the MPU is reset and operates even when the external power supply is turned off. In addition to this, once a reset signal is applied to the MPU in this state, the gate means is cut off and no further reset signals are received, thereby preventing power outages, etc. If an operation is being performed with no external power applied, even if the external power is applied during the operation due to recovery from a power outage, etc., a reset signal will be applied when performing that operation. Therefore, it is possible to prevent the CPU from being reset again during the operation.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a reset signal control circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of a multi-function telephone device equipped with the reset signal control circuit, and Fig. 3 is a circuit diagram of the reset signal control circuit. FIG. 3 is a timing diagram showing the operation. 1, , NAND gate 264. Microprocessor - (shown as MPU in the figure) 300. Flip-flop circuit 439. Battery 501. Voltage drop detection circuit 6... OR circuit Name of agent Patent attorney Toshio Nakao and one other person Figure 1 Figure 2

Claims (1)

[Claims] A storage means that is operated by a backup battery and stores power drop information in response to a data retention mode transition command signal generated when the external power supply is turned off; and a storage means that stores power drop information in the storage means according to the information stored in the storage means. gate means is provided for blocking input of a reset signal to the microprocessor in a state in which the power-down information is stored in the storage means, and for passing a reset signal to the microprocessor in a state in which power-down information is not stored in the storage means; A reset signal control circuit, characterized in that the reset signal control circuit is configured to erase the power drop information in the storage means in accordance with the output signal of the means.