JPS62152291A - Picture memory device - Google Patents

Abstract

PURPOSE:To reduce the deterioration in picture quality by interpolating vertically a sample point a lacking at the time of reading from a memory by data one line to quncuneially sampled data and outputting the result. CONSTITUTION:By a TV synchronizing signal generating circuit 11, a horizontal reading address generating circuit 10 and a vertical reading address generating circuit 9 are operated. The output of the circuit 9 passes through an address converting circuit 8 and is supplied to the memory 5 to read the memory in the sequence of the addresses. In the second field, when the output of the circuit 10 is an odd number address, the operation for sibtracting '1' from an address value of the circuit 9 is carried out by the circuit 8, and when the output is an even number address, the circuit 8 is passed through. The data read from the memory 5 is converted in a dA converter 13 and data read from a memory 7 is converted in a DA converter 14, respectively and fd to an output circuit 15.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention converts an analog video signal into a luminance signal and two types of color difference signals, performs pulse code modulation, and then reads out the signal recorded on a recording medium as a digital video signal. The present invention relates to an image memory device for displaying images.

Conventional technology In recent years, audio and video signals have been pulse-code modulated and recorded on a disk-shaped recording medium (hereinafter referred to as a disk) as a spiral or concentric focused row, and changes in the intensity of light or electrostatic capacitance have been developed. Methods for detecting and reproducing signals are being actively developed. Among these, many methods have been proposed for recording not only music signals but also characters, graphic ink images, and color still images on digital audio discs.

FIG. 3 shows a block diagram of a conventional image memory device. In FIG. 3, 31 is a write control circuit, 32 is a write address generation circuit, 33 is a data input circuit, 34 is an address switching circuit, and 35, 36, and 37 are Y, R-, respectively.
Memory for Y and B-Y data, 38 is a read address generation circuit, 39 is a TV synchronization signal generation circuit, 40, 41.42 is a digital-to-analog converter (hereinafter abbreviated as DA converter)
, 43 is an output circuit.

The operation of the image memory device configured as described above will be described below. FIG. 4 is a schematic diagram showing the process that image data goes through from original data to arrangement on the screen. For simplicity, it is assumed that the image data is composed of 8 dots in the horizontal direction and 8 lines in the vertical direction.

As shown in Figure 4 (al), the original data is sampled at the same position in the vertical direction in the first and second fields. Furthermore, it is time-division multiplexed with a luminance signal, two types of color difference signals, etc.The reproduced data is sent to the data input circuit 33 through the write control circuit 31 shown in FIG. to initialize the write address generation circuit 32.The data input circuit 33 operates to distribute the luminance signal Y and the color difference signals R-Y and B-Y to the memories 35, 36, and 37, respectively.Write address generation The circuit 32 sequentially generates an address for each memory, and only when writing, switches the address switching circuit 34 to the write address side and writes to each memory.For example, focusing on the memory 35, the written data is the first address in the memory. It is as shown in Figure 2 (bl).

During reading, the TV synchronization signal generation circuit 39 generates horizontal and vertical synchronization signals, and in synchronization with these, the read address generation circuit 38 generates a read address. The data read from each memory 35, 36, 37 is converted into an analog signal by a DA converter 40, 41, 42, and sent to a display device through an output circuit 43.

The data on the screen of the display device is as shown in Figure 4 (C).
The original data will be played back.

Problems to be Solved by the Invention In such a conventional configuration, there is a problem that the number of memories increases, making it impossible to reduce the price. However, there was a problem in that the memory readout circuit became complicated. In the explanation of the conventional example, an image of (8 dots l-)
), (B-Y) each having 8 bits can be considered as an example. Calculating the number of bits in this case is 512X 512X 8 x 3 = 62914
It becomes 56 (bi-nod). This is a commercially available 64 RA
When calculating the number when M is used, 96 pieces are required.

Taking advantage of the fact that the visual characteristics of the human eye are incapable of recognizing color difference signals in a small area, we set the sampling frequency to 1/4 and the number of horizontal dots to 128 only for (RY) and (B-Y). But bit a is 512x 512x 8 + 128
x 512 x 8 x 2 = 3145728 (bits), and if 64KRAM is used, 48 bits are required.

Furthermore, if the number of horizontal dots is not a power of 2, the address lines cannot be separated for horizontal and vertical addresses, so for example, when attempting to read information on one line in the vertical direction, address calculation is required every time. , the memory read circuit becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image memory device that can significantly reduce memory capacity, cause little deterioration in image quality, and simplify memory peripheral circuitry.

Means for Solving the Problems The image memory device of the present invention is configured to separately pulse code modulate a luminance signal and two types of color difference signals of color image information, store them in a memory, and display them. There is a memo 'J tr write circuit that can write the data to any address on the memory, and a memory that has a power of 2 dots a in the horizontal direction for each of the luminance signal and two types of color difference signals. The capacity ratio of the three types of memory is expressed as an integer ratio, and holds data sampled at points where the phase of the first field sample point and the second field sample point differ by 180 degrees out of one frame's worth of image information. an image memory circuit;
A horizontal successive address generation circuit generates a horizontal address for reading data from the image memory circuit in synchronization with a synchronization signal sent to a display device, and a vertical successive address generation circuit generates a vertical address according to the value of the horizontal address. The present invention is characterized in that it includes an address conversion circuit that performs arithmetic processing on vertical addresses to convert the addresses.

Effect: With this configuration, when data is sampled in which the phases of the sample points of the first field and the second field differ by 180 degrees, that is, so-called quincunx sampled data is captured into the memory, and data is successively extracted from the memory in order to increase the horizontal resolution. The position of each dot one line below in the vertical direction (when viewed in one frame)
By reading out the data again at the time, there is little deterioration in image quality, and the memory capacity can be reduced to 172 compared to the conventional one. Furthermore, since the number of dots in the horizontal direction is a power of 2,
When reading again at a position one line lower in the vertical direction, the horizontal address is the same address in the vertical direction, so address calculation is not necessary, and the hardware of the memory read circuit is simplified.

EXAMPLE Hereinafter, an example of the present invention will be explained based on FIGS. 1 and 2. FIG. 1 is a block diagram of an image memory device according to an embodiment of the present invention, where ■ is a four-speed control circuit, 2 is a write address generation circuit, and 3 is a data input circuit.
2.3 can be replaced all together with one microcomputer. 4 is an address switching circuit for switching between a read address and a write address; 5, 6.7 are memories for storing image information; here, for convenience of explanation, memory 5 is a memory for the luminance signal Y, and memory 6 is a memory for the color difference signal (R). -Y)
It is assumed that the memory 7 is a memory for color difference signals (B-Y).

8 is an address conversion circuit for converting read addresses, 9 is a vertical successive address generation circuit, 10 is a horizontal successive address generation circuit, 11 is a TV synchronization signal generation circuit, 12.13.1
4 is a DA converter that converts Y, (RY), and (B-Y) into analog signals, and 15 is an output circuit for synthesizing video signals to be output to a television or the like.

FIG. 2 is a schematic diagram showing the process that image data goes through from original data to arrangement on the screen. For convenience of explanation, it is assumed that one image data is composed of 8 dots in the horizontal direction and 8 lines in the vertical direction.

As shown in FIG. 2(a), the sampling positions of the original data are out of phase by 180° between the first and second fields. It would be better to do this as shown in Figure 2 (al.
This is to reduce the amount of information since image data generally has a large amount of information, and the quincunx arrangement allows for wide horizontal and vertical resolution at the expense of resolution in the diagonal direction in terms of spatial frequency. It is assumed that the data is recorded on the recording medium in the numerical order shown in FIG.
At the same time, the screen synchronization signal is detected and the address of the write address generation circuit 2 is initialized. The data that is actually reproduced is three types of data: a luminance signal Y, a color difference signal (R-Y), and a color difference signal (B-Y) that are time-division multiplexed and reproduced. memory 7
It is necessary to allocate to This operation is carried out by the data input circuit 3. However, since the above matters are not related to the requirements of the present invention, we will focus only on the memory 5.

The reproduced data is written into the memory 5 in the arrangement shown in FIG. 2(b). That is, data for one horizontal section is written at every other address of the memory, and data for the next horizontal section is written at the skipped address. The write address generation circuit 2 sequentially generates addresses as described above, switches the address switching circuit 4 to the write address side only at the time of writing, and writes into the memory. In this way, data is finally written into the memory 5 in the order shown in FIG. 2(b).

Next, during reading, the TV synchronization signal generation circuit 11 generates a horizontal synchronization signal and a vertical synchronization signal, and in synchronization with these, the horizontal successive address generation circuit 1o and the vertical read address generation circuit 9 are operated. Since the horizontal dots 9 are made to be a power of 2, the horizontal address lines and vertical address lines can be physically separated. To read the first field, as shown in FIG. 2(C), the memory in the figure (bl) is read out in address order as is. Therefore, the output of the vertical address generation circuit 9 is passed through the address conversion circuit 8, and the address is It is given to the memory 5 without being converted. In the second field, it is read as shown in FIG. The address conversion port B8 subtracts 1 from the address conversion port B8, and when the horizontal successive address is an even number, the address conversion circuit 8 is passed through.

Given the memory address as described above, the data read from the memory 5 is sent to the DA converter 12, the data read from the memory 6 is sent to the DA converter 13, and the data read from the memory 7 is sent to the DA converter 14. Then, each signal is digital-to-analog converted and sent to the output circuit 15. Output circuit 1
When the video signal output from 5 is displayed on a TV, the data is arranged as shown in FIG. 2 (el), and image quality deterioration is relatively suppressed.

The number of reproduction dots in the horizontal direction of the luminance signal is 512, the number of reproduction dots in the vertical direction is 512 lines, and the sampling frequency of the color difference signal is 1 of the luminance signal.
74, and each dot has 8 bits, the number of bits for the entire screen is 256 x 512 x 8 + 64 x 512 x 8
x 2 =1572864 (bits), and if 64KRAM is used as memory, only 24 bits are required.

As described in the detailed description of the invention, the image memory device of the present invention is capable of interpolating missing sample points when reading quincunx sampled data from the memory with data on one line in the vertical direction and outputting the interpolated data. By installing a memory continuous circuit like this, even though the image information is 172, it is possible to reproduce images with less deterioration in image quality, and the memory capacity is also lower than the conventional 172.
It can be set to 2. Furthermore, the number of dots in the horizontal direction is increased to 2.
Because it is a power of It also has the effect of making it easier to wear.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image memory device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of the main parts of FIG. 1, FIG. 3 is a block diagram of a conventional image memory device, and FIG. It is a schematic diagram of the main part. 2...Write address generation circuit, 5, 6.7...
...Memory, 9...Vertical read address generation circuit, 10...Horizontal read address generation circuit, 8
...Address conversion circuit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1! Figure 2 (α) Figure 3 Figure 4

Claims (1)

[Claims] A memory write circuit for writing input data in which the luminance signal and two types of color difference signals that constitute color image information are separately pulse code modulated to any address on the memory, and the luminance signal and the two types of color difference signals. The capacity ratio of the three types of memory is expressed as an integer ratio, and the sample of the first field of image information for one frame is a memory circuit that holds data sampled at a point where the phase of the point and the sample point of the second field are different by 180 degrees; and a horizontal address and a horizontal address for reading the data of the memory circuit in synchronization with a synchronization signal sent to the display device. An image memory device comprising a horizontal read address generation circuit and a vertical read address generation circuit that generate vertical addresses, and an address conversion circuit that performs arithmetic processing on the vertical address according to the value of the horizontal address to convert the address.