JPS6215159B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates to electronic timing devices. The electronic timer is provided with an information storage section, and timer information inputted by an external designation operation is stored in this storage section. In such a case, the timer information is in a normal form (for example,
For 12-hour format, the time must be between 1:00 and 12:59, and AM and PM must be specified. Moreover, there must be specification of operation control information for the controlled object, such as time switch on/off information. ). If the timer information is not in a normal format, it is necessary to prohibit the timer information from being stored in the information storage section. Conventionally, this type of electronic timer is known to prohibit the timer information from being stored in the information storage section if the timer information is not in the correct format; There is no way to notify the operator whether or not it has been stored in the storage unit, and as a result, the operator may have made a mistake in specifying the timer information and set the timer information even though it was not set in the information storage unit. There was a problem that made me look at it. Based on this, it has a function to determine whether the specified timer information is normal or not, and when the timer information is normal and set in the information storage section, the display on the display section is switched, and when the timer information is abnormal, it is set in the information storage section. If the timer information is not set correctly, it may be possible to let the operator know whether or not the timer information has been set correctly by leaving the display as is. There is a problem in that it is difficult to tell which part of the timer information is abnormal just because the display does not change. Particularly recently, timer devices that can set timer information on a weekly basis have been developed, and in such devices, the day of the week designation is also included as a component of the timer information, so it is difficult to determine which part of the timer information is abnormal. Not knowing this means there is an operational problem. This invention was made in view of the above points, and when there is an abnormality in the specified timer information, it is possible to determine which part of the timer information the abnormality is in and to notify the user by displaying the abnormal part. It is an object of the present invention to provide an electronic time limit device that can improve operability and ensure information re-designation operations. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the basic circuit configuration of the entire device, where 1 is a 4-bit 1-chip microcomputer. This computer 1 is an input terminal
An oscillator 2 is connected to OSC1 and OSC2 to obtain a basic operating clock. Further, this computer 1 has an initialization circuit 3 connected to an input terminal INIT, so that when the entire device is powered on, the initialization circuit 3 starts execution from a specific command part. The microcomputer 1 is provided with 4-bit parallel input terminals K ₁ , K ₂ , K ₄ , K ₈ as input terminals, and 8-bit parallel output terminals O ₀ , O ₁ , O ₂ , O ₃ as output terminals. ，
O ₄ , O ₅ , O ₆ , O ₇ and independent 16-bit output terminals R ₀ , R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , R ₆ ,
_R7 , _R8 , _R9 , _R10 , _R11 , _R12 , _R13 , _R14 , and _R15 are provided. A waveform shaping section 4 is connected to the input terminal _K8 , and a time reference signal obtained by shaping the commercial power frequency into a rectangular wave is input thereto. Lines l ₁ , l ₂ , l ₃ connected to the input terminals K ₁ , K ₂ , K ₄ and the output terminals R ₂ , R ₃ , R ₄ ,
Lines connected to R ₅ , R ₆ , R ₇ , R ₈ , R ₉ , R ₁₀
l ₄ , l ₅ , l ₆ , l ₇ , l ₈ , l ₉ , l ₁₀ , l ₁₁ , l ₁₂ constitute a matrix circuit, and the intersection part of the circuit has “0/
EW” “1/MON” “2/TUE” “3/WED”
"4/THU""5/FRI""6/SAT""7/
SUN” “8/M-F” “9/M-S” “AM/11”
"PM/12""ON1""OFF1""ON2""OFF
2” “ALARM” “SNOOZE” “CLEAR”
"INPUT""STOP""WEEK""CALL""SET"
Key switches corresponding to the 26 keys "TIME ADJ." and "CLOCK" are arranged as shown in the diagram. Among these 26 keys, "CALL" and "SET"
The four "TIME ADJ." and "CLOCK" form each mode changeover switch of the mode selection section 5, and the remaining 22
These form an information/signal input section 6 for timer information, time information, clear signals, transfer signals, etc. Between the output terminal R ₁₁ and the input terminal K ₁ is an open/close type 5
A 0/60Hz frequency selection switch 7 is connected. The output terminals R ₂ -R ₈ are also connected to the grid of the fluorescent display 8. The output terminals 0 ₀ to 0 ₇ and the output terminals R ₀ , R ₁ , R ₁₂ are connected to each segment of the fluorescent display 8. That is, the fluorescent display 8 has a seven-digit configuration as shown in FIG. 2, and the first digit display section 8-1 has a seven-segment numerical display element 8-1.
a, 1-segment sound signal mark display element 8-1
b. A 1-segment Sunday display element 8-1c is provided, a 7-segment numerical display element 8-2a, a 1-segment weekly operation mark display element 8-2b, and a 1-segment weekly operation mark display element 8-2b are provided in the second digit display section 8-2. A Saturday display element 8-2c is provided. Further, the third digit display section 8-3 includes a 7-segment numerical display element 8-3a and a 1-segment Friday display element 8-3.
b. A 1-segment decimal point display element 8-3c is provided, a 7-segment numerical display element 8-4a and a 1-segment Thursday display element 8-4b are provided in the fourth digit display section 8-4, and The 5th digit display section 8-5 has a 2-segment colon display element 8-5.
5a and a one-segment Wednesday display element 8-5b are provided. Further, the sixth digit display section 8-6 is provided with a 7-segment numerical display element 8-6a, a 1-segment Tuesday display element 8-6b, and a 7-segment numerical display element 8-6a and a 1-segment Tuesday display element 8-6b.
The digit display section 8-7 has a 7-segment numerical display element 8-7a and a 1-segment Monday display element 8.
-7b is provided. The grids of the respective digit display sections 8-1 to 8-7 are connected to digit terminals _G1 to _G7 , respectively. In each segment of the digit display sections 8-1 to 8-7, the a segment of the numerical display element is connected to the terminal a, the b segment is connected to the terminal b, the c segment is connected to the terminal c, and the d segment is connected to the terminal a. is connected to terminal d, and e
The segment is connected to terminal e, the f segment is connected to terminal f, and the g segment is connected to terminal g. Two segments of the colon display element 8-5a are connected to the terminal f, and a segment of the decimal point display element 8-3c is connected to the terminal Dp. Furthermore, each day of the week display elements 8-1c, 8-2c,
8-3b, 8-4b, 8-5b, 8-6b, 8-
7b is connected to the terminal w, and the alarm display element 8-1b
segment is connected to terminal AL, and the segment of weekly operation mark display element 8-2b is connected to terminal AL.
Connected to EW. Then, _the digit terminals G1 to G7 are connected to the output terminals _R2 to _R8 of the microcomputer 1, respectively, and the terminals a to g and Dp are connected to the output terminals _{O0 to O7, respectively} . There is. Also, the terminal for output terminal R ₀
AL, a terminal EW is connected to the output terminal _R1 , and a terminal w is connected to the output terminal _R12 . With such a circuit configuration, the fluorescent display 8
is dynamically displayed by the microcomputer 1. In addition, a diode 9 for preventing a signal from being passed around from the key matrix to the fluorescent display 8 is inserted in the lines _l4 to _l10 connected to the output terminals _R2 to _R8 in the polarity shown. .
Further, the input terminal of the alarm frequency oscillation section ₁₀ is connected to the output terminal R13 of the microcomputer 1. This alarm frequency oscillator 10 performs an oscillating operation when the output of the output terminal _R13 is logic "1".
The oscillation output is supplied to a sound alarm device 12 via a sound changeover switch 11. The changeover switch 11 is a three-contact switch, and when the common contact 11t is connected to the fixed contact 11a, the oscillation output is input to the sound alarm device 12 via the resistor 29, and the common contact 11t is connected to the fixed contact 11b. When this happens, the oscillation output is directly input to the notification device 12, and when the common contact 11t is connected to the fixed contact 11c, the oscillation output is prohibited from being input to the notification device 12. That is, the fixed contact 11a is a low volume output contact, the fixed contact 11b is a high volume output contact, and the fixed contact 11c is a sound stop contact. Further, reference numeral 13 denotes fixed contacts 13a, 13b, 13c and a common contact 13 selectively connected to each fixed contact.
The common contact 13t of this changeover switch 13 is a 3-contact type first power changeover switch consisting of
is connected to the +V terminal via the first relay coil 14, the fixed contact 13a is grounded via the first NPN transistor 15, and the fixed contact 13b is connected to the +V terminal via the first relay coil 14.
is directly grounded. Note that the fixed contact 13c is a non-connecting contact. A normally open contact 14a energized by the first relay coil 14 is inserted into a first power outlet circuit (not shown). A protection diode 16 and a series circuit of a resistor 17 and a light emitting diode 18 are connected in parallel to the first relay coil 14 . and the first
The base of the transistor 15 is connected to the output terminal _R14 of the microcomputer 1 via a resistor 19. Note that the first transistor 15
A resistor 20 is connected between the base and emitter of. Reference numeral 21 denotes fixed contacts 21a, 21b, 21c and a common contact 2 selectively connected to each fixed contact.
This is a 3-contact type second power changeover switch consisting of 1t, and the common contact 21 of this changeover switch 21
t is connected to the +V terminal via the second relay coil 22, the fixed contact 21a is grounded via the second NPN transistor 23, and the fixed contact 21a is connected to the +V terminal via the second relay coil 22.
b is directly grounded. Note that the fixed contact 21c is a non-connecting contact. A normally open contact 22a energized by the front second relay coil 22 is inserted into a second power outlet circuit (not shown). A protection diode 24 and a series circuit of a resistor 25 and a light emitting diode 26 are connected in parallel to the second relay coil 22 . and the second
The base of the transistor 23 is connected to the output terminal _R15 of the microcomputer 1 via a resistor 27. Note that the second transistor 23
A resistor 28 is connected between the base and emitter of. In both circuits, the power selector switch 1
Common contacts 13t and 21t of 3 and 21 are fixed contacts 1
3a, 21a, the relay coils 14, 22 output terminals R ₁₄ , R ₁₅ at logic “1”.
When the transistors 15, 23 are energized by the output, they are energized, and when the common contacts 13t, 21t are connected to the fixed contacts 13b, 21b, the relay coils 14, 22 are always energized, and the common contact 13t is energized. , 21t are connected to the fixed contacts 13c, 21c, the relay coils 14, 22
will continue to remain inactive. FIG. 3 is a block diagram showing the basic circuit configuration of the microcomputer 1, in which 31 is a central processing unit (CPU), 32 is a random access memory (RAM), 33 is a read-only memory (ROM), and 36 is a block diagram showing the basic circuit configuration of the microcomputer 1. is an input port, 37 and 38 are output ports, 39 is a data bus, and 40 is an address bus.
Buses 41, 42, and 43 are control signal lines. The CPU 31 includes a built-in arithmetic circuit, a program counter, a control circuit, an instruction decoder, a command register, and a memory for storing other processing signals, and connects each input port 3 to the CPU 31.
Based on the signals and information input from 4, 35, and 36, the RAM 32, ROM 33, and output port 3
7, 38 as data bus 39, address bus 4
0, control is performed via each control signal line 41, 42, 43. The RAM 32 has a 128 word x 4 bit configuration and has various storage sections formed therein. The ROM 33 has a capacity of 2K bytes.
A program for the CPU 31 to control each part according to input is stored. The input port 36 is adapted to receive signals from input terminals _K1 to _K8 . The output port 37 is an output terminal O ₀ ~
Outputs the signal to O ₇ , and output port 38 is the output terminal
Signals are output to R ₀ to R ₁₅ . The RAM 32 is addressed by a 3-bit X register and a 44-bit Y register,
Each address consists of a memory with 1 word and 4 bits. Below, each word is indicated by M[X, Y], and the bit within the word is indicated by M[X, Y]<b>.
Regarding the memory configuration, as shown in FIG. 4, M[0,0] to M[0,8] are a setting storage section or a setting storage section for setting the information input from the information/signal input section 6, or as described later. The display storage section is used to display the contents of the clock counting section and each information storage section. M[0,9] is a blinking mode storage unit that stores information on whether or not the display is blinking, and which part of the display 8 should be blinked when the display is blinking.
M[0,10] is a mode storage section that stores the mode selection state of the mode selection section 5. M
[0,11]<3><2> is the counting control section, and M
[0,11]<2> constitutes a memory that stores whether or not to count up a second counting section, which will be described later.
M[0,11]<3> constitutes a memory that stores the state of the input terminal _K8 . M[0,12] is a decimal counter for sequentially controlling the dynamic display of the fluorescent display 8, the judgment of each switch state of the mode selection section 5, the information/signal input section 6, and the frequency changeover switch 7. It is a routine control section consisting of a format. M[0,13] is a display mode storage unit that stores which of nine display modes to be described later. M[0, 14] is an input information storage unit that stores the states of input terminals K ₁ , K ₂ , and K ₄ . M[0,15] is a first counting section in the form of a hexadecimal counter that counts the commercial power frequency pulses input to the input terminal _K8 .
M[1,0]<3><2> constitutes a sound alarm state storage section, M[1,0]<2> constitutes a memory that stores the sound alarm operation state, and M[1,0]<3 > constitutes a memory that stores the snooze operation state. M
[1, 14] is a snooze counter that counts the time of the snooze operation. M[1,15], M[1,
1] to M[1, 7] are clock counting units that count the time. M[1,8] to M[1,13] are second counters that function as a stopwatch. M [2,0] ~ M [2,6], M
[3,0]~M[3,6], M[4,0]~M
[4,6], M[5,0] ~ M[5,6], M
[6,0]~M[6,6], M[7,0]~M
[7,6], M [2,7] ~ M [2,13], M
[3,7] ~M [3,13], M[4,7] ~M
[4,13], M [5,7] ~ M [5,13], M
[6,7] ~M [6,13], M[7,7] ~M
[7, 13] are the first to twelfth information storage units, respectively. M[2,14]<3><2> is the switch operation state storage section, and M[2,14]<3> is the first
When this bit is logic "1", output terminal _R14 is set to logic "1", and when this bit is logic "0", output terminal _R14 is set to logic "0". M[2,14]<2> constitutes the second switch operation state memory, and when this bit is logic "1", output terminal _R15 is set to logic "1", and when it is logic "0", output terminal R15 is set to logic "1". ₁₅ is set as logic "0". M[2,14]<1><0
>, M [2, 15] is determined by comparing the clock counting unit and the 12 information storage units, and if there is an information storage unit whose time matches, then according to the controlled object operation information of that information storage unit, If it is snooze operation information, M[2,
14] Set logic “1” to <1>, and set logic “1” to M[2, 14] <0> if it is alarm operation information.
If the first power outlet circuit is on (ON1) operation information, set M[2,15]<3> to logic “1”, and if the first power outlet circuit is off (OFF1) operation information. If so, M [2, 15] <
2> is set to logic “1”, and if the second power outlet circuit ON (ON2) operation information is set, M[2,
15] Comparison result storage that sets logic “1” to <1> and sets logic “1” to M[2, 15] <0> if the second power outlet circuit is off (OFF2) operation information. Department. M[7, 14] is a comparison control unit that is a hexadecimal counter and is used to sequentially control the comparison when checking the coincidence of times between the clock counting unit and the 12 information storage units every minute. . This comparison control section allows the clock counting section and 12
When all time comparisons with the information storage section are completed, based on the contents of the comparison result storage section, the alarm state storage section M[1,0]<3><2> and the switch operation state storage section M[2,14]<3><2>
Logic signals are stored in . M [3,
14], M[3, 15] are key input control units for preventing on-chattering and off-chattering of key operations and taking measures against simultaneous operation of two or more keys using software. M [5, 14],
M[6,14] is the setting storage section M[0,0]~M
This is an information setting control unit used for control when setting and storing information [0, 8] in one of the 12 information storage units. M[5,15] and M[6,15] are information used for control when setting and storing information in the display storage unit in order to display one of the 12 information storage units on the display 8. This is a display control section. Writing and reading control of logic signals to and from each of these storage sections is performed by the CPU 31 based on a program set in the ROM 33. When the above-mentioned M[0,0] to M[0,8] function as the display storage part of the clock counting part M[1,15], M[1,1] to M[1,7], as shown in FIG. As shown, M[0,0] and M[0,1] constitute the day of the week display memory, M[0,0]<3> is the Sunday display memory, and M[0,0]<2> is the Saturday display memory. memory, M
[0,0]<1> is Friday display memory, M[0,0]
<0> is Wednesday display memory, M[0,1]<3> is weekly display memory, M[0,1]<2> is Thursday display memory, M[0,1]<1> is Tuesday display memory,
M[0,1]<0> becomes the Monday display memory. This day of the week display memory contains M [1, 7] of the clock counter.
According to the day of the week information, logic "1" is set in the corresponding display memory. Also M [0,
2] to M[0,8] constitute a time display memory,
M[0,2] is 1 second display memory, M[0,3]
is 10 seconds display memory, M[0,4] is 1 minute display memory, M[0,5] is 10 minute display memory, M
[0,6] is 1 o'clock display memory, M[0,7]<1
><0> is 10 o'clock display memory, M[0,7]<3
> is the morning display memory, M[0,7]<2> is the afternoon display memory, and M[0,8]<3> is the colon display memory. And M[0,2] ~ M[0,
6] is the clock counter's 1 second range, 10 second range, 1 minute range,
Information for the 10 minute range and 1 o'clock range is stored. M[0,
7] <1><0> is set to logic "1" when there is information about 10 o'clock in the clock counter, and set to logic "0" when there is no information about 10 o'clock.
M[0,7]<3> is set to logic "1" when there is morning information in the clock counter, and M[0,7]<3>
2> is set to logic "1" when there is afternoon information in the clock counter. M[0,8]<3> is set to logic "1". When the above-mentioned M[0,0] to M[0,8] function as the display storage section of each information storage section, as shown in FIG. A day of the week display memory similar to that shown in FIG. 5 is constructed. For M[0,2], M[0,2]<1>
constitutes a snooze display memory, and M[0,2]<0> constitutes an alarm display memory. Regarding M[0,3], M[0,3]<3> is ON1 display memory, M
[0,3]<2> is OFF1 display memory, M[0,
3] <1> is ON2 display memory, M[0,3] <0>
constitutes the OFF2 display memory. M[0,4],
M[0,5], M[0,6], M[0,7], M
Regarding [0, 8], a time display memory similar to that shown in FIG. 5 is constructed. The clock counting section M[1,15], M[1,1]~
M[1,7] is M[1,15] as shown in Figure 7.
<2><1><0> is a 1/50 or 1/60 second counter, M[1,1] is a 1/10 second counter, M[1,
2] is a 1 second counter, M[1,3]<2><1
><0> is a 10-second counter, M[1,4] is a 1-minute counter, M[1,5]<2><1><0>
A 10-minute counter and M[1,6] are configured as an hour counter. Also, M[1,5]<3> is in the morning.
The afternoon memory, M[1,7]<2><1><0>, is configured as a day of the week memory. Said M [1, 15]
<2><1><0> functions as a quinary counter when the power frequency is 50Hz, and functions as a quinary counter when the power frequency is 60Hz.
Functions as a forward counter. Said M[1,1],
M[1,2], M[1,4] function as decimal counters, M[1,3]<2><1><0>, M
[1,5]<2><1><0> functions as a hexadecimal counter, and M[1,6] functions as a hexadecimal counter. M[1,5]<3> is set to logic "1" in the morning and set to logic "0" in the afternoon. M[1,7]<2><1><0> is binary data of logic "1" and "0"; it is "1" on Monday, "2" on Tuesday, and "3" on Wednesday. , "4" is stored on Thursday, "5" is stored on Friday, "6" is stored on Saturday, and "7" is stored on Sunday. As shown in FIG.
~7, 0 or 7] and M [2 to 7, 1 or 8] constitute the day of the week information memory. The arrangement of the day-of-week memories in this memory is similar to that in FIG. For M[2-7, 2 or 9], M[2
~7, 2 or 9] <1> is snooze information memory,
M[2-7, 2 or 9]<0> constitutes an alarm information memory. For M[2-7, 3 or 10], M[2-7, 3 or 10]<3> is ON1 information memory, M[2-7, 3 or 10]<2> is
OFF1 information memory, M [2-7, 3 or 10] <1
> is ON2 information memory, M [2 to 7, 3 or 10] <
0> constitutes the OFF2 information memory. M [2
~7, 4 or 11] constitutes a 1-minute information memory,
M [2-7, 5 or 12] <2><1><0> is 10
Configure the branch information memory, M [2 to 7, 6 or
13] constitutes the timetable information memory, and M[2~
7, 5 or 12]<3> constitutes the morning/afternoon information memory. Said second counting section M[1,8] to M[1,13]
As shown in Figure 9, M[1,8] is a 1 second counter, M[1,9] is a 10 second counter, and M[1,
10] is a 1-minute counter, M[1, 11] is a 10-minute counter, M[1, 12] is a 1-hour counter, M
[1, 13] is configured as a 10 o'clock counter.
Said M[1,8], M[1,10], M[1,12],
M[1,13] functions as a decimal counter, and M
[1,9] and M[1,11] function as hexadecimal counters. That is, the second counting sections M[1,8] to M[1,13] function as counters from 1 second to 99 hours, 59 minutes, and 59 seconds. Next, the control of the fluorescent display 8 by the microcomputer 1 will be described. Each segment control terminal a, b, c, d, e, f, g, Dp of the display 8 will be described.
The display pattern information is displayed on microcomputer 1.
Each output terminal O ₀ , O ₁ , O ₂ , O ₃ , O ₄ , O ₅ , O ₆ ,
The display pattern information is generated by decoding a total of 5 bits of information from a 4-bit accumulator and 1 _- bit status latch inside the microcomputer 1 using a programmable logic array. . This bit information is as shown in Table 1 when the status latch is at logic "0", and as shown in Table 2 when the status latch is at logic "1". In other words, when the status latch is at logic "0" and the contents of the accumulator are between 0 (0000) and 9 (1001), display pattern information that displays the corresponding numerical value and decimal point is output, and when it is 10 (1010), it is output as " Outputs display pattern information to display "A", and outputs display pattern information to display "U" when it is 11 (1011),
When it is 12 (1100), it outputs display pattern information to display "C", and when it is 14 (1110), it outputs display pattern information to display "L",
15 (1111), display pattern information for displaying "F" is output. Note that when the content of the accumulator is 13 (1101), it is not displayed. Also, when the status latch is logic “1”, the accumulator <0
>Displays the c segment when the bit is logic "1", displays the b segment when the <1> bit is logic "1", and displays the e segment when the <2> bit is logic "1". <0> of the accumulator so that the f segment is displayed when the <3> bit is logic “1”.

【table】

【table】

[Table] Each bit of <1><2><3> and c of display 8,
Display pattern information configured such that the segments b, e, and f correspond one to one is output. Next, display memory section M[0,0] to M of RAM32
The fifth clock counter information is set to [0,8].
Regarding the control of the fluorescent display 8 in the case shown in the figure, the information of M[0,2] is _G1 digit, M
[0,3] information is _G2 digit, M[0,4]
The information is G ₃ digits, and the information M[0,5] is
Control is performed to sequentially display the _G4 digit, the M[0,6] information on the _G6 digit, and the M[0,7] information on the _G7 digit. At this time, if logical "1" is set in the Monday display memory M[0,1]<0> among the day of the week display memories M[0,0] to M[0,1], the _G7 digit is displayed. At this time, a logic "1" is output to the output terminal _R12 . Also, when displaying the _G7 digit and _G5 digit, the status latch is set to logic "1" and the display is controlled in the format shown in Table 2.
When displaying each of the digits G ₁ , G ₂ , G ₃ , G ₄ , and G ₅ , the status latch is set to logic "0" and the display is controlled in the format shown in Table 1. The morning information is displayed by the f segment of the _G7 digit, and the afternoon information is displayed by the e segment of the _G7 digit. Therefore, if the time information of, for example, 12:25:34 a.m. on Monday is set in the display storage section, the display on the fluorescent display 8 will be as follows.

[Table] 12: 25. ₃₄
And if the time information of 3:56:17 on Wednesday is set, the display on the fluorescent display 8 will be:

[Table] 3: 56. ₁₇
becomes. Next, display memory section M[0,0] to M of RAM32
6th with information in the information storage section set to [0, 8]
Regarding the control of the fluorescent display 8 in the case shown in the figure, M[0,0], M[0,1], M[0,
4], M[0,5], M[0,6], M[0,7]
The information is exactly the same as when displaying time information. The snooze display information of M[0,2]<1> is displayed by the b segment of the _G1 digit, and the alarm display information of M[0,2]<0> is displayed by the c of the _G1 digit. This is now done in segments. Also M [0,
3] Display of ON1 display information of <3> is performed by f segment of _G2 digit, and M[0,3]
The display of the OFF1 display information in <2> is performed by the e segment of the _G2 digit, and M[0,3]<
1> ON2 display information display is _G2 digit b
segment, and M[0,3]
The OFF2 display information of <0> is displayed by the c segment of the _G2 digit. Also, since the information in this information storage unit is timer information, it is possible to set the timer operation to be repeated every week.
1 or 8] by setting logic "1" to <3>. Therefore, at this time, logic "1" is set in M[0,1]<3> of the display storage section. In such a case, a logic " ₁ " is output to the output terminal R1 when displaying the _G2 digit. Therefore, if timer information is set in the display storage section, for example, to turn on the first power outlet circuit at 8 p.m. on Friday,
The display on the fluorescent display 8 is as follows:

【table】 - -
If timer information is set to turn on the second power outlet circuit and perform the snooze operation every Monday, Tuesday, Wednesday, Thursday, and Friday at 7 a.m., the display on the fluorescent display 8 will be as follows. ,

【table】 - -
becomes. In the apparatus of the present invention constructed in this manner, various controls are performed by the four mode changeover switches of the mode selection section 5 and the 22 keys of the information/signal input section 6. (1) Clock setting mode This mode is set to “TIME” in mode selection section 5.
This mode is set by operating the "ADJ." key, and is a mode in which time information is set in the clock counter. In this mode, the "WEEK" key is used to invert the contents of M[0,8]<3>, lighting up the colon segment of the _G5 digit when it becomes a logic "1", and turning it on when it becomes a logic "0". Turn off the light when it gets cold. “1/
MON”, “2/TUE”, “3/WED”, “4/
THU”, “5/FRI”, “6/SAT”, “7/
Each key of "SUN" has the function of specifying the day of the week from Monday to Sunday as a day of the week specification key when M[0,8]<3> is logic "1".
When [0,8]<3> is logical "0", it has the function of specifying a numerical value from 1 to 7 as a numeric key. When each of the above keys is used as a day of the week designation key, M[0,0], M in the setting storage section
Set the day of the week memory corresponding to [0, 1] to logic “1”
and the others are set to logic "0", and the corresponding day segment of the fluorescent display 8 is lit. At the same time, M[0,8]<3> is set to logic "0" and the colon segment is turned off, indicating that the next time each key is operated, it will be used as a numeric key. This control is based on the fact that only one type of day of the week can be specified when setting time information. When each of the keys is used as a numeric key, numeric data is set in M[0,2] of the setting storage section. As a result, the data that was previously set to M[0,2] becomes M
Transferred to [0,3], and then M[0,3] → M
[0,4], M[0,4] → M[0,5], M
The data will be transferred from [0,5] to M[0,6]. When the data transferred from M[0,5] in M[0,6] is 0, 1, or 2, and the data set before it is 1, M[0,7]<1. ><0> is set to logic “1”, otherwise M[0,7]<1><0>
is set to logic “0”. As a result, M
The data set to [0, 2] is 1 on the display 8.
The _G1 digit 8-1 is used to display seconds, and the data that was displayed before is transferred and displayed one digit at a time. At this time, when the _G7 and _G6 digits 8-7 and 8-6 display 13 o'clock or more, the _G7 digit 8-7, that is, the 10 o'clock digit display section, is turned off. "0/EW", "8/M~F", "9/M~
Each key of "S" functions as a numeric key regardless of whether the logical value of M[0,8]<3> is "0" or "1". When each key is operated, if M[0,8]<3> is logic "1", it is inverted to logic "0". Of course, the data for each key is set to M[0,2]. “AM/
11” key is the key for specifying the morning, M[0,7]<3
> is logic "1" and M[0,7]<2> is logic "0" to light up the f segment of _G7 digit 8-7. The “PM/12” key is a key for specifying the afternoon, and sets M[0,7]<3> to logic “0”.
[0,7]<2> is set to logic "1" to light up the e segment of _G7 digit 8-7. This "AM/11" key and "PM/12" key are both M
If [0,8]<3> is logic "1", it is inverted to logic "0" and the colon segment is turned off. The "CLEAR" key is used to erase the setting memory section when a setting is made incorrectly. By operating this key, the setting memory section M[0,0], M
[0,1], M[0,2], M[0,3], M
Set “0” to [0, 8] respectively, and set M
“12” in [0,4], “13” in [0,5], M
Set "13" to [0,6] and "10" to M[0,7]. and M[0,2] to M[0,3],
For M[0,8], set the status latch to logic "1" and set it to M[0,8] in the format shown in Table 2.
4] to M[0,7], the status latch is set to logic "0" and displayed on the display 8 in the format shown in Table 1. Therefore, the display at this time will be AC. This display control is performed in the same way when the mode is switched from another mode to the clock setting mode in the mode selection section 5, and it is displayed that the address has become the clock. In this clock setting mode, the display format must be set as status latch "0" or "1".As mentioned above, there are two display modes: clock display mode and address display mode.
This is stored in the display mode storage section of M[0,13]. When the mode in the mode storage section M[0,10] differs from the mode in the mode selection section 5, that is, when the mode in the mode selection section 5 is switched from another mode to the clock setting mode, press the "CLEAR" button. is operated, the display mode is set to address display mode, and in the address display mode, "0/EW" ~ "9/M ~"
By setting the display mode to clock display mode when each of the "S" keys, "AM/11", and "PM/12" keys are operated, it is possible to set both display formats in both display modes without any problems. I have to. The "STOP" key sets M[1,0]<2> to logic "0" when M[1,0]<3> is logic "1" and sets the count value of M[1,14] to 0. , M[1,0]<3> are logic "0", M[1,0]<2> is set to logic "0", which will be described in detail later. In this clock setting mode, "ON1", "OFF1", "ON2",
The "OFF2", "ALARM", and "SNOOZE" keys have no meaning. The "INPUT" key is a transfer key for transferring time information set in the setting storage section to the clock counter. When this key is operated, if the contents of the setting storage section are correct as time information, this time information is transferred to the clock counter section, and M[1, 14], M[1, 15], M
[1,0], M[1,1], M[0,15] are cleared to zero, M[0,11]<3> is set to logic “0”, and M[0,13] ] is stored in the display mode storage unit, and the setting storage unit is set to that display mode. Then, "AC" is displayed on the display 8, indicating that the clock address has been correctly set.
The meaning of M[1,14] and M[1,0] being zero will be explained later, but M[1,15], M[1,
1], M[0,15] is zero, and M[0,11]<3
> is set to logic "0" to mean that the counter for less than 1 second is reset to zero. Further, when the time information set in the setting storage section is not correct, the following control is performed. First, if neither morning nor afternoon is specified, this is displayed. For example, if you operate the "INPUT" key in address display mode, the display mode storage section will be set to clock display mode, and the display will change to M[0,0], M
[0,1], M[0,7] are set to zero, M[0,
8] Set logic “0” to <3>, and set M[0,
2], M[0,3], M[0,4], M[0,
5], after setting M[0,6] to 13, it will display that there is no morning or afternoon specification. This display lights up the e and f segments of the _G7 digit for 0.5 seconds, and
This is done by repeatedly turning off the light for seconds.
That is, in the blinking mode storage section of M[0,9],
The value according to the blinking type, in this case, the value according to the morning and afternoon blinking modes, is memorized and carried out, and the blinking period is determined by the 1/10 second counter of M [1, 1], and this count value is set to 0. The setting is made by turning off the light when the number is 4 to 4, and turning it on when the number is 5 to 9. Segments other than this segment are displayed according to the contents of the setting storage section. Also, when performing this blinking, M[0,
8] Set <3> to logic “0” and do not display the colon segment. Then, when the "AM/12" key is pressed, this blinking operation is stopped, and the control operation by operating these two keys described above is performed.
Second, if there is no day of the week specification, that is, M[0,
0], M[0,1] are all logic “0”, day of the week segments 8-7b, 8-6b, 8-
5b, 8-4b, 8-3b, 8-2c, 8-1
Display c all blinking at 0.5 second intervals. In this case, the blinking mode storage section of M[0,9] stores the value according to the day of the week blinking mode, and also stores the value according to the day of the week blinking mode.
[0,8] Set logic “1” to <3>, then “1/MON”, “2/TUE”, “3/WED”,
“4/THU”, “5/FRI”, “6/SAT”, “7/
When the "SUN" keys are operated, these keys function as day-of-the-week designation keys. Further, the blinking period is set by M[1,1] as in the case where morning or afternoon is not specified as described above. Segments other than this segment are displayed according to the contents of the setting storage section. Thirdly, if the time value is not normal, that is, in a 12-hour display system, when setting time information, a value other than 1:00:00 to 12:59:59 is not possible, so for example, 12 minutes 15 seconds or 12
The value of 72 minutes and 98 seconds is incorrect information.
In such a case, the numerical value is displayed blinking as it is. That is, when M[1,1] is between 0 and 4, the numerical value remains lit, and when it is between 5 and 9, nothing is displayed in the time section. Also, at this time, M[0,8]<3> is set to logic "0" and then "1/MON" to "7/
When the keys up to "SUN" are operated, these keys function as numeric keys. Segments other than this segment are displayed according to the contents of the setting storage section. (2) Information setting mode This mode is set by operating the "SET" key of the mode selection section 5, and is a mode in which timer information is set in one of the 12 information storage sections. In this mode, when the mode is switched to the information setting mode in the mode selection section 5 or when the "CLEAR" key is operated, the address of the storage section for which timer information is not set among the 12 information storage sections is selected. , with priority given to the one with the younger address, and set the value according to that address in the information setting control section of M[5,14], M[6,14], and 0,
8] has M[0,0], M[0,
1], M[0,2], M[0,3] are set to zero, M[0,6] is set to 13, M[0,7] is set to 10, M[0,8] Set <3> to logic "0". Also, when the address is 0 to 9, the address number is set to M[0,4], and the address number is set to M[0,4].
5), and the address is 10.
-12, address numbers are set in M[0,4] and M[0,5]. For example, when the unset address is number 1, "A1" is displayed on the display 8, and when it is address 12, "A12" is displayed. At this time, the address display mode is stored in the display mode storage section M[0,13]. There are two display modes in this information setting mode: the address display mode mentioned above and the information display mode (see Figure 6). Changing the mode from the address display mode to the information display mode is the same as in the clock setting mode mentioned above. The information display mode is stored in M[0,13] instead of the address display mode. At this time, M[0,0]=
0, M[0,1]=0, M[0,2]=0,M
[0,3]=0, M[0,4]=13, M[0,
5]=13, M[0,6]=13, M[0,7]=0
and sets M[0,8]<3> to logic "0" to prepare for setting new key setting information. Also, when searching for unset information storage units in this information setting mode, if all 12 information storage units have already been set, M[0,4]=14, M[0,5]=14, M
Set [0,6]=11, M[0,7]=15, and set M[3,15]<3> to logic "1". As a result, the display 8 displays FU LL to indicate that all information storage units are set. Also, among the key input control units, M[3,
15] <3> is set to logic "1", but this bit is a key input prohibition bit. When this bit is logic "1", all key input operations are prohibited, even if a key operation is performed by mistake. The display continues to show "FULL". In this information setting mode, the "CLEAR" key is used to clear the setting storage section, similar to the clock setting mode described above, and the contents and display of the setting storage section after operating this key are as described above. The "WEEK" key has the same effect as the clock setting mode described above. "0/EW", "1/
MON”, “2/TUE”, “3/WED”, “4/
THU”, “5/FRI”, “6/SAT”, “7/
The ten keys "SUN", "8/M~F" and "9/M~S" are set when logic "0" is set to M[0,8]<3> and the colon segment is turned off. It has a function as a key, and the numerical value input by this is set to M[0,4].
Then, the values previously set in M[0,4] to M[0,6] are sequentially transferred to the upper counter in the same way as in the clock setting mode, and M[0,6]
If the data transferred from M[0,5] is 0, 1, or 2, and the data set before it is 1, then M[0,7]<
1><0> is set to logic "1" and the others are set to logic "0". As a result, the newly set value for M[0,4] is displayed on the 1-minute display section of the _G3 digit, and the previously displayed values are shifted one digit higher. and
When the _G7 and _G6 digits display 13 o'clock or more, the _G7 digit is turned off. Also, these 10 keys are M[0,
8] When <3> is set to logic "1" and the colon segment is lit, it functions as a day of the week designation key. In other words, “1/
MON” key to “7/SUN” key corresponds to Monday to Sunday, and by operating this key,
The corresponding bits of [0,0] and M[0,1] are set to logic "1" and the corresponding day of the week display segment of the display 8 is lit. “8/M
~F'' key corresponds to the five days of the week from Monday to Friday, and by operating this key, M[0,0]
<1>, <0> of and <2>, < of M[0,1]
1>, <0> are set to logic "1", and the display 8's Monday, Tuesday, Wednesday, Thursday,
Light up each Friday segment. “9/M~
The "S" key corresponds to all days of the week from Monday to Sunday, and by operating this key, M[0,0]
<3>, <2>, <1>, <0> and M[0,
1], the seven bits <2>, <1>, and <0> are set to logic "1" and all day of the week display segments on the display 8 are lit. “0/
The "EW" key is a key for specifying weekly operations, and the key is M[0,
1] Set logic “1” to <3> and display the weekly operation mark segment 8-2b on the display 8.
lights up. The weekly operation here means that the timer operation on the set day of the week is performed every week. The timer information set without operating the "0/EW" key is cleared and reserved as an unset address when the timer operation based on the information is started. In the clock setting mode described above, M[0,8]<3> is set to logic "1" to provide a day of the week designation function when operating the keys "1/MON" to "7/SUN".
In this state, when one key is operated to specify the day of the week, M[0,8]<3> is set to logic "0", and the next time each key is operated, it is used as a numeric key. However, in this information setting mode, multiple day of the week information can be set in one information storage unit, so two or more of the above 10 keys may be operated in succession. There is also. Therefore, in this information setting mode, M[0,8]<3> is maintained at the logic "1" state even if the above ten keys are operated. However, when all bits of M[0,0] and M[0,1] become logic "1" by this key operation, no more days of the week can be specified, so M
[0,8]<3> is set to logic "0" so that these 10 keys will function as numeric keys the next time they are operated. "AM/11" key,
The "PM/12" key and the "STOP" key have the same functions as in the clock setting mode described above. "ON1", "OFF1", "ON2",
The six keys "OFF2", "ALARM", and "SNOOZE" are operation information setting keys for the controlled object, and when these keys are operated, M[0,8]<3> is set to logic "0". Set. And the “ON1” key sets M[0,3]<3> to logic “1”, M[0,
3] Set <2> to logic “0”, turn on the f segment of _G2 digit, turn off the e segment,
The "OFF1" key sets M[0,3]<3> to logic "0" and M[0,3]<2> to logic "1".
G ₂ digit e segment turns on, f segment turns off, "ON2" key is M [0, 3] <
1> is logic "1", M[0,3]<0> is logic "0", the b segment of the _G2 digit is turned on, the c segment is turned off, and the "OFF2" key is set to M[0,3]. <1> is logic “0”, M[0,
3] Set <0> to logic "1" to turn on the c segment of the _G2 digit and turn off the b segment. Also, the “ALARM” key is M[0,2]<1>
is logic “0”, M[0,2]<0> is logic “1”
Lights up the c segment of the G ₁ digit as
Turn off the b segment and press the “SNOOZE” key to M
[0,2]<1> is logic “1”, M[0,2]<0
> is set to logic "0" to turn on the b segment of the _G1 digit and turn off the c segment.
The "INPUT" key has a more complicated function than the clock setting mode described above. First, when normal timer information is set in the setting storage section, the timer information is sent to the information setting control section M[5, 14], M
The address stored in [6, 14] is transferred to the information storage section, and the mode selection section 5 searches for the next address to be set in the same manner as when the mode is switched to the information setting mode. The address is stored in the information setting control section, this address is set in the setting storage section, and this address is displayed on the display 8 in address display mode. This allows the user to know that the information has been reliably set in the information storage section and also to know the next setting address. Next, if there is no specification of morning, afternoon, or day of the week, it is determined that time is specified. At this time, the specified and displayed time is added to the time information of the clock counting section, and the time is set in the setting storage section and displayed on the display 8. In this process, the 1-minute and 10-minute digits are processed by 4-bit parallel addition, but special arithmetic processing is performed for the hour range. This is because the calculation result may affect the bits designated for morning and afternoon and the designated bits for the day of the week. Here, the time that can be added to the time information of the clock counter is from 0 minutes to 12:99 (13:39). In this way, when adding 13:39, if there is a carry from the 10 minute range, the value added to the hour digit will be 14. In other words, the maximum value added to the hour digit is 14. Therefore, when 4-bit parallel addition is performed for the time series, the result obtained is a value between 1 and 26. When the result of this addition is in the range of 1 to 11, there is no problem since there is no switching between morning, afternoon, and day of the week, but when the result is 12 or more, various judgments are required. for example
When the clock reaches 12, it is necessary to judge whether or not it is necessary to change the morning and afternoon bits depending on whether the time in the clock counter is over 12 o'clock or less than 12 o'clock, and then change from pm to am. Sometimes it is necessary to change the day of the week. Also, when it turns 13, the time changes to 1 o'clock, and
In the afternoon, the change in the day of the week must be determined based on whether the time on the clock counter is more than 12 o'clock or less than 12 o'clock. This was done in the same way in 14 and 15.14
It is necessary to change the time to 2 o'clock when it is , and to 3 o'clock when it is 15. Furthermore, if the number is 16 or more, 4-bit parallel addition can only process from 0 to 15 at most, so it is also necessary to judge the carry of parallel addition. Similar judgments are made up to 23. At 24, when the time on the clock counter is 12 o'clock, it is necessary to change the morning or afternoon and determine whether to change the day of the week, and at 10 o'clock or 11 o'clock, it is necessary to change the day of the week without changing the morning or afternoon. On the 25th and 26th, it is also necessary to change the time to 1:00 and 2:00. The processing at the time of parallel addition of the above timetables is illustrated in a graph as shown in FIG. In other words, in this graph, the (a) line shows the line that changes afternoon to am and also changes the day of the week, and the (b) line changes 13:00 to 1:00 and has to judge whether to change am, pm, or day of the week. The (c) line indicates the line where morning should be changed to afternoon and the day of the week must be determined. The (d) line indicates the line where 13:00 is set to 1 o'clock and the line is where the change of morning, afternoon, and day of the week must be determined. It shows you the line you have to follow.
In this way, when the time table is performed by 4-bit parallel addition, there is a problem that the number of instructions to be written to the ROM 33 described above becomes extremely large because the content of judgment differs depending on the case. This problem is solved by taking the following method. In other words, when adding the set time value to the hour digit value of the clock counter, the time value is subtracted by 1 while adding 1 to the hour digit value of the clock counter, and as a result, the hour digit value becomes 12. The time is changed from AM to PM, and when this change is from PM to AM, the day of the week is also changed.When the time reaches 13, it is changed to 1.The program process only changes the hour digit value until the time value becomes zero. Keep adding. Next, we will explain the control when abnormal timer information is set in the setting storage section.
First, there may be a case where the day of the week is specified but AM and PM are not specified. In this case, the e and f segments of the G7 digit on display 8 will be displayed in AM and PM blinking modes, similar to the _clock setting mode described above. is displayed blinking. Second, there may be a case where AM or PM is specified but the day of the week is not specified, but in this case as well, all day segments of the display 8 are blinked in the day of the week blinking mode as in the clock setting mode described above, and M [0,8] Set logic "1" to <3>. Thirdly, the set time is 1 o'clock.
There may be a case where the value is not set from 00 to 12:59, but in this case as well, the display 8 should be blinked in the time blinking mode as in the clock setting mode described above, and M[0,8]<3> is set to logic “0”. Fourth, when there is no motion information specification for the controlled object, that is, M[0,2]<
1>, <0>, M[0,3] <3>, <2>, <1
>, <0> may not be set to logic "1"; in this case, the b and c segments of the _G1 digit and the _G2
The b, c, e, f segments of the digit are
When [1,1] is 0 to 4, the light is off, and when it is 5 to 9, it is lit, blinking at 0.5 second intervals.
At this time, the operating blinking mode is stored in the blinking mode storage section of M[0,9]. (3) Clock display mode This mode is set to “CLOCK” in mode selection section 5.
This mode is set by key operation, and is a mode in which the display 8 displays the contents of the clock counter or the second counter. In this mode, when the mode selection section 5 switches the mode to clock display mode, the contents of the clock counter are transferred to the display storage section (the same storage section as the setting storage section is used), and M[0,8] <3> is set to logic "1", and the clock display mode is stored in the display mode storage section M [0, 13] and displayed on the display 8. Then, when the "WEEK" key is operated when M[0,8]<3> is logic "1", M[0,8]<3>
M[0,
13] as the second counter display mode.
to be displayed. In this case M[0,0]~M
The contents of the second counting section transferred to the display storage section [0, 8] are as shown in FIG. That is, all of the day of the week display memories of M[0,0], M[0,1] and the colon display memory of M[0,8]<3> are set to logic "0", and M[0,
2] to M[0,7] are display memories for 1 second, 10 seconds, 1 minute, 10 minutes, 1 o'clock, and 10 o'clock, respectively. When displaying the contents of this second counting section, set 13 to all digits above 10 minutes, especially when all digits above 10 minutes are zero. In this second counter display mode, G ₁ ,
Each digit of G ₂ , G ₃ , G ₄ , G ₆ , and G ₇ is displayed in the first table format with the status latch set to “0”.
The _G5 digit is displayed in a second table format with the status latch set to "1". Therefore, when all digits of 10 minutes or more become zero, display 8
will be a zero suppress display where nothing will be displayed in the digits above 10 minutes. Conversely, if the "WEEK" key is operated when M[0,8]<3> is logic "0", M[0,8]<3> is inverted to logic "1" and the clock counter is The contents are transferred to the display storage section and displayed on the display 8 with M[0,13] set to clock display mode. The colon segment is lit in the clock display mode but is turned off in the second counter display mode, so whether the display is for the clock counter or not depends on whether the colon segment is lit or not. You can easily tell if it is from the counting section.
Also, if the "INPUT" key is operated when M[0,8]<3> is logic "1", M[0,8]<3>
3> to logic “0” and the above “WEEK”
The contents of the second counter are displayed in the same way as when the keys are operated. In operation of this "INPUT" key, M[0,11]<2> is set to logic "1". The above M[0,11]<2> is the second
This is a control bit for the counting section of the circuit, which causes counting to be performed when the logic is "1", and stops counting when the logic is "0". Therefore, when the "INPUT" key is operated while the clock counter is displayed, the contents of the second counter will be displayed, and if the second counter is in a stopped state at that time, it will start counting, and the second counter will start counting. If the unit is in the counting state, it continues counting. Conversely, the above M[0,8]
When the "INPUT" key is operated when <3> is logic "0", M[0,11]<2> is inverted. That is, if the second counting section is counting, it stops counting, and if it is stopping, it restarts counting. “CLEAR” key is M[0,
8] If <3> is logic "0", clear the second counter to zero, set M[0,11]<2> to logic "0", and display "0. ₀₀ " on display 8. display. The operation of this "CLEAR" key is M[0,
8] When <3> is logic "1", it has no meaning. The "STOP" key has the same function as in clock setting mode. "ON1", "OFF1",
Each key of "ON2" and "OFF2" is M[2,14]<3
><2> The switch state storage section is controlled to set logic "0" and "1". When the "ON1" key is operated, M[2,14]<3> is set to logic "1" and output terminal _R14 is set to logic "1". At this time, if the first power supply changeover switch 13 connects the common contact 13t to the fixed contact 13a, it turns on the first transistor 15, energizes the first relay coil 14, and connects the normally open contact 13t to the fixed contact 13a.
A is closed to control energization of the first power outlet circuit. Further, the light emitting diode 18 is made to emit light to indicate this fact. When the "OFF1" key is operated, M[2,14]<3> is set to logic "0", output terminal _R14 is set to logic "0", and the operation opposite to that of the above "ON1" key is performed. energization of the power outlet circuit is controlled to stop, and the light emitting diode 18 is turned off. When the "ON2" key is operated, M[2,14]<2> is set to logic "1" and output terminal _R15 is set to logic "1". At this time, if the second power selector switch 21 connects the common contact 21t to the fixed contact 21a, it turns on the second transistor 23, energizes the second relay coil 22, and connects the normally open contact 21t to the fixed contact 21a.
a to control the energization of the second power outlet circuit. Further, the light emitting diode 26 is made to emit light to indicate this fact. When the "OFF2" key is operated, M[2,14]<2> is set to logic "0" and output terminal _R15 is set to logic "0", and the operation opposite to that of the above "ON2" key is performed. energization of the power outlet circuit is controlled to stop, and the light emitting diode 26 is turned off. In this mode, operating any keys other than those mentioned above has no meaning. (4) Information recall mode This mode is set by operating the "CALL" key in the mode selection section 5, and allows you to recall the contents of the 12 information storage sections to the display 8 for confirmation or deletion. This is the mode where you can In this mode, when the mode is switched to the information call mode by the mode selection unit 5, M[0,0]=
0, M[0,1]=0, M[0,2]=0,M
[0,3]=0, M[0,4]=14, M[0,
5]=14, M[0,6]=10, M[0,7]=12
At the same time, M[0,8]<3> is set to logic "0", and the information call mode is stored in the display mode storage section of M[0,13].
The display in this mode is M[0,2], M[0,3]M as in the adren display mode.
[0,8] is performed in the second table format with the status latch being logic “1”, and M[0,4], M[0,
5], M[0,6], and M[0,7] are set in the first table format with the status latch being logic "1". Therefore, the display on the display 8 becomes C A L L . This display lets the user know that the information call mode has been entered. In this mode, the "1/MON" to "9/M to S" keys correspond to the first to ninth information storage sections, respectively, and the "0/MON" to "9/M to S" keys correspond to the first to ninth information storage sections, respectively.
"EW" corresponds to the 10th information storage section, "AM/
The "11" key corresponds to the eleventh information storage section, and the "PM/12" key corresponds to the twelfth information storage section. When each of these keys is operated, a numerical value corresponding to the value set in the address display mode is displayed while the key is being operated, in the same way as when switching from the other mode to the information setting mode described above. Note that in the information setting mode described above, the addresses were stored in the information setting control units of M[5, 14] and M[6, 14], but in this information retrieval mode, the addresses were stored in the information setting control units of M[5, 14] and M[6, 14]. , 15] is stored in the information display control unit. For example, when the "1/MON" key is operated, "A1" is displayed on the display 8, indicating that the address is number 1. If you release the key in this state,
That is, when the address display mode is stored in M[0,13], M[3,14], M[3,
15] When the key input control unit determines that the key has been released, the contents of the information storage unit at the address according to the address of the information display control unit are transferred to the display storage unit in the form shown in FIG. be done. At this time, M[0,8]<3> is set to logic "1". Then, an information display mode similar to the information setting mode is stored in the display mode storage section M[0,13] and displayed on the display 8. For example, if timer information for turning on the first power outlet circuit at 3:15 p.m. on Mondays, Wednesdays, and Fridays is stored in the first information storage section at this time, the display will be as follows.

【table】 - -
becomes. If the "CLEAR" key is operated in this state, the first information storage section displayed here will be erased. That is, the information storage section at the address corresponding to the address of the information display control section is erased. This display after erasing displays the erased contents of the information storage section as ":0" in the information display mode to indicate that the contents have been erased. In this mode, by operating one of the 12 keys corresponding to each information storage section, the address of the corresponding information storage section will be displayed, and when the key is released, the information storage section at that address will be displayed. The contents are displayed. If the ``CLEAR'' key is operated in this state, the contents of the displayed information storage section will be erased, and this fact will be displayed. Also, when the "CLEAR" key is operated in the information recall display mode, the all information recall display mode is stored in the display mode storage section of M[0, 13], and the display mode of M[0, 7] is
=13. The status latch in this all information call display mode is used in the same way as in the information call display mode. Therefore, the display at this time is A L L, indicating that all 12 information storage units have been designated. If you operate the "CLEAR" key in this all information call display mode, the contents of all 12 information storage sections will be erased, the information call display mode will be stored in M[0, 13] again, and the display will become "CALL". . In this way, the information call display mode and all information call display mode are set to M[0,7].
It can be used in a simple way by simply changing the value of , and its meaning can be clearly displayed. “STOP” key is M[1,0]<3><2
＞ is set to logic "0", and M
This is the key that sets the snooze counter at [1, 14] to zero and also sets the output terminal R ₁₃ to logic "0". In this information call mode, other "ON1",
"OFF1", "ON2", "OFF2", "ALARM",
The keys "SNOOZE", "INPUT", and "WEEK" have no meaning. Further, in the apparatus according to the embodiment of the present invention configured as described above, the following operations are performed when the power is restored. That is, when the power is turned on, the initialization circuit 3 starts executing the program at a specific address in the ROM 33. First, all contents of RAM 32 are erased. Then M[3,15]<3>
Sets logic "1" to all key inputs. In addition, in order to issue a power outage alarm after 5 minutes, M[1,0]< in the alarm state storage section M[1,0]
3> is set to logic "1" in the snooze state storage unit. Further, the blinking mode memory for M[0,9] stores the power failure blinking mode, the display mode memory for M[0,13] stores the power failure display mode, and the routine enters the normal routine. In this case, M[3,15]<
3> is set to logic "1" because in the power failure display mode, it is necessary to invalidate all key inputs unless the mode selection section 5 is in the clock setting mode. For example, if you think about a situation where a power outage occurs while you are using the clock display mode as an alarm, and then the power outage is restored, if the alarm device 12 is activated to recover from the power outage, even if the "STOP" key is pressed. Even if the key is operated, the alarm operation is disabled by invalidating the key input, so that the alarm operation is not stopped when the set time has come, but rather the alarm operation is performed when the power is restored. It has the function of letting you know that there is a Furthermore, when a power outage occurs, all the contents of the information storage section are erased and the clock counting section is also erased, so in order to operate it as a timer again, it is first necessary to set the time information. For this reason, key input is disabled except in clock setting mode. Specifically, in the power outage display mode, the mode selection section 5
When enters clock setting mode, M [3, 15]
<3> is set to logic “0” to enable key input, and when a key input occurs here, M[0,
9] The non-blinking mode is stored in the flashing mode storage unit, and after that, the mode selection unit 5 operates in the same way as when it switches to the clock setting mode in normal use (when no power outage occurs), and then each key is input. Perform the actions according to the instructions. Further, when there is no key input in the clock setting mode and the mode selection section 5 is subsequently set to another mode, M[3,15]<3> is set to logic "1" again and the key input is prohibited. This power outage display mode is M[0,1]~M
[0,8] are all zero, and G ₁ ,
G ₂ , G ₅ digits in the format shown in Table 2 with the status latch set to logic "0", G ₃ , G ₄ , G ₆ , G ₇ digits set in the format shown in Table 1 with the status latch set to logic "1" 0.5 This is done by displaying for a second and then not displaying anything for the remaining 0.5 seconds. Therefore, the display on the display 8 will start blinking 00 00 at 0.5 second intervals. Also, at this time, since logic "1" is set in the snooze state storage section of M[1,0]<3>, the output terminal _R0 becomes logic "1" and the alarm display segment 8-1b is set.
lights up. Further, in the apparatus according to the embodiment of the present invention configured as described above, the following operations are performed based on the commercial power supply frequency pulse inputted from the input terminal _K8 . The clock counter performs a time counting operation based on this commercial power supply frequency pulse, and in this operation, the 10-second counter of M[1,3]<2><1><0> is counted from the 10-second counter of M[1,4]. When the 1-minute counter is incremented, the time in the clock counting section and the times in the 12 information storage sections are sequentially compared. For example, when the time of the clock counting unit matches the time of the first information storage unit of M[2,0] to M[2,6], the comparison result is calculated based on the controlled object operation information of the first information storage unit. Set storage units M[2,14]<1><0> and M[2,15]. For example, M[2,2]<1> is logic “1”
If so, M[2,14]<1> is set to logic "1", and if M[2,2]<0> is logic "1", M[2,14]<0> is set to logic "1". 1”, M
[2,3] If <3> is logic “1”, then M[2,
15] Set <3> to logic “1” and set M[2,
3] If <2> is logic “1” then M[2,15]<2
> is set to logic “1”, M[2,3]<1>
If M[2,15]<1> is logic "1", set M[2,15]<1> to logic "1", and if M[2,3]<0> is logic "1", M[2,15]<0> to logic "1". If logic "1" is set in M[2,1]<3>, this means that it operates every week, so M[2,2]<1><0>, M[2,3]
The contents of the data are left unchanged and the process moves on to comparison with the next time in the second information storage section. Also M[2,1]<3>
If logic “0” is set in , it means that this operation is only for one week, so M[2,1]<1><1>
<0>, M[2,0] (one of the same day of the week as the time information) is inverted to logic "0". And this result M[2,0]<3>,<2>,<1
>, <0>M [2,1] If the bits of <2>, <1>, and <0> all become logic "0", the timer information in the first information storage section is erased, and then the timer information in the second information storage section is erased. Let's move on to a comparison with the information storage section. Also M[2,0]<
3>, <2>, <1>, <0>, M[2,1]<2
>, <1>, and <0> if logic "1" still remains in any of the bits, the timer information in the first information storage section is not erased and compared with the second information storage section. Transition. When the comparison is completed for all 12 information storage units in this way, the comparison result storage unit M
[2,14]<1><0>, M[2,15]<3><2
The controlled object is operated based on the contents of ><1><0>. In this operation, if M[2,14]<1> is logic "1", the snooze operation is performed regardless of the logic of M[2,14]<0>. In this snooze operation, if the mode selection section 5 is set to a mode other than the information call mode, the operation of the sound alarm device 12 is immediately stopped by operating the "STOP" key.
After a few minutes, the sound alarm device 12 starts operating again. This snooze operation is completely stopped only when the alarm tone has been sounded for 3 minutes. This is to prevent unnecessary sounding when the user is absent. Further, when the mode selection section 5 is set to the information call mode, the sound alarm device 12 is completely stopped by operating the "STOP" key and does not start operating again. In other words, this snooze operation is used for the purpose of waking up, etc., and the mode at such times is the normal clock display mode, and even if the user operates the "STOP" key in this mode, there will be no alarm sound. It will start every 5 minutes. If the user wants to completely stop the warning sound, he or she can set the mode selection section 5 to the information display mode and then operate the "STOP" key. 3 minutes of sound during this snooze operation,
The 5-minute time count of the repetition interval is performed by the snooze counter M[1, 14]. That is, M
[2, 14] When <1> is logic “1”, M[1,
0] Set <3> and <2> to logic "1", and set M[1, 14] to 5. M[1,
0]<3> is a snooze state storage section, and when this is logic "1", the output terminal _R0 is set to logic "1" and the alarm display segment 8-1b is lit. When M[1,0]<2> is logic "1", the sound alarm device 12 is operated. And when the "STOP" key is operated in a mode other than information display mode, M
[1,0]<2> is set to logic "0" to stop the alarm sound, and M[1,14] is set to zero. Then, every minute passes, M[1, 14] is counted up by 1, and when this value reaches 5, M[1, 0] < 2
> is set to logic "1" to restart the alarm.
If the "STOP" key is not operated, M
[1, 14] becomes 6, 7, etc. every minute that passes.
...and this value becomes 8, then M[1,0]<3
> and <2> are each inverted to logic "0" and the sound alarm operation is completely stopped. Also, when the "STOP" key is operated in information display mode, M[1,0]<
3>, <2> are logic “0”, and M[1,
14] to zero to completely stop the alarm operation. In addition, even when the power is restored as described above, M[1,0]<3> is logic "1" and M[1,14] is the same as when operating the "STOP" key with this snooze operation.
is zero, which means that the alarm will start 5 minutes later when the power is restored. During the snooze operation, the status of M[1,0]<3> is displayed by the warning display segment 8-1b, but this is to notify the user that a re-warning will be sounded within 5 minutes. be. Also, M[2,14]<1> is logic “0” and M[2,
14] If <0> is logic “1”, perform an alarm operation. No matter which mode the mode selection section 5 is set to, the alarm operation will completely stop the alarm sound when the "STOP" key is operated, and the alarm sound will stop in 5 seconds even if the "STOP" key is not operated. It is an action. In other words, in this alarm operation, M[1,0]
Set only <2> to logic “1” and press “STOP”
M[1,0]<2> is inverted to logic "0" by key operation. Also, when M[1,0]<3> is logic "0" and M[1,0]<2> is logic "1", the 1-second counter M[1,2] of the clock counting section becomes 5. Then, M[1,0]<2> is inverted to logic "0". Note that M[2,14]<1> is logic “0” and M
[2,14] Even if <0> is logic “1”, M[1,
0] When <3> is logic "1", snooze operation is entered instead of alarm operation. By the way, the control of the sound alarm device 12 when M[1,0]<2> is logic "1" is based on M[1,1].
Output terminal R ₁₃ when 1/10 seconds counter is 0 to 4
This is done by setting the output terminal _R13 to logic "1" and setting the output terminal R13 to logic "0" when the signal is 5 to 9 to operate the sound frequency oscillator 10, and the sound system 12 is driven at 0.5 second intervals. Also, for on/off control based on the contents of the comparison result storage section, if M[2,15]<2> is logic "1", M[2,15]<3> is logic "1" or "0". In either case, M[2,14]<3> is set to logic “0”, M[2,15]<3> is set to logic “1”, and M
[2,15] If <2> is logic “0”, then M[2,
14] Set <3> to logic “1”. This is the first
This means that the on/off control of the power outlet circuit always gives priority to the off operation. When M[2,14]<3> becomes logic "1", output terminal _R14 becomes logic "1", and when M[2,14]<3> becomes logic "0", output terminal R14 becomes logic "_1" . is set to logic “0”. Also, if M[2,15]<0> is logic "1", M[2,14]<2 regardless of whether M[2,15]<1> is logic "1" or "0". > is logic “0”, M[2,15]<1> is logic “1”, and M
[2,15] If <0> is logic “0”, then M[2,
14] Set <2> to logic “1”. This is the second
This means that the on/off control of the power outlet circuit always gives priority to the off operation. Therefore, when information with completely opposite ON and OFF states is set in two information storage units at the same time, priority is given to the OFF operation. When each operation based on the contents of the comparison result storage unit is completed, M[2,14]<1><0>M
[2, 15] The bits of <3><2><1><0> are all set to logic "0" and the normal routine begins. Next, a hexadecimal counter is constructed as the first counting section at M[0,15], but this is provided to equalize the duty cycle of each digit in the display on the display 8. It is something. That is, each time the state of each key is checked, the state of the input terminal _K8 is determined to determine whether or not to count up the first counting section. The state of each key is judged and the period during which each digit is dynamically displayed is counted by the first counter M [0, 15].
After one cycle of determining the overall key status and displaying all digits, the count value of the first counter is added to M[1, 15] of the clock counter, and the first The counter is reset to zero. In this regard, if we directly count M[1, 15] of the clock counter without providing such a first counter, the clock counters M[1, 14], M
Since the calculation speed differs depending on the numerical values stored in [1,1] to M[1,7], the duty cycle of each digit differs, causing flickering on the display. In other words, M[1,15] is 1
M[1,
15] by one count up
Since the calculation time is different within the range up to the maximum time required to count up to the day of the week digit [1, 7], the duty cycle of each digit is different. The duty cycle of the digit also differs depending on whether M[0,15] is counted up by one or not. That is, when counting up, the number of executed instructions is greater than when not counting up, so the time for performing the next digit operation is delayed. Regarding this, dummy instructions are added so that the number of instructions is the same even when the count is not up as when the count is up, thereby making the duty cycle of each digit uniform. Figure 12 shows each digit G ₁ , G ₂ , G ₃ , G ₄ ,
This is a time chart showing the display period of G ₆ , G ₇ , G ₅ and the time interval between each digit display, where a shows the method of the embodiment of the present invention, and b and c show the method of directly counting M[1, 15]. It shows. That is, in the method of the embodiment of the present invention, each digit G ₁ ,
Display period of G ₂ , G ₃ , G ₄ , G ₆ , G ₇ , G ₅ t ₁ ~ _{t 2} , t ₃ ~
_t4 , _t5 to _t6 , _t7 to _t8 , _t9 to _t10 , _t11 to _t12 , _t13 to _t14 and the time interval between each digit display _t2 to _t3 , _t4 to t ₅ , _t6
~t ₇ , t ₈ ~ t ₉ , t ₁₀ ~ t ₁₁ , t ₁₂ ~ t ₁₃ can be made uniform, and only change by adding the count value of the first counting section to M[1, 15] Minimum time t when there is no carry at all in the upper digits ₁₇ to M[1,7]
The range is up to the maximum time _t18 when counting up to the day of the week digit is performed. In the method of directly counting this point M[1, 15], when a count-up signal is detected between digits _G1 and _G2 , b
As shown in , the time interval between digits G ₁ and G ₂ changes from t ₂ to _{t 3} at the minimum and from t ₂ to _{t 5} at the maximum, and a count-up signal is generated between digits G ₆ and G ₇ . When detected, this digit is displayed as shown in c.
The time interval between G ₆ and G ₇ is at least t ₁₀ to t ₁₁ and at most t ₁₀
The time width of which part changes and how much it changes, such as changing from ~t ₁₃ , becomes indeterminate. This causes display flickering. As described above, in the method according to the embodiment of the present invention, a first counting section is provided, and this first counting section counts commercial power supply frequency pulses, and after one cycle of determining the overall key state and displaying all digits, The count value of the first counter is M [1, 15]
In addition, dummy instructions are added to make the number of executed instructions the same whether there is a count-up or not in the first counting section.
The display period of each digit and the time interval between each digit display can be made uniform, and flickering of the display does not occur. Furthermore, information is transferred from each storage section of the RAM 32 to the display storage section in the clock display mode and the second counter display mode by transferring the information from the 1-second counter M[1, 2] of the clock counter to the lower counter M[1]. , 1] when there is a carry, that is, once per second. In addition, in the information display mode, the 1-minute counter M [1, 4] of the clock counting section and the lower counter M [1, 3]
This is done when there is a carry from , that is, once every minute. Therefore, these transfers end up transferring the count value of the first counter M[0,15] to M of the clock counter.
This will be done when the numbers are added to [1, 15] and carried for 1 second and 1 minute, respectively.
The duty cycle of each digit is not different. In this way, in the timer information setting mode, for example, if the day of the week is specified but morning or afternoon is not specified, M[0, 7] <3> of the setting storage section is pressed when the "INPUT" key for transfer is operated. <
2>, it is detected that there is no designation, and the morning and afternoon flashing modes are set in the flashing mode storage section. Then, in the morning and afternoon flashing modes, the e and f segments of the _G7 digit of the fluorescent display 8 are controlled to flash to notify the user. Also, if morning or afternoon is specified but the day of the week is not specified, "INPUT" for transfer
M[0,0]<3> in the setting storage section when a key is operated
<2><1><0>, M[0,1]<2><1>
Check <0> to detect that there is no designation, and set the day of the week blinking mode in the blinking mode storage section. By this weekday flashing mode, all day segments 8-7b, 8-6b, 8- of the fluorescent display 8
5b, 8-4b, 8-3b, 8-2c, 8-1c
The flashing is controlled to notify the user. Also, if the set time is not set to a value between 1:00 and 12:59, M [0, 4] and M in the setting storage section will be changed when operating the "INPUT" key for transfer.
[0,5], M[0,6], M[0,7]<1><0
> to detect that the specification is incorrect, and set the time blinking mode in the blinking mode storage section. In this time blinking mode, the fluorescent display 8 blinks and displays the incorrect time to notify the user. Furthermore, if the snooze information, alarm information, ON, and OFF information, which is the operation information of the controlled object, is not specified at all, M[0, 2]<1>< of the setting storage section when operating the "INPUT" key for transfer 0>, M[0,3]
, and detects that there is no specification, and sets the operating blinking mode in the blinking mode storage section. In this operating blinking mode, the b, c segments of the G ₁ digit and the b, c, e, f segments of the G ₂ digit of the fluorescent display 8 are controlled to blink to notify the user. Of course, these controls
This is performed by the CPU 31 based on the program in the ROM 33. Therefore, if there is an error in the specified timer information, the user can be informed of the part where the error is, and the user only has to re-specify the information in that part. Since the operability can be improved and the erroneous part can be clearly identified, the re-designation operation of the information can be limited and made reliable. As described in detail above, according to the present invention, when an error occurs when setting timer information, the abnormal part is determined by dividing it into each component of the timer information, and the display displays an error corresponding to each component. Therefore, it is possible to provide an electronic time limit device that can improve operability and ensure information re-designation operations.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention; FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a block diagram showing the configuration of a fluorescent display, and FIG. 3 is a block diagram showing the circuit configuration of a microcomputer. Figure 4 shows RAM
FIG. 5 is a diagram showing the configuration of the setting storage unit/display storage unit when time information is stored.
9 is a diagram showing the configuration of the setting storage/display storage unit when storing timer information, FIG. 7 is a diagram showing the configuration of the clock counting unit, FIG. 8 is a diagram showing the configuration of the information storage unit, and FIG.
10 is a diagram showing the configuration of the second counting section, FIG. 10 is an explanatory diagram of time addition processing, and FIG. 11 is a diagram showing the configuration of the setting storage and display storage section when storing the second counting section information. FIG. 12 is a time chart illustrating the display control method of the fluorescent display, in which a is a time chart showing the method of the embodiment of the present invention, and b and c are time charts showing the conventional method. DESCRIPTION OF SYMBOLS 1... Microcomputer, 5... Mode selection section, 6... Information/signal input section, 8... Fluorescent display, 12... Sound alarm device, 31... CPU (Central Processing Unit), 32... RAM (random access memory), 33...ROM (read only)
memory).

Claims (1)

[Scope of Claims] 1. A setting storage unit, one or more information storage units, and timer information specifying means for specifying and storing timer information for controlling the operation of controlled objects such as time switches and alarms in the setting storage unit; an input section comprising a timer information transfer means for transferring the timer information stored in the setting storage section by the timer information specifying means to the information storage section and storing the timer information; a display section for displaying the timer information, and a display section for each component of the timer information to determine whether or not the contents of the timer information are normal in response to a timer information transfer start signal from the timer information transfer means of the input section. A determination means for separately determining the abnormality, and an abnormality display control means for causing the display section to display an abnormality corresponding to the component determined to be abnormal when the determination means determines that the timer information is abnormal. An electronic timer characterized by: 2. The electronic timer according to claim 1, wherein the abnormality display control means displays the abnormality by blinking the display element corresponding to the component determined to be abnormal. Device. 3 The timer information includes morning and afternoon designation information,
A patent claim characterized in that the display section has display elements for AM and PM, and when AM and PM are not specified, the abnormality display control means causes the display elements for AM and PM to blink. The electronic timer according to item 2 of the scope of the invention. 4. The timer information includes day of the week designation information, and the display section has display elements for each day of the week, and when the day of the week is not designated, the abnormality display control means causes all of the display elements for each day of the week to blink. An electronic timer according to claim 2, characterized in that: 5. There are a plurality of controlled objects whose operation is controlled by timer information, the display section has a display element for each controlled object, and when the operation control of the controlled object is not specified, the abnormality display control means displays each of the above-mentioned objects. 3. The electronic timer according to claim 2, wherein all control target display elements are made to blink.