JPS62145322U - - Google Patents

Info

Publication number
JPS62145322U
JPS62145322U JP3313886U JP3313886U JPS62145322U JP S62145322 U JPS62145322 U JP S62145322U JP 3313886 U JP3313886 U JP 3313886U JP 3313886 U JP3313886 U JP 3313886U JP S62145322 U JPS62145322 U JP S62145322U
Authority
JP
Japan
Prior art keywords
adhesive layer
conductive wires
substrate
electronic
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3313886U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3313886U priority Critical patent/JPS62145322U/ja
Publication of JPS62145322U publication Critical patent/JPS62145322U/ja
Pending legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す電子回路を構成
した基板の平面図、第2図は第1図のA―A線に
よる視図である。 1…基板、2a,2b,2c,2d…導線、3
…電子素子、4…導通部、5…保護層。
FIG. 1 is a plan view of a substrate constituting an electronic circuit showing an embodiment of the present invention, and FIG. 2 is a perspective view taken along line AA in FIG. 1. 1... Board, 2a, 2b, 2c, 2d... Conductive wire, 3
...electronic element, 4...conducting part, 5...protective layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁性を有する基板に対して電子回路を構成し
、かつこの電子回路を基板と共に合成樹脂等から
成る保護層により封止することにより全体をチツ
プ化するものにおいて、基板に対して絶縁性を有
する接着層を形成し、この接着層の所定の位置に
対して電子素子、及び予め所定の長さに切断しか
つ要すれば屈曲形成した導線を配置すると共に、
これら導線及び電子素子を接着層が接着保持し、
更にこれら導線及び電子素子の導通部に対して電
気的接続手段を施すことにより電子回路を構成し
たことを特徴とするネツトワーク電子部品。
An electronic circuit is constructed on an insulating substrate, and the entire electronic circuit is sealed together with the substrate with a protective layer made of synthetic resin, etc. to form a chip, which has insulating properties with respect to the substrate. Forming an adhesive layer, arranging electronic elements and conductive wires cut to a predetermined length and bent if necessary at predetermined positions on the adhesive layer;
The adhesive layer adheres and holds these conductive wires and electronic elements,
Furthermore, a network electronic component is characterized in that an electronic circuit is constructed by providing electrical connection means to the conductive portions of these conductive wires and electronic elements.
JP3313886U 1986-03-10 1986-03-10 Pending JPS62145322U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3313886U JPS62145322U (en) 1986-03-10 1986-03-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3313886U JPS62145322U (en) 1986-03-10 1986-03-10

Publications (1)

Publication Number Publication Date
JPS62145322U true JPS62145322U (en) 1987-09-12

Family

ID=30840465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3313886U Pending JPS62145322U (en) 1986-03-10 1986-03-10

Country Status (1)

Country Link
JP (1) JPS62145322U (en)

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