JPS62134720A - Digital signal selecting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements and an operation time, and to improve the reliability by constituting the titled circuit by using almost the same module by a gate array, etc., and executing a processing in parallel even in case the number of digital signals for fetching the minimum value has increased. CONSTITUTION:In the second logic circuit 2, P1=0, Q1=1, and R1=0, they are inputted to OR circuits (gate) 211-213 together with a control signal, its output is inputted to an AND circuit 201, and the minimum value bit signal Z1 outputs '1'. At the same time, this signal is inputted to an invertor 202, and '0' which is outputted from the inverter 202 is inputted to AND circuits 221-223, respectively, together with outputs of the OR circuits 211-213. Outputs of the AND circuits 221-223 become all '0', and control signals outputted from OR circuits 231-233 become 101, respectively in accordance with digital signals P, Q, and R, in the same way as the control signal which has been inputted from the second logic circuit 3, and outputted to the second logic circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal selection circuit, and more particularly to a digital signal selection circuit that extracts a digital signal having a minimum value from among a plurality of digital signals.

[Conventional technology]

Conventionally, in order to extract a digital signal with the minimum value from among a large number of digital signals, a comparator is used to compare two input digital signals and detect which one is larger, and a is basically a selector that extracts one digital signal, and as the number of digital signals to extract all minimum values increases, the rate of increase in the number of these elements exceeds the rate of increase in the number of digital signals ↓ Become. Since the number of comparison processes increases, the calculation time also increases. Below, we will focus on the configuration and operation of a digital signal selection circuit according to the conventional technology, as shown in Figures 4 and 5 (a) and (b).
A brief explanation will be given with reference to t=.

Referring to FIG. 4, an example of a conventional configuration of a digital signal selection circuit having two digital signal inputs includes a comparator (501) and a selector 602.

Each bit Po- of the digital signal P consisting of 4 bits
P3 (Po indicates the least significant bit + P3 indicates the most significant bit, the same applies hereinafter) and each bit signal Q of the digital signal Q,
−Q, is input to the comparator 601 and the selector 602.

A comparator 601 discriminates between digital signals P and Q, and if P is smaller than Q, the output discrimination signal M is 1.
In other cases, the discrimination signal N1 becomes 0. Next, in the selector 602, when the discrimination signal M is 1, the digital signal P is set as the minimum f-force signal Z, and each bit signal 2. −
23 is output.

When discrimination No. 18 is O, the digital signal Q is the minimum value signal Z
The type of signal indicating the minimum value and its value are output.

Next, looking at FIG. 5(, l), an example of a conventional configuration of a digital signal selection circuit having four digital signal inputs includes comparators 701 to 703 and selectors 704 to 707.
06 and a converter 707. Each bit signal Po-P3 of the digital signal P and each bit signal Qo=Q3 of the digital signal Q, each consisting of 4 bits, are input to a comparator 701 and a selector 704. Further, each bit signal Ro-R3 of the digital signal and each bit signal 5o-S3 of the digital signal S are input to the comparator 702 and the selector 705. Selectors 704 and 70 according to the discrimination signals MO-M output from comparators 701 and 702
The digital signals input from 5 to 5 are compared and the smaller signal is output.

These digital signals are sent to a comparator 703 and a selector 70.
6 and is output from the comparator 703.
2, the selector 706 outputs each bit signal 2o-23 of the minimum value signal Z.

In addition, the converter 707 is shown in the explanatory diagram of FIG. 5(b).
The type of digital signal that becomes the minimum value signal (P-
8) is determined.

Furthermore, when the number of input digital signals is doubled, in order to select the digital signal having the minimum value from among them, two sets of circuit elements shown in FIG. 5(a) are collected, and these two sets of circuit elements are Results obtained from the devices need to be further compared. Therefore, the number of elements in the digital signal selection circuit is increasing faster than the number of input digital signals, and as a result, operations are being performed vertically, and new devices such as converters are being used. An element is also required.

[Problem that the invention seeks to solve]

The problem with the conventional technology that the present invention aims to solve is that, as described above, when the number of digital signals from which the minimum value is to be extracted increases, the increase rate of the elements constituting the Tesimer signal selection circuit is greater than this increase rate. The problem is that the scale becomes large and the calculation time increases.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital signal selection circuit which solves the above-mentioned drawbacks.

[Failure to solve the problem]

The digital signal selection circuit of the present invention is a digital signal selection circuit that selects a digital signal having the minimum value from among several digital signals. A first logical product output signal representing the logical product of each of the bit signals is input, and an inverted signal of the first logical product output signal and the highest significant bit signal are respectively output. a first logic circuit that outputs a first cascaded control signal representing a logical product of outputting a second logical product output signal representing a logical loss of a plurality of logical sum signals representing a logic 11f with a bit signal of the second digit of the digital signal corresponding to the digital signal; a signal representing the logical product of each of the logical sum signals corresponding to the inverted signal and the digital signal, and a first cascaded control signal corresponding to the same digital signal as the logical sum signal among the first cascaded control signals; and a second logic circuit that outputs a second cascade control signal representing a logical sum to the next stage for each of the plurality of digital signals, and the plurality of logic circuits have the same configuration as the second logic circuit. bit signals of corresponding digits of the plurality of digital signals are input to each logic circuit corresponding to the third digit to the least significant digit. and a plurality of signals representing the logical sum of a cascaded control signal outputted from the preceding stage for each of the plurality of digital signals, and a bit signal of the digital signal corresponding to the cascaded control signal among the bit signals of the plurality of digital signals. A logical product output signal representing the logical product of the plurality of logical sum signals is output, and an inverted signal of this signal and a signal representing the logical product of the plurality of logical sum signals corresponding to the digital signal are output from the previous stage. Among the output cascade control signals, a signal representing the logical sum of the logical sum signal and a cascade control signal corresponding to the same digital signal is used as a cascade control signal of the corresponding logic circuit, and is sent to the next stage for each of the plurality of digital signals. It is configured with the feature of output.

Embodiments] Next, the present invention will be described in detail with reference to drawings showing embodiments. FIG. 1 is a block diagram showing an overview of the present invention, FIG. 2 is a block diagram showing the configuration of a first embodiment of the present invention,
FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

First, an outline of an embodiment of the present invention will be explained with reference to FIG.

In the digital signal selection circuit of the present invention, the plurality of digital signals P-Q---Y are the bit signals PN-1-Q of the highest digit.
N-1-1-YN- or lowest digit bit signal Po-
It is separated into Qo---Yo, and each digit is input to the logic circuit. Each bit signal input to the logic circuit for each digit passes through a gate and sequentially outputs its AND signal, and the value is converted into the minimum value signal Z as the minimum value bit signal ZN-,--
-z Output in the order of 1 and Zo.

Compare each bit of the digital signal of the digit in sequence starting from the highest digit, and if the bit is composed of O and 1, output 0 as the value of that digit,
The control signal whose bit signal of the digital signal corresponds to 1 is
The selection circuit is configured so that all digits below n are set to 1 and excluded from the comparison judgment, and the digits below this number are sequentially compared and judged until the lowest digit is reached. Therefore, among the control signals (i.e., discrimination signals) output from the lowest digit, the digital signal corresponding to the control signal whose output is O is the smallest, and that area is output for each digit. Note that when the bit signals to be compared and determined are all the same, that value is output as the value of that digit, and O is output as the control signal corresponding to the bit signal to be compared and determined.

First logic circuit LCN that inputs the bit signal of the highest digit
-1, the highest digit bit signal PN-1-QN-1---
YN-, and outputs the AND of these as a L/J% value bit signal ZN-1. The control signal corresponding to the input digital signal whose highest digit bit signal is 0 becomes O, and the Oki J control signal corresponding to the input digital signal whose highest digit bit signal is 1 becomes 1, They are output to the second logic circuits LC, , respectively. It should be noted that even if all input highest bit bit signals are the same, all output control signals will be 0. Further, when the control signal becomes 1, all the control signals of the digital signals corresponding to the lower digits become 1 and are not subject to discrimination. A second logic circuit LC (1
-LCl---LCH-z, the input control signal is 0
The logical product of the bit signals of each digital signal is output as an overall minimum value bit signal ZN-4---Z2.zI. When the bit signal of a digital signal corresponding to a control signal whose value is 0 is composed of O and 1, the control signal corresponding to that digital signal becomes O or 1 according to the value of that bit signal, and all If they are the same, the control signal corresponding to that digital signal will also be 0. Control signals corresponding to other digital signals become l and are output to the second logic circuit of the next digit.

Among the control signals output from the second logic circuit LCo of the lowest digit (i.e., the discrimination signal Zp-ZQ ---Zy), the digital signal corresponding to the control signal whose value is 0 is the one indicated by its minimum value. , its value is 2.

In the above explanation of the circuit outline, we have talked about digital signals expressed in binary system (straight binary system), but 1 is assigned from high-order digits to low-order digits, and one digit is As long as the condition that 1 is greater than 0 is satisfied, other representation systems (for example, binary IO base system) can also be applied.

Next, an embodiment of the present invention will be described, focusing on its configuration and operation. As shown in FIG. 2, the first embodiment of the present invention includes a first logic circuit 4 and second logic circuits 1 to 3.
Three digit digital signals are compared and the digital signal having the minimum value is extracted. Digital signal P-
QR is separated into the highest digit bit signal P3, Q3, 几3 or the lowest digit bit signal Po-Qo-几◎, and a first logic circuit 4 and a second logic circuit 1 are connected for each digit. ~
Enter into 3. Here P=1101. Q=lO1l.

If 几=llOO, then P3=l, Q3=l, and R8=1, so the bit signals P3, Q3, and R3 are connected to the AND circuit 4.
When the minimum value bit signal Z3 is input to 01, 1 is output. At the same time, this signal is input to the inverter 402, and the 0 output from the inverter 402 is the bit signal P3/Q3.
- Simultaneously with 几3, it is input to AND circuits 421 to 423, respectively. Therefore, the control signal O is output from the AND circuits 421, 422, and 423, and the second logic circuit 3
Output to.

In the second logic circuit 3, P2=l, Q2=0゜几,=
l, and the bit signals P2, Q2, and ordinary! enters the OR circuits (gates) 311 to 313 together with the control signal output from the first logic circuit 4, and its output is the digital signal P.
-Q-R correspond to l, 0, and l, respectively, and these are input to the AND circuit 301, and the minimum value bit signal Z2 is 0.
outputs.

At the same time, this signal is input to the inverter 302, and l output from the inverter 302 is input to the OR circuits 311 to 31.
3 are input to AND circuits 321 to 323, respectively.

The outputs of the AND circuits 321 to 323 are digital signals P-Q
-R corresponds to 1, 0, and 1, respectively, and are input to the OR circuits 331 to 333 together with the outputs (i.e., control signals) of the AND circuits 421 to 423, respectively, and the outputs are converted to the digital signals P-Q and 几. Correspondingly, they become 1 and 0-1, respectively, and are outputted to the second logic circuit 2 as a control signal. Therefore, the output of the 11m1 logic circuit 332 becomes O, and the control signal corresponding to the digital signal Q becomes 0. Also, since the outputs of the OR circuits 331 and 333 become 1, the digital 1
Control No. 18 corresponding to No. 5 PR has 1 up to the lowest digit.

In the second logic circuit 2, P1=O2Q1=l, R1=0
, and the logical sum circuit (gate) 211 to
213, its output is input to the AND circuit 201, and 1 is output as the minimum value bit signal 21. At the same time, this signal is input to the inverter 202, and the inverter 202
0 outputted from the logical sum circuits 211 to 213 are input to the logical product circuits 221 to 223, respectively.

The outputs of the AND circuits 221 to 223 are all 0, and the control signals output from the OR circuits 231' to 233 are as follows.
Similarly to the control signal inputted from the second logic circuit 3, the output signal becomes 101 corresponding to the digital signals P, Q, and R, respectively, and is output to the second logic circuit 1.

In the second logic circuit l, Pn=l l Qo=1,
ft1=0, and the output is input to the logical sum circuits (gates) 111 to 113 together with the control signal, and the output thereof is input to the logical product circuit 101, and the minimum value bit signal Z is input.

outputs 1. At the same time, this signal is transferred to the inverter 102
O inputted into the inverter 102 and outputted from the inverter 102 are inputted to the AND circuits 121 to 123, respectively, together with the outputs of the OR circuits Ill to 113.

The outputs of the AND circuits 121-123 are all 0, and the "condolence" signal ZP output from the OR circuits 131-133.
-ZR is 1, but the discrimination signal ZQ is 0. Therefore, the digital signal Q shows the minimum value from the discrimination signal, and that value becomes the minimum value signal Z, that is, 1011.

In this example, two logic circuits mainly consisting of gate arrays are used.
If the module is made in advance as a type of module, the number of digits can be freely selected, and if the design is designed with a margin in the number of digital signals in advance, a general-purpose selection circuit can be constructed.

In addition, even if the number of digital signals increases, sorting 1
Since the processing is executed in parallel, the processing time is approximately constant. Note that the discrimination signal ZP-ZR indicating the minimum signal of the digital signals P to I(,
It is also possible to connect an inverter to the output of P-ZR and determine if the output becomes 1.

As shown in FIG. 3, the second embodiment of the present invention is equipped with second logic circuits 11 to 14, and is configured to input three 4-digit digital signals and extract the digital signal having the maximum value. It has become. The digital signal P-Q-it is a bit signal of the highest digit P3, Q3, or a bit signal of the lowest digit.
It is separated into bins Hg from jji Po to Qo to ◎, and inputs each digit to the second logic circuit 11-14. The result is the minimum value signal 2 (bit signal 2.-2
3) is output from the second logic circuits 11 to 14, and a signal ZP-2Q-ZR is used to determine the type of digital signal.
It is the same as the first embodiment that the determination is made when the corresponding signal in 0 becomes 0, so only the differences between the two embodiments will be described below.

The second logic circuit 14 to which the highest-order bit signals P3, Q3, and R3 are input is provided with an input terminal for a control signal, unlike the first logic circuit 4 in the first embodiment. If the input terminals of these control signals are collectively added with a signal A that becomes 0, the OR circuits 511 to 513 will have input/output functions similar to those of direct connection, and the second logic circuit 14 will be the same as the one in the first embodiment. The operation is the same as that of the first logic circuit 4.

Therefore, in this embodiment, if one type of logic circuit module, mainly a gate array, is created in advance, the number of digits can be freely selected, and the design can be designed with a margin in advance for the number of digital signals. In this case, a more efficient selection circuit than the first embodiment can be constructed. Further, even when the number of digital signals increases, since the sorting process is executed in parallel, the processing time is almost constant, which is the same as in the first embodiment.

〔Effect of the invention〕

The digital signal selection circuit of the present invention is configured using almost the same module f: such as a gate array, so that even when the number of digital signals from which the minimum value is to be extracted increases, processing is performed in parallel. Therefore, the number of elements and calculation time are reduced, and reliability is also improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an overview of an embodiment of the present invention, Fig. 2 is a lock diagram showing the configuration of the first embodiment of the invention, and Fig. 3 is a configuration of the second embodiment of the invention. A block diagram showing
FIG. 4 is a block diagram showing the configuration of an example of the conventional technology, FIG. 5(a) is a block diagram showing the configuration of another example of the conventional technology, and FIG. 5(b) shows the operation of the converter. Explanatory diagram. L cN-, ...... first logic circuit, LC, ~L
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Claims (1)

[Claims] In a digital signal selection circuit that selects a digital signal having a minimum value from among a plurality of digital signals, a bit signal of the highest digit of a plurality of digital signals having a predetermined number of digits. is input, a first logical product output signal representing the logical product of the respective bit signals is outputted, and the logical product of the inverted signal of the first logical product output signal and each of the bit signals of the highest digit is calculated. a first logic circuit that outputs a first cascaded control signal representing the plurality of digital signals in correspondence with the plurality of digital signals; A second logical product output signal representing the logical product of a plurality of logical sum signals representing a logical sum with the bit signal of the second digit is output, and an inverted signal of the second logical product output signal and a digital signal are output. a second signal representing the logical product of each of the corresponding logical sum signals and a first cascaded control signal corresponding to the same digital signal as the logical sum signal among the first cascaded control signals; a second logic circuit that outputs a cascade control signal for each of the plurality of digital signals to the next stage, and a logic circuit having the same configuration as the second logic circuit as a third logic circuit of the plurality of digital signals. A bit signal of the corresponding digit of the plurality of digital signals is inputted to each logic circuit corresponding to the third digit to the least significant digit, and the bit signal of the corresponding digit of the plurality of digital signals is A logical product of a plurality of logical sum signals representing the logical sum of the cascaded control signal outputted from the previous stage for each signal and the bit signal of the digital signal corresponding to the cascaded control signal among the bit signals of the plurality of digital signals. outputs an AND output signal representing the inverted signal of this signal, a signal representing the AND of each of the plurality of OR signals corresponding to the digital signal, and the logical OR of the cascade control signal output from the previous stage; A digital signal selection circuit characterized in that a signal representing the logical sum of the signal and a cascade control signal corresponding to the same digital signal is outputted to the next stage for each of the plurality of digital signals as a cascade control signal of the corresponding logic circuit. .