JPH04112362A - Accumulation circuit - Google Patents

Abstract

PURPOSE:To reduce the scale and the power consumption of an accumulation circuit by providing a selection control circuit which compares the interim result of an accumulating operation with the saturation level of a threshold circuit, decides the continuation of arithmetic operations to the inputs received from other input terminals, and outputs the interim result of the accumulating operation that should be continued. CONSTITUTION:The interim result value of an accumulating operation is compared with the threshold value level of a threshold circuit 19 by means of the saturation characteristic of the circuit 19 for the output stages of the accumulated values of the 1st coefficient arithmetic circuits 4211-421k and 42m1-42mk and the 1st adder circuits 4311-43k-1 and 43m1-43m.k-1 corresponding to the inputs given from the input terminals 401-40k and 40K+1-40n respectively. If the saturation level of the circuit 19 is high, the accumulating operation of other input signals is eliminated halfway. Thus the scale and the power consumption can be reduced for an accumulation circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an accumulation circuit, and in particular to an accumulation circuit used to calculate correlations between a large number of inputs and counts in pattern recognition and neural network circuit operations. Regarding.

Neural network circuits model biological neural circuits m to realize pattern recognition processing such as character recognition and speech recognition, optimization problems, robot control, etc., which were difficult with conventional Neumann type computers. Conventional Neumann type computers require a huge amount of calculation time to perform sequential processing according to the program, whereas neural network circuits have extremely high processing speeds because they can perform calculations in parallel using neuron circuits. In addition, by configuring a network by connecting many identical neuron circuits, even if there is a faulty circuit, it can be easily replaced with another normal circuit. realizable. There is a need to reduce the circuit scale of accumulation circuits used as such neural network circuits.

[Conventional technology]

FIG. 4 shows a block diagram of an accumulation circuit used in a conventional neural network circuit.

40-40. are input terminals, 4111-41. ,. is a memory circuit, 421□~42m, is a coefficient calculation circuit, 431
, ~43- are adder circuits, 44. ~44. is a threshold circuit, 4
51-45. is an output terminal, 46. -46 are unit circuits.

The accumulation circuit has n input terminals 401 (n is an integer greater than or equal to 1).
~40fi and m output terminals 4 (m is an integer greater than or equal to 1)
5. ~45. It has m unit circuits 461 to 46 . of the same structure. , is made up of.

Unit circuits 46□ to 46□ have n input terminals 40, to 40
A coefficient calculating circuit 42 which calculates the difference between the signal from ゜ and the coefficient stored in the memory circuits 41, 1 to 41, ゎ, the distance, or the load value based on the coefficient. .

~42. n afi and n coefficient calculation circuits 421
~42. . An adder circuit 433 that adds all the outputs of . ~4
3. ffi and one threshold circuit 441 to 44. It is composed of.

The threshold circuits 441 to 44, which ultimately determine the output value, have transfer characteristics as shown in FIG. The sigmoid function form shown in figure (C) is the most versatile to represent the transfer characteristic, but the step function form shown in figure (A) and the step function form shown in figure (B) are the most versatile.
) is often used as a simplified version like the polygonal line.

m unit circuits 46. ~46. ．． have their own coefficients, for example, the unit circuits 461 to 46 . for pattern recognition. Output terminals 45, -45. The output from the input terminals 401-40. exceeds the threshold level of the threshold circuits 441-441 and becomes a high level. It is possible to recognize input patterns from

[Invention or problem to be solved]

However, the conventional accumulator circuit of FIG. 4 processes each unit circuit 46 . .about.46 can perform calculations in parallel, which has the advantage of being able to perform calculations at high speed. However, n input terminals 401 to 40 .
and m output terminals 45, to 45. In the network having coefficient calculation circuits 42,1 to 42. , , and the addition circuit 43
1. ~43.6 is required approximately in nm pieces. Number of output terminals m
Since it is necessary to increase the size according to the number of categories to be recognized in pattern recognition etc., the coefficient calculation circuit 42, 1 to 4
The number of circuits (nm) of the adder circuits 4311 to 43 .2- and the adder circuits 4311 to 43 . . However, since they operate in parallel at the same time, the power consumption associated with the circuit operation becomes extremely large, which has been a major problem when converting the accumulation circuit into an LSI.

The present invention has been made in view of the above points, and an object of the present invention is to provide an accumulation circuit that can reduce the circuit size and power consumption of the accumulation circuit without impairing the advantage of the conventional accumulation circuit in that it can perform high-speed calculations. do.

[Means to solve the problem]

The present invention includes n (n is an integer greater than 1) input terminals;
It has m output terminals (m is an integer greater than 1), has m coefficient sets each consisting of unique n coefficients, and for every coefficient set, i (i is an integer from l to n). The difference or distance between the th coefficient and the 1st input terminal signal or the weight value due to the coefficient is determined by the coefficient calculation circuit as a single polarity coefficient calculation value, and all the coefficient calculation values from 1 to n are accumulated. When performing a series of calculations in which the output signal is the converted value obtained by thresholding the accumulated results, from 1 to k
(k is an integer greater than or equal to 1 and less than n) For the input terminal signal, in order to obtain the coefficient calculation value, a first coefficient calculation circuit dedicated to one coefficient, and a first coefficient calculation circuit dedicated to each coefficient, m sets of circuits each having a first adder circuit for accumulating the outputs of the arithmetic circuits are arranged in parallel, and the intermediate results of m accumulations are compared with the saturation level of the threshold circuit to calculate the input from the remaining input terminals. It is equipped with a selection control circuit that determines whether to continue the calculation for the calculation and outputs the intermediate result of the necessary accumulation, and determines whether to continue the calculation or outputs the intermediate result of necessary accumulation. The circuit and the second addition circuit are used in common to switch the input terminal signal and coefficient value to continue the accumulation operation, input the accumulation results for the 1st to nth input terminals to the threshold circuit, and calculate the processing results of the threshold circuit. is output to the output terminal.

[Effect]

The present invention utilizes the saturation characteristics of the threshold circuit in the output stage of the cumulative value of the first coefficient calculation circuit and the first addition circuit corresponding to the input from each input terminal to calculate the value of the cumulative intermediate result and the threshold circuit. The number of arithmetic circuits can be significantly reduced by comparing the threshold levels of and omitting the cumulative calculation of the remaining input signals if the threshold circuit is at the saturation level or high level.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention.

In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted.

10 is a selection control circuit, 12 is a coefficient RAM circuit, 14 is a register circuit, and 20 is a centralized calculation unit, which includes a plurality of register circuits 14+ to 14. and coefficient calculation circuits 15+ to 15.
-, , addition circuits 171 to 17, .

18 is an output register circuit, and 19 is a threshold circuit.

Further, the numbers of n input terminals 40 and m output terminals 45 are the same as in FIG. 4. Furthermore, input terminals 401-. 4
For a signal of 0, the coefficient calculation circuits 42++ to 421 and the addition circuit 43 are operated in parallel according to all calculations as in the conventional case.
, 1 to 43+tk-n. This corresponds to the rows of input terminals INI to IN4 in FIG. 3, which will be described later.

Reference numeral 100 denotes a parallel calculation unit that performs parallel calculation processing based on inputs to input terminals 401-40.

On the other hand, input terminal 40Lk+z~40. In response to the input, only the centralized calculation unit 20 shown in FIG. 1 executes the calculation. This is the input terminal INS in Figure 3, which will be described later.
The following columns apply.

Input terminal 40. ~40. The intermediate results of the calculations for m output terminals 45. ~45. There are m pieces corresponding to , and all of them are input to the selection control circuit 10 .

The selection control circuit 10 holds information on the saturation level of the threshold circuit 19 in advance, and compares the intermediate result of the accumulation with the saturation level of the threshold circuit 19.

As a result, if the saturation level of the threshold circuit 19 is not reached, the selection control circuit IO operates the m adder circuits 43.1 to 43.
. -1, one of the intermediate results of the calculation is selected and input to the centralized calculation section 20. At this time, the selection control circuit 10 outputs the output terminal 45. Which output terminal 45. ~4
5. It simultaneously outputs as an address signal whether the signal corresponding to is selected. The address signal is input to the coefficient RAM circuit 12 and the output register circuit 18.

Further, the selection control circuit 10 compares the saturation level of the threshold circuit 19 with the cumulative result, and if the saturation level has been reached,
For the next input, an address signal is outputted so that the centralized calculation section 20 performs the calculation.

The coefficient RAM circuit 12 reads out necessary coefficient data in accordance with the address signal of the selection control circuit 10 and outputs it to the centralized calculation unit 20.
The register circuit corresponding to the input terminal of 14. ~14 n-
Transfer to k.

The transferred coefficient data is input terminal 40Lk++~40
, and the coefficient calculation units 151 to 15. which correspond to the input signals of the input terminals of the centralized calculation unit 16. , the calculation is executed, and the addition circuit 17. ~17. ．． The cumulative results of the calculations for all inputs are accumulated with the intermediate results of the calculations, and are input to the threshold circuit 1.9.

The output signal of the threshold circuit 19 is input to the output register circuit 18. On the other hand, output terminals 45t to 45. selected by the address signal from the selection control circuit IO. The signal is output by the output register circuit 18, and the output register circuit 18 holds the output signal.

In this way, most of the arithmetic circuits for inputs from +11 to 40□ to the input terminal 40+ are omitted.

FIG. 2 shows a block diagram of another embodiment of the invention.

In the figure, the same components as in FIGS. 4 and 1 are denoted by the same reference numerals, and their explanations will be omitted.

The configuration of the centralized calculation section 35 of this embodiment is different from that of the centralized calculation section 20 of the first embodiment. 21 is a switch, 22.2
4 is a switch circuit, 26 is a coefficient calculation unit, 28 is an accumulation register circuit (ACC), 29 is an adder circuit, 33. ~3
3. ．． is a register circuit for coefficient data.

In this embodiment, the configuration of the centralized calculation unit 35 is shown in FIG. 2. In order to further reduce the circuit scale of the coefficient calculation circuit I5 and the adder circuit 17 of the centralized calculation unit 2o in FIG. ACC) 28 and switch circuits 22 and 24, a set of coefficient calculation circuits 26 and addition circuits 29 are configured to perform calculations on input signals from +11 to +40 to input terminal 40+.

That is, in the second embodiment, switch circuits 22 and 24 are provided at the two inputs of the coefficient calculation circuit 26, respectively, and the input terminals 40+
Input signals from +11 to 40□ and coefficient RAM circuit 12
The coefficients from

Further, the cumulative pig signal accumulated by the parallel calculation unit 100 is taken out from the selection control circuit IO, and the switch 21 is activated as shown in the figure.
Tilt it to the left and input it to the ACC register circuit 28. Once the accumulated data is taken out, the switch 21 is turned to the right in the figure. The coefficient calculation circuit 26 calculates the switched coefficient and the input signal, and the added value is added to the value from the register circuit 28 in the addition circuit 29. The result is input to the threshold circuit 19, and then sent to the output terminal via the output register circuit 18. It is output at 451 to 45 degrees.

As a result, the scale of the arithmetic circuit for the inputs to the input terminals 4 (lfk+11 to 40.) is further reduced compared to the first embodiment.

FIG. 3 shows the operation of the accumulator circuit. Corresponding to the conventional accumulation circuit, the coefficient calculation circuit 42, addition circuit 43, and coefficient memory circuit 41 are considered as one cell. FIG. 3 shows the calculation operation of each cell in the case where the number of input terminals n is 8 and the number of output terminals m is 6.

The coefficient calculating circuit 42 generally calculates the error or distance between an input signal and a coefficient in pattern recognition or the like. In that case, the output of the coefficient calculation circuit 42 is a positive number. On the other hand, the threshold circuit 19 has saturation characteristics as shown in FIG.

With saturation characteristics, the output level does not change when the input level exceeds a certain value. In other words, when the output level reaches the saturation level, the output level will not change even if the input level increases beyond that level. Therefore, when a positive number cumulative operation is combined with the threshold circuit 19, the cumulative result only increases monotonically, and if the output level or saturation level is reached during the accumulation, subsequent calculations can be omitted. .

FIG. 3 shows cells 30 that require calculations and cells 32 that require calculations to be omitted or required. In the figure, the only column in which calculations must be performed for all cells is the eighth column. At this time, the rows of input terminals IN1 to IN4 have many cells that require calculations, but the rows of input terminals IN5 to INS have cells that do not require calculations, except for the eighth column. Therefore, for the rows of input terminals INI to IN4, calculations are performed in the parallel calculation unit 100 shown in FIGS. 1 and 2, while for the rows of input terminals IN5 to IN8, the centralized calculation unit 20.
5 and perform the calculation.

Generally, in pattern recognition, one of the
The outputs are designed to react and classify the input patterns into categories.

Even in neural network circuits, only a small number of outputs react, and most outputs do not. Therefore, operation as shown in FIG. 3 is a characteristic found in many applications. In the example shown in the figure, it is clear that only the calculation circuit 42 in the 8th column is required to perform calculations after the input terminal INS, and most of the other calculation circuits can be omitted. Does the arrangement of cells 30 that require calculations and cells 32 that do not require calculations change depending on the input signal?Since unnecessary cells are distributed in a form similar to that shown in FIG. 3 even in response to input signals, the present invention Even if the arithmetic circuit is omitted, the same arithmetic operations as in the conventional accumulator circuit can be performed.

〔Effect of the invention〕

As described above, according to the present invention, the circuit scale can be significantly reduced with almost no reduction in calculation speed compared to conventional accumulation circuits. Moreover, with the omission of the arithmetic circuit, power consumption can also be significantly reduced.

Furthermore, when implementing hardware for pattern recognition circuits and neural network circuits, the number of unit circuits required varies depending on the application; for boat fishing, the larger the number of circuits, the better the processing power. Therefore, it is expected that LSIs equipped with a large number of unit circuits will be realized. However, due to chip size limitations, there is a limit to the amount of circuitry that can be mounted on a single chip, and there are also limits to the amount of power that can be consumed by a single chip due to heat dissipation and mounting issues. Therefore, the present invention is extremely useful in practice in that reducing circuit scale and power consumption are the most important issues in order for an LSI to exhibit practical performance.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of another embodiment of the invention, Fig. 3 is a diagram showing the operation of an accumulation circuit, and Fig. 4 is a diagram of a conventional accumulation circuit. FIG. 5, which is a configuration diagram of an example of the circuit, is a diagram showing the transfer characteristics of the threshold circuit. 10... Selection control circuit, 12... Coefficient RAM circuit,
14, ~14. k...Register circuit, 15. ~15,
,．． 26... Coefficient calculation circuit, 17. ~+7. ．． ...
Addition circuit, 18... Output register circuit, 19... Threshold circuit, 20... Centralized calculation unit, 40° to 40, . 40
□Ya...~40. ．． ...input terminal, 42. . ~42□, 43. ~43□−z 45+~45°・
...Output terminal. Patent applicant Nippon Telegraph and Telephone Corporation Transfer characteristic diagram of threshold circuit (C) Sigmoid function form

Claims (1)

[Claims] A coefficient set having n (n is an integer greater than 1) input terminals and m (m is an integer greater than 1) output terminals, and is composed of unique n coefficients. There are m sets, and for all coefficient sets, the difference or distance between the i-th coefficient and the i-th input terminal signal, or the weight value due to the coefficient, etc., is calculated using a coefficient calculation circuit with a single polarity. When performing a series of calculations in which all the coefficient calculation values from 1 to n are accumulated, and the output signal is the converted value obtained by thresholding this cumulative result, from 1 to k (k is an integer greater than or equal to 1 and less than n) For the input terminal signal, a first coefficient calculation circuit dedicated to each coefficient is used to obtain the coefficient calculation value, and a first coefficient calculation circuit dedicated to each coefficient is used to calculate the coefficient calculation value from 1 to k. The first step is to accumulate the output of the circuit.
m sets of circuits having adder circuits are arranged in parallel, and the intermediate results of m accumulations are compared with the saturation level of the threshold circuit to determine whether to continue the operation on the inputs from the remaining input terminals, and It is equipped with a selection control circuit that outputs an intermediate result of accumulation that requires continuation, and uses one or several second coefficient calculation circuits and second addition circuits in common for inputs that require continuation of calculation. continues the cumulative calculation by switching the input terminal signal and the coefficient value, inputting the cumulative results for the 1st to nth input terminals to a threshold circuit, and outputting the processing results of the threshold circuit to the output terminal. Accumulation circuit.