JPS62128322A - Input/output control system - Google Patents

Abstract

PURPOSE:To perform the logical copy of a file from a DKU to an MTU lowering a termination frequency in a tape travel by providing a table which describes the position or the size of a buffer where the data of plural blocks obtained from the DKU are stored. CONSTITUTION:A CPU1 transfers in order a file requested to copy from a DKU5 to an MMU10. When appropriate number of blocks are read from the DKU5, the CPU1 generates the first table to start up an MTU3. In a generated table, the position or the size of the buffer in which the data of plural blocks are stored is described, and an MTC2 receives it from the MMU10 and performs the readout of the data from the buffer and a transfer to the MTU3 according to the content of the table, and only the share of the number of blocks of the data included in the table can be outputted continuously to the MTU3. Thereby, the termination frequency of a magnetic tape can be lowered, and also, an interruption from the MTC2 to the CPU1 is performed once for the number of blocks included in the table in a normal operation, thereby a load on the CPU1 being reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an input/output control method, and in particular operates a magnetic tape control device according to instructions output from a central processing unit, and operates a magnetic disk device via a main storage device. and G with a streaming function (input/output that enables logical copying of files between tape devices at high speed without stopping the magnetic tape, and maximizes the performance of the streaming function). Regarding control method.

(Prior Art) Conventionally, as shown in FIG.
(hereinafter referred to as DKU) 4 via a magnetic disk device (hereinafter referred to as DKU
In an information processing system in which a magnetic tape controller C (hereinafter referred to as MTC) 5 is connected to a +ffff- tape unit (hereinafter referred to as MTU) 3, a
The operation of logically copying a file stored in KU5 to MTU3 has been performed as follows, for example, along the flow shown in FIG.

That is, when a read command for DKU5 is output from CP LJ l to DKC4, DKC4 decodes this and first moves the head of DK tJ 5 to the position where the necessary information (file) is stored. A seek command is sent to the DKU5, and then, when the soak operation is completed, a data read command is sent to the KU5. When D'KU 5 receives a read command, it finds the beginning of the indicated information (file) and transfers one block of information in the file to DKC 4.

When the DKC4 receives one block of information from the oK IJ 5, it uses direct memory access (DMA) to transfer this information to the main memory in the CPtJ I (hereinafter M
(referred to as MU) and transfers to C after completing the necessary transfer.
When CI (CI) receives the above notification, it issues a write command to M T U 3 and sends a write command to M T U 3.
Send to U2. This write command is decoded by MTU2, the write command is sent to M T [J 3, and MTU2
U3 starts running the magnetic tape. The MTU 2 also receives one block of information from the CPU 1 by DMA, and sends it to the MTU 3 to record it on the magnetic tape.

When the MTU 2 completes the transfer of information for one block, it generates an interrupt to cP U l and notifies it of the end of the write operation.

When the above interrupt occurs, CPU 1 repeats the same operation as above for the number of blocks in
, complete the necessary logical copy.

[Problem that the invention seeks to solve]

By the way, the MTU3 has a so-called streaming function. This is a function that, after recording input information in a certain block, writes an inter-record gap (IRG) without stopping tape running and continuously moves to the recording operation of the next block. However, for this streaming function to work, it is necessary that the write information for the next block is already prepared while writing the IRG, and if the information is prepared and the chair write command is not input again within a predetermined period. , tape running stops. Since the MTU3 requires about 500 m5ec on average to go from a stopped state to a predetermined running state, it is necessary to make maximum use of the streaming Wii U in order to perform high-speed writing.

However, a file handled by software is a collection of blocks, and one block is also a collection of records. Although such files are logically connected, they are often recorded in physically discontinuous positions on the DKUS. Therefore, the seek time of l) K tJ 5 described above requires, for example, about 30 m5ec on average. In addition, in the conventional method, information for one block and one cook from the DKU5 is transferred to the CPU
Each time data is transferred to MMUIO, DKC4 interrupts central processing unit 1, and each time one block of information + μ is written to MTU3, MTU2 issues an interrupt to CP [J l to transfer the next block. CP IJ I is configured to receive many interrupts.
MTU
During the IRG processing in step 3, the next block of data could not be prepared in MTU2, and the streaming function could not be used to its fullest extent.

For this reason, the MTU3 has the disadvantage that it is necessary to operate the StoffpoosterToastSop for every l block, and that it takes a lot of time to transfer files.

The present invention solves these conventional problems, and its main purpose is to logically copy files from the DKU to the MTU, i.e., to tape, so that the MTU's streaming function can be utilized to the fullest. The purpose of the present invention is to provide an input/output control method that can reduce the frequency of stopping the vehicle.

[Means for solving problems]

The present invention provides an input/output control method for logically copying files stored in a DKU to an MTU having a streaming function via an MMU in order to achieve a two-legged system. storage means for sequentially storing the stored files one block at a time in a buffer provided in the MMU; after a predetermined number of blocks are stored in the buffer of the MMU by the storage means, the position and size of the buffer are and table creation means for creating a plurality of mutually chained tables describing control information and other control information on the MMU, and receiving the tables created by the table creation means and mutually chained, and storing them in the buffer according to their contents. Transfer the written data to the MTU and write it.
A TC will be established.

[Effect]

The table created on the MMLI describes the location and size of the buffer in which multiple blocks of data acquired from the DKU are stored, and the MTC uses this as the MMLI.
[It is taken from J and reads data from the buffer and transfers it to MTU according to its contents, and MT
Since data corresponding to the number of blocks included in the table can be continuously output to U, the magnetic tape stoppage rate can be lowered. Also, from MTC to cPU! In normal case, I;IIlΔ will be executed once for each block error included in the table, and the CPU load will be light.
can be achieved.

〔Example〕

FIG. 1 is a block diagram of a main part of an embodiment of the present invention.
is a CPU that has MMUIO inside, 2 is MTC, 3 is MTU, and MTC2 is connected to CP IJ via Has6.
As shown in FIG. 2, which shows an example of the configuration of a system to which the present invention is applied, the bus 6 to which the MTU 3 is connected to the MTC 2 is connected to the DKC 4 via the DKC 4.
It is also connected to S.

The MTC2 in FIG. 1 includes an address register 101,
Data register 102. Bus control circuit 103. Microprocessor (hereinafter referred to as MPU) 104. First-in, first-out control buffer (hereinafter referred to as FIFO) 1
05゜Ill, I'? OM2O3,RA M2O3
, address counter 108° data buffer 109. It includes a data counter 110 and a control circuit +12.

Also, Figure 3 shows the DKU5-DKC4-CP when a file is logically copied from DKU5 to MTU3.
tJl-MTC2-MTU3 flowchart of data, commands, etc., Figure 4 shows Cr' U l -MTC2 at that time.
- A flowchart showing an example of processing between MTU 3, Figure 5 is a flowchart showing an example of processing within MTCZ, Figure 6 is a diagram showing an example of table contents, and Figure 7 is a control information area in the table. Figure 8 shows an example of the content of MTC2.
FIG. 9, which is a diagram showing a state in which table block information is stored in FOIII, is a conceptual diagram of a table chain developed on MMUIO. Below, MTU from DKU5
The operation of logically copying a file to 3 will be explained.

First, the CPUI sequentially transfers files to be copied from the DKLI5 to the MMtJIO. This is, for example, the third
As shown in the figure, the CPU 1 issues a read command to the DKC 4, and in response, the DKC 4 sends a seek command to the DKU 5 to perform a seek operation, and subsequently sends a read command to the DKU 5. DKI
J 1 block of data from 5 is converted to C by r) M△
This is performed by repeating the operation of transferring the data to MMt 10 of PIJ I.

When an appropriate number of blocks (n blocks in FIG. 3) are successively output from the DKU5 by the above operation, CPUt is set to MTU.
Generate the first table ([) to activate 3. In addition, during this table generation process, DK
Operations such as successive output of blocks from U5 are performed sequentially.

FIG. 6 is a diagram showing an example of the above table generated by cput, and shows the SPM dump area indicating the main memory address when transferring the contents of M107 to R in FIG. pointer.

The effective table length indicating the size of the table itself, the control information area indicating the control status of the table itself, the number of blocks included in the table, the offset value indicating the number to stop the operation from block l 5 Blocks that MTC2 is processing Current block number indicating the number, Next table address indicating the address of the next table to be referenced when processing of this table is finished, Table of the next table indicating the table length of the next table to be referenced when processing of this table is finished. length, and block 1 information ~ block n11
This indicates that the t1 report is included. In addition, block I
During the information+H to block n information, the buffer address, range, remaining range, and status indicate the starting address, number of data, remaining range at the end, and status at the end of the DMA transfer in that block, respectively. In addition, the control information area in the table is, for example, 16 as shown in FIG.
It has a binoto structure, and the table number is on the 0th to 7th bit,
VT(
The flag is “l” in the 9th bit.
When the TM (Termination) flag, which indicates that the table chain ends with this table, is "I" at the 10th bit, the CP (Completio
n) FE, R(
When the IError) flag is "1" in the 12th bit, an IT (Illegal Thale) flag indicating that the value set in this table is inappropriate is stored.

Note that if the size of the next table (2) is not determined when table (11) is generated, indirect chaining is performed using a dummy table, but this point will be described later.

Now, CPU I creates the first table f11 as shown above.
When the generation of VT is completed, the VT in the control information area of FIG.
Set the flag to "l", set the start address of table + 11 (XXX in Figure 9) to M7C3 as shown in the flowchart of Figure 4, and start MTC2. When the start address of (1) is received, the MPU 104 transfers table (1) to the CPU M
M [takes data from month 0 and stores it in RAM 107 (table read) 5゜Next, M P U 104 reads table (1
After confirming that the VT flag in 1 is “l”,
Write the block number rlJ to the number area of RAM 107, the current file in pull fi+, and the current block number area of table fil on MMUIO (
At this time, if an offset value is specified, the block number to be written will be the offset value).

Next, the MPU 104 reads the block information corresponding to the written block LJ 7 number from the RAM 107, and
As shown in the figure, it is stored in FIFO III and the control circuit 11
2 is given an instruction to start the transfer.

When the control circuit 112 is given an instruction to start transfer, the FI
The buffer address and range are taken out from FOIII, and the buffer address is set in the address counter 108 and the range is set in the data counter 110.

Next is the control circuit! 12 is a light command for MTU3)
′ is sent.

In response to this light controller F, the MTU 3 starts running the tape, and when it becomes ready to receive data, makes a data request to the control circuit 112.

When control circuit +12 receives this data request, MMtJ1
A path from 0 to data register 102 to data buffer 109 to control circuit +12 to MTU3 is created and data is transferred. At this time, the address counter 108 is incremented by 1 every l hide transfer, and the data counter 110 is incremented by 1. When the value of the data counter 110 becomes "0", the control circuit 1
12 generates an interrupt for the end of one block transfer to the MPU 104. If an error occurs even if the data counter ≠ 0, an interrupt is generated), and if there is no error, the FIFOI
The buffer address and range of the next block are retrieved from address counter 108.II. Set the data counter 110 and start transferring the next block (
If there is an error, do not proceed).

On the other hand, when the MPU 104 receives an interrupt indicating the completion of l block transfer, it receives the completion status from the control circuit 112 and writes it in the status area of the corresponding block in table (1) on MMtJlO. Also, if there is no error in the status of Ml'U 104, RAM 107 and M
The current block number of table t11 on MIJIO is incremented by +l (1!!L, if there is an error, do not perform this).

The control circuit +12 repeats the above operation until an error occurs or until all blocks have been transferred.

On the other hand, after writing one block, MTU3 writes IGR, which is the gap between blocks, so if it receives the next write command during this time, it will continue to write data without stopping the tape running. .

When the MPU 104 finishes processing all the programs in the RAM 107 table (11), it sets the CP flag in the control τI information area of the MMIJIO-hi table + 11. If an error occurs, it sets the CP flag or the ER flag. Set the IT flag), then run S to the CPUI.

And Ml) UI04 is a table in RAM107 +
Refer to the next table address and next table length in 11.
! Then, the next table (2) is retrieved from MMLJIO and stored in the RAM 107 (this is not done if an error occurs), and the same operation as above is repeated.

On the other hand, when the CPU receives an interrupt from the M7C3, it checks the 1Erl flag and cp flag in the control information area of table (1), and checks the Erl flag and cp flag in the control information area of table (1). When =O and CP=1, table +11 is updated (or deleted).

However, when ER=1, the current block number of table +11 is set to the offset value of table +11, the current block number 5 ER flag 5 IT flag is set to O, and the start address of table (1) is instructed to M7C3 and started. Retry processing is performed by applying .

In this case, it is possible to retry without configuring the table r+\. Also, CP 1. Jl can determine the processing status of the table by looking at the current block number area of the existing table, so if necessary, adjust the speed of file read from DK tJ 5 and write to MTU 3 for subsequent chained tables. This is possible by changing the size and number of tables.

Next, indirect chaining using a dummy table will be explained. If the table chain cannot be directly connected temporarily due to the sorting time of DKU5 or processing overhead of other SYSTEM devices, for example, as shown in Fig. 10, the effective table length, control information area, next table address, etc.
It is possible to chain tables as an indirect chain by taking a dummy table and chain with contents such as the table length of the next table. For example, C)) U
l is the "next table address" of table (1) and the table length of the primary table if you want to create table (11) and start up M7C3, but the size of table (2) is not determined. value cannot be set in the area of .In this case, the table address and table length of the dummy table shown in Fig.
The VT flag in the control information area of the dummy table is set to "O" and the M7C3 is activated. Then, when the size of table (2) is determined while the M7C3 is processing table (11), CPU t writes table (2) in the "next table address" and "table length of next table" areas of the dummy table. Write the table address and table length of V in the control information area.
Set the T flag to “l” and set the dummy table to F of M7C3.
Store in IFOI05.

FIFOI05 is used by the MPU when the dummy table is stored.
104, and the MPU
When an interrupt occurs, 104 sequentially outputs the 6th table address and table length of the 6th table from the FIFO 105, and stores the table in RAM 107 (11's ``next table address'' and ``table length of the next table''). Write to the area of .This will cause table (1) and table (
The chain 2) is taken, and in the same way, table (2) and table (3) and table (3) and table (4) are made into indirect chains using dummy tables, respectively, as shown in FIG. 12, for example. By this, M T U 3
It is possible to further prevent the streaming function from being used by only one person.

Note that if you know the size of the next table when creating one table, you can directly link it to the next table without using a dummy table, so the timing for starting M7C3 will be faster. If some delay is acceptable, as another embodiment of the present invention, for example, in FIG. 3, it is possible to adopt a method in which 1υ1 at the time of generating table fl+ is delayed until the time when table (2) can be generated. .

〔Effect of the invention〕

As explained above, the present invention allows the MTC to create a table that describes the location, size, etc. of the buffer in which multiple blocks of data acquired from the DK IJ are stored.
[The data is taken from IJ2, and according to its contents, data is read from the MMIJ buffer and transferred to M'FtJ, and data corresponding to the blocks included in the table are continuously transferred to MTU. 7.
It is possible to reduce the frequency of stopping the 11-ki tape, and it is also possible to
If υ1 is included in the table from C to the CPU, it will only be sent once for each program included in the table, and the load on the CPU will be reduced. Therefore, it is possible to logically copy files from the DKU to the MTU by making full use of the streaming function of the MTIJ and reducing the frequency with which tape running is stopped.

In addition, if you use indirect chaining using a dummy table with the table length of the next table, 7 dresses, and a control area, when the table is generated! υ1 can be accelerated, and it is also possible to prevent as much as possible from stopping the running of the magnetic tape due to the inability to generate the next table in time, and the streaming function of the MTU can be further utilized.

4.Additional explanation for page 121 Figure 1 is a block diagram of the main parts of an embodiment of the present invention, Figure 2 is a diagram showing an example of the configuration of a system to which the present invention is applied, Figure 3 is from DKU5 to MTIJ3 DKU5-DKU4-CPU1 when a logical copy of the file is performed
7. Data on MTC2-MTU3, poison orders, etc.
An explanatory diagram of the operation of the embodiment showing this, FIG. 4 is D +'<”+
Logical copy of file from u 5 to MTU3; i
FIG. 5 is a diagram showing an example of the processing performed between the CPUI-MTC2-MTU3 when the CPU is disconnected.
I! Figure 6 is a diagram showing an example of table contents.

Figure 7 is a diagram showing an example of the contents of the control information area during teni-pull, Figure 8 is a diagram showing a state in which table block information is stored in FIFO III of MTC2, and Figure 9 is a diagram showing an example of the contents of the control information area during ten pull.
A conceptual diagram of the table chain developed above, Figure 1O is an explanatory diagram of the contents of the dummy table, Figure 1+ is F
A diagram showing a state in which dummy table information is stored in IFOI05, FIG. 12 is an explanatory diagram of indirect chaining using a dummy table, and FIG. 13 is a diagram showing the flow of conventional processing. l is CPU, 2 is MTC23 is MTI), 4 is DK
(',, 5 is DKU, 101 is address register, +0
2 is a data register, 103 is a bus control circuit, +04 is a microprocessor, 105.111 is a FIFO 110
6 is a ROM, +07 is a RAM, 108 is an address counter, 109 is a data buffer, 110 is a data counter, and 112 is a control circuit.

Patent issued 19n person 11 Kidenki Co., Ltd. agent Buri R. Sakai! An example of the configuration of the data processing system is shown in Fig. 2. Fig. 2 shows an example of table contents. Riichi---------------
-------------'' 4 existing diagrams of table chain Figure 9 Diagram to explain the contents of dummy table Figure 10 Figure to explain the contents of FIFO 105 Figure 11 Figure 2 Explanation of indirect chain conversion using dummy table 12
figure

Claims (1)

[Claims] An input/output control method for logically copying files stored in a magnetic disk device to a magnetic tape device having a streaming function via a main storage device, comprising: storage means for sequentially storing one block at a time in a buffer provided in the main storage device; and after a predetermined number of blocks are stored in the buffer in the main storage device by the storage device, the location, size, and other information of the buffer are stored. table creation means for creating a plurality of mutually chained tables describing control information on the main storage; and table creation means for receiving the tables created by the table creation means and being chained together and storing them in the buffer according to their contents. An input/output control system comprising: a magnetic tape control device that transfers and writes data to the magnetic tape device.