JPS62112430A - Channel pulse generator - Google Patents

Abstract

PURPOSE:To miniaturize an entire generator by sending two signals of frame signal and channel clock from a common section and generating channel pulses of required number from both the signals at a channel section so as to miniaturize the connector of the common section. CONSTITUTION:In obtaining a transmission synchronizing signal, a frame signal TSphi commanding the start of one frame and a channel clock CHCLK commanding the start of each channel are given to counters 6A1-6A24 of channel sections 2A1-2A24 via signal lines 4, 5 respectively from a frame signal generating means 31 and a channel clock generating means 32 of the common section 3. The counters 6A1-6A24 have the same constitution and when the signal TSphi rises, they are initialized and becomes an initial value given via 5-bit signal lines 8A1-8A24. When a pulse of a channel clock CHCLK comes, the counters count up and when the count is, e.g., '25', the output is at an H level and when the count is other value, the output is an L level. The output of the counters 6A1-6A24 is given to a transmission synchronizing signal input terminal of the PCM CODECs 1A1-1A24 of each channel respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a channel pulse generator used in, for example, a PCM terminal station device.

[Technical Background of the Invention] In a PCM terminal device, a plurality of audio signals are digitized, multiplexed, and transmitted as data D having a frame structure as shown in FIG. That is, following the synchronization signal 5YNC, digitized 8-bit audio data is sequentially arranged for the number of channels (here, 24 channels). For this reason, when arranging an audio signal of 8 digits in each channel, or when separating an 8 digit audio signal from each channel, the arrangement or separation must be performed on the corresponding time slot. .

Therefore, in the PCM terminal equipment, as shown in FIG.
PCM codec (CODEC) 1 for each channel, transmission synchronization signal (TSYNC), transmission clock (TCLK)
, reception synchronization signal (R3YNC), reception clock (RCL)
K) is given. The PCM codec 1 starts arranging the audio signal at the rising edge of the transmission synchronization signal (TSYNC), and outputs the arranging of the audio signal for 8 bits of the transmission clock (TCLK). At this time, an analog 1 cog audio signal is input to the PCMLI-Deck 1 from the input terminal AIN, and a digital audio signal is output from the output terminal PCHOUT. Furthermore, when separating audio signals, the PCM codec 1 starts separating the audio signals in synchronization with the rise of the reception synchronization signal (R3YNC), and
Separate the 8-bit audio signal of K) 3. At this time,
A digital audio signal is input from the input terminal PCHIN of the PCM-]-deck 1, and an analog audio signal is output from the output terminal AOUT. , it is necessary to give two channel pulses, the transmit plane W1 signal (TSYNC) and the reception synchronization signal (R3YNC), to a one-channel PCM codec 1. Therefore, in Japanese-American PCM terminal equipment, the channel The number is 24 and it is a European PC.
Since the number of channels in the M terminal equipment is 30, it is necessary to apply 48.60 channel pulses to each channel.

In the conventional PCM terminal equipment, all the channel pulse generation parts are provided in a common part, and a PCMII = "i" rack is provided in the fame channel board for each channel.
Channel pulses were sent from the common section to each high-pitched channel A/channel using a -1 connector cable.

[Problems with the Background Art] For this reason, in the conventional PCM terminal equipment, the number of pins of the connector in the common part is extremely large, such as 48 or 60, and the connector becomes large. Along with this, there is a problem in that miniaturization of the PCM terminal equipment is hindered.

[Object of the invention] 7! The invention was made to solve the above problems, and its purpose was to create a channel pulse generator that could miniaturize the connector of the common part and miniaturize the overall device. It is to acquire and provide equipment.

[Summary of the Invention] Accordingly, in the present invention, the common section sends out two signals: a frame signal that instructs the start of one frame, and a channel clock that instructs the start of each channel.
The above object is achieved by forming grooves in the channel section so as to generate a necessary number of channel pulses from the L frame signals and the channel clock.

[Embodiment of the Invention] FIG. 1 is a block diagram showing the main parts of a PCM terminal equipment employing an embodiment of the present invention. This PCM terminal equipment 100
is a Japanese and American series, and has a data structure of 24 channels and 1 frame. In this embodiment, only the configuration for obtaining a transmission synchronization signal is shown. In the figure, 3 indicates a common section, and the common section 3 is provided with a frame signal generating means (pulse output circuit) 31 and a channel clock generating means (pulse output circuit) 32. The frame signal generating means 31 outputs a frame signal TSφ (a signal having a pulse at the start of one frame) instructing the start of one frame. The channel clock generating means 32 generates a channel clock CIICL (
A signal with a pulse for every 8 bits) is output. These frame signal TSφ and channel clock CIICL
The relationship between K and multiplexed data D is as shown in FIG. Frame signal TSφ and channel clock CHCL
K refers to the channel section 2A1 to 2A1 through the signal line 4゜5.
2A24 is given to counters 6A1 to 6A24. The counters 6A1 to 6A24 have the same configuration and are initialized when the frame signal TSφ rises, and the counters 6A1 to 6A24 are initialized when the frame signal TSφ rises.
7 to 1 to 8 The initial value given through A24 is then counted up when the channel clock C) ICLK pulse arrives, and the count value becomes "'".
25'', the output is set to H level, and when the count value is any other value, the output is set to L level. Counters 6A1 to 6△
The outputs of 24 are given to transmission synchronization signal input terminals of PCM codecs IA1 to 1A24 of each channel via signal lines 7A1 to 7A24, respectively.

Note that the initial value of 5 bits is given from a control section (not shown), but it is given from each of the channel sections 2A1 to 2A24. The initial value given to each counter 6A1 to 6A24 is 24 (1100
0), counter 6A2 has 23 (10111),...
・, (omitted), ..., the counter 6A24 has 1 (0
0001) is given.

The operation of the channel pulse generator configured as above will be explained. When the frame signal generating means 31 of the common section 3 outputs a pulse of the frame signal MTSφ, the counters 6A1 to 6A24 are initialized to set their count values to 24 to 1, respectively. Next, when the first pulse of the channel clock CHCLK is output, the counters 6A1 to 6A
24 callan 1-1 shift is 25-2 roar. Therefore, the output of counter 6A1 becomes H level, and the output of counter 6A2~
The output of 6A24 remains at L level. Next, by the output of the second pulse of the channel clock CHCLK, the count 1 of the counters 6A1 to 6A24 becomes 26 to 3.
becomes.

As a result, the output of counter 6A2 becomes H level, and the outputs of counters 6A1.6A3 to 6A24 become L level. As a result, the counter 6A outputs a channel pulse (transmission synchronization signal) that is at H level in the section corresponding to the first 8 bits of data of one frame. Thereafter, each time a pulse of the channel clock CHCLH arrives, a channel pulse is sequentially outputted from the counters 6A2 to 6A24.

Each of the PCM codecs 1A1 to 1A24 arranges audio data based on the incoming channel pulse. In this figure, only the transmission system is shown, so in reality, the common section 3 is provided with frame signal generation means and channel clock generation means for the reception system, and each channel section 2A1 to 2A24 is provided with frame signal generation means and channel clock generation means for the reception system. The reception synchronization signal (R3
YNC) generation counter is provided. The initial value given to this counter is the signal line 8A1-8
The counters 6A1 to 6A are given through A24.
24.

As described above, according to this embodiment, the common section 3 only outputs two frame signals and a channel clock through four signal lines for channel pulse generation, whereas the conventional unit 3 outputs only two frame signals and a channel clock for channel pulse generation. Compared to the original, the number of signal lines is greatly reduced, and therefore the number of connector pins is also reduced. Therefore, the connector of the common part 3 can be downsized, and the common part 3 itself can be downsized. In addition, the four signal lines and five (5-bit) signal lines 8A1 to 8A24 for initial value setting are connected to the channel sections 2A1 to 2A24, respectively, whereas the conventional system has four signal lines. There is no need to increase the number of connector pins that much compared to . In other words, the common part 3, which has changed from 48 pins to 4 pins, can be made smaller, and the channel parts 2A1 to 2Δ24, which have changed from 4 pins to 9 pins, are hardly enlarged, so the PCM terminal equipment can be made smaller as a whole. become.

FIG. 2 shows a block diagram of main parts of another embodiment of the present invention. In this embodiment, the channel units 21 to 23 each output channel pulses for eight channels, which is different from the embodiment shown in FIG. 1, which outputs channel pulses for each channel.

The counters 41 to 43 of the channel sections 21 to 23 have the same functions as the counters 6A1 to 6A24 in FIG. 1. and,
The initial values given to the counters 41 to 43 are 2A (11000) for the counter 41 and 2A (11000) for the counter 41, respectively.
1B (10000) for 2 and 8 (01000) for counter 43. 8-bit shift registers 51-53 are connected to the counters 41-43, respectively. Shift registers 51 to 53 transfer input signals to output terminal 0 in synchronization with the pulse of channel clock CHCLK.
Shift to 0-07 and output.

In the channel clock generator having such a configuration, the counters 41 to 43 control the channel by the first and second, ninth and tenth, and seventeenth and eighteenth pulses of the channel clock CHCL. A pulse is generated, which is shifted from register 1 to register 51.
-07 to PCM codec 1 to output terminal 00 of ~53
The signals are sequentially output to A1 to A24. Even in this embodiment, the number of signals output from the common section 3 is four considering transmission and reception, so the connector can be made smaller. In the channel sections 21 to 23, the number of output terminals is 8x2=16, and the miniaturization of the common section 3 (from 48 pins to 4 pins) leads to miniaturization of the device. In addition, the number of channel parts is 4.
It may be more than that.

In the above embodiment, the number of channels is 24 for Japanese and American channels, but the present invention can be implemented even if the number of channels is 30 for European channels. That is, by appropriately changing the number of counters and initial values, it is possible to support any number of channels.

[Advantageous Effects of the Invention 1] As explained above, according to the present invention, the common part connector can be downsized, and thereby the entire device can be downsized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main part of the PCM station device adopted in Embodiment 4 of the present invention, Fig. 2 is a block diagram of the main part of the third embodiment of the present invention, and Fig. 3 is a block diagram of the main part of the adopted PCM station device. FIG. 4 is a diagram showing the relationship between the γ-data, the frame signal, and the channel clock, and is a diagram for explaining the operation of the PCM codec. 1.1A1~1A24...PCM codec 2A1~
2A24.21-23...Channel section 3...Common section 4.5.7A1-7A24.8A1-8A24...Signal lines 6A1-6A24.41.43...Counter 31...
・Frame signal generation means 32...Channel clock generation means 51-53...Shift register agent Patent attorney Book 1) Takashi Figure 1 Figure 2

Claims (3)

[Claims] (1) A frame signal generation means that generates a frame signal that instructs the start of one frame including a plurality of channels, and a channel clock generation means that generates a channel clock that instructs the start of each channel of the one frame. a common part; and a channel part comprising a channel pulse generating means for generating a channel pulse having a pulse width corresponding to each channel section of the plurality of channels based on the frame signal and the channel clock applied from the common part. Channel pulse generator consisting of. (2) The channel pulse generating means is initialized by the frame signal, counted up by the channel clock,
The channel pulse generator according to claim 1, characterized in that the device comprises a number of counters corresponding to the number of channels that output channel pulses when a preset count value is reached. (3) The channel pulse generation means includes a counter that is initialized by a frame signal and outputs a channel pulse at a predetermined channel clock that arrives after that, and a counter that shifts the channel pulse output by this counter in synchronization with the channel clock. A channel pulse generator according to claim 1, characterized in that the channel pulse generator comprises a shift register that outputs a pulse signal.