JPS62101137A - Scramble circuit - Google Patents

Abstract

PURPOSE:To keep normally the sequence of scramble while taking the self synchronization by detecting the specific state of a shift register string in a PN series generator and presetting the PN series generator periodically. CONSTITUTION:The 1st gate circuit 7 detects the specific state of a shift register string in a PN series generator 1, the output of the 1st gate circuit 7 and a frame synchronizing signal 2 inputted externally are ORed and a function presetting the PN series generator 1 applies the 2nd gate circuit 6. In setting the interval between the specific between the specific state of the shift register in the PN series generator 1 to be detected by the 1st gate circuit 7 and the preset state equally to the frame period, even when the external input to a frame synchronizing signal 2 is intermitted due to any fault, the self- synchronization of the PN series generator 1 is taken and the PN series generator 1 is not run away. In an exclusive OR gate 3, the digital signal 4 inputted externally and the PN series are subjected to an exclusive OR and the scramble is executed in a correct sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scrambling circuit in, for example, a PCM communication system.

[Conventional technology]

For example, in a PCM communication system, by performing an exclusive OR operation between the baseband signal and the PN sequence,
There are cases where the frequency spectrum of a baseband signal is spread over a wide range of frequencies. This is a technique called scrambling, and it is possible to decode the original baseband signal by performing the exclusive OR operation again using the same PN sequence used during scrambling. This is a technique called descrambling. The PN sequence required for this scrambling and descrambling can be generated by applying the concept of coding theory.

An example of generating a PN sequence using X+X+1e as a primitive polynomial is shown in FIG. 2(A). In this case, the initial values of shift registers (1) (2) +31 +41 are set to a0. a
l, a2゜a3. Figure 2 (1B) shows the state transition diagram for the case of and Lfc.
A state pattern diagram for this case is shown in FIG. 2 (0). In other words, when generating a period N=2-1 0PN sequence,
An arbitrary primitive polynomial of order t is selected, and shift registers are connected using exclusive OR gates so as to satisfy the primitive polynomial. If this shift register is clocked at f (Hz), a predetermined PN sequence can be obtained in series at f (bps) as the final stage soft register output. For the sake of simplicity, Figure 2 (A) is shown.

Clock lines and preset lines are not written.

In the above example, there were four polynomials, that is, four shift registers, but in reality polynomials of more than ten degrees are often used.

FIG. 3 is a block diagram for mE'Af of a conventional scrambling circuit using a PN sequence generated according to the above principle. In the figure, frame synchronization is achieved by presetting a PN sequence generator (1) by a frame synchronization signal (2) input from the outside. Further, in the exclusive OR gate (3), an exclusive OR operation is performed between the externally input digital signal (4) and the PN sequence signal output from the pN sequence generator,
Scrambling is performed and a scramble signal (5) is output.

[Problem that the invention seeks to solve]

In FIG. 3, there is a problem in that when the input of a frame synchronization signal from the outside is interrupted due to some kind of failure, frame synchronization is not achieved and the PN sequence generator runs out of control.

This invention was made to solve this problem, and even when the input of the frame synchronization signal from the outside is interrupted, the PN sequence generator self-synchronizes.
The purpose is to keep the scramble sequence normal.

[Failure to solve the problem]

The scrambling circuit according to the present invention detects a specific state of a shift register array in the PN sequence generator, performs an OR operation between the detection signal and a frame synchronization signal input from the outside, and This is used as a signal to preset periodically.

[Effect]

In this invention, even if input of a frame synchronization signal from the outside is interrupted, a specific state of a shift register array in the PN sequence generator is detected and the PN sequence generator is periodically preset. Since self-synchronization is achieved, it is possible to maintain a normal scrambling sequence.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

I) The first gate circuit (7) detects the specific state of the shift register array in the N-sequence generator (1), and compares the output of the first gate circuit (7) with the frame input from the outside. The function of performing the n* logical sum operation with the signal (2) and presetting the above I) N sequence generator (11) is performed by the second gate circuit (
61. If the interval between the specific state and preset state of the shift register in the PN sequence generator (11) to be detected in the first gate circuit (71) is set equal to the frame period, the frame synchronization signal (2) may Even if the external input is interrupted, the PN sequence generator +11 is self-synchronized and the PN sequence generator (1
) will not run out of control. In the exclusive OR gate (3),
An exclusive OR operation is performed between the digital signal (4) inputted from the outside and the above PN series.

Scrambling is performed in the normal LI/-1 sequence.

〔Effect of the invention〕

As explained above, this invention uses an external frame synchronization signal (
Even if the input of 2) is interrupted, the scramble sequence is maintained normally.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Fig. 2 is a block diagram for explaining the principle of PN sequence generation, and Fig. 3 is a block diagram for explaining the conventional technology, where (l) is a PN sequence generator, and (2) is a frame synchronization signal. , (31 is an exclusive OR game), (41 is a digital signal, (5) is a scramble signal, (61 is a second gate circuit, and (7) is a first gate circuit. The same symbols indicate the same or corresponding parts.

Claims (1)

[Claims] a PN sequence generator that generates a PN pattern; a first system that detects a specific state of a shift register array in the PN sequence generator;
The gate circuit performs an OR operation between the frame synchronization signal inputted from the outside and the output of the first gate circuit, and calculates the above PN.
A second gate circuit that presets the sequence generator, and an exclusive OR gate that performs an exclusive OR operation between a digital signal input from the outside and a PN sequence signal output from the PN sequence generator. A scramble circuit characterized by: