JPH04317229A - Scrambling system - Google Patents

Abstract

PURPOSE:To reduce the number of shift registers in a parallel pseudo-random signal generation circuit, to reduce the circuit scale and power consumption and to flexibly cope with a paralleled number. CONSTITUTION:'n' kinds of combination exclusive OR circuit group 12 which is preliminarily designated corresponding to the paralleled number 'n' so that it can be identical to a prescribed generation polynomial, outputs respective operation results. A selector circuit selects the output of one combination exclusive OR circuit 12 corresponding to the paralleled number 'n'. By performing the feedback input of the output of the selected one combination exclusive OR circuit 12 to 'n' parallel shift registers which can be commonly used without depending on the paralleled number, the pattern series of an 'n' parallel pseudo- random signal 10 can be generated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scrambling method in PCM transmission, and more particularly to a scrambling method in which low-speed signals before time division multiplexing are scrambled and then multiplexed.

0002

2. Description of the Related Art FIG. 4 shows the basic configuration of a conventional parallel scrambling system (Japanese Patent Publication No. 1998-198843). In FIG. 4, 1 is a multiplexing circuit, 2
1, 22, . . . 2n are EX-OR gates, and 3 is a pseudorandom signal generation circuit, which is composed of n pseudorandom signal generation circuits 41, 42, . . . 4n having the same configuration. FIG. 5 shows the configuration of a conventional parallel pseudo-random signal generation circuit 3 (generating polynomial X7 +X3 +1). FIG. 6 is a configuration diagram when a conventional scrambling function is performed on a high-speed signal of multiplexed output. FIG. 7 shows a serial pseudo-random signal generation circuit for use in FIG. FIG. 8 is an operation explanatory diagram comparing the operation of the serial pseudo-random signal generation circuit in FIG. 7 and the operation of the parallel pseudo-random signal generation circuit in FIG. 5.

Next, the operation will be explained. Now, in FIG. 4, parallel low-speed signals CH1 and CH2 when the number of multiplexing n=3
, Pseudo-random signals P1, P2, P3 corresponding to CH3
can be equivalently taken every 3 bits from the serial pseudo-random signal P when applying the scrambling function to the high-speed signal after multiplexing in FIG.
1, 42, and 43 have a 3-bit shift configuration. The pseudo-random signal generation circuits 41, 42, and 43 use initial values that are sequentially shifted one bit at a time, for example, (1
111111), (1111110), (111110
0) are loaded respectively.

In the pseudo-random signal generation circuit 41, the first 1-bit signal A is output, then the value D shifted by 3 bits is output, and thereafter G, J, . . . are output in order. The output pseudo-random signal P1 is A, D, G,
It becomes J... The pseudo-random signal generation circuit 42 similarly has a 3-bit shift configuration, but the initial value is one bit shifted from the initial value of the pseudo-random signal generation circuit 41, so the output pseudo-random signal is the same as the pseudo-random signal generated. The circuit 41 is shifted by 1 bit, and the output pseudo-random signal P2 is B, E, H,...
・It becomes.

Similarly, the pseudo-random signal generation circuit 43 shifts the output pseudo-random signal P2 of the pseudo-random signal generation circuit 42 by 1 bit, and the output pseudo-random signal P3 becomes C, F, I, . . . .

EX-OR gates 21, 22, 23
, three parallel low-speed signals CH1, CH2, CH3
and pseudo-random signals P1, P2, and P3, and outputs the operation results EX1, EX2, and EX3. The multiplexing circuit 1 multiplexes EX1, EX2, and EX3,
A high-speed signal SD1 shown in data string g in FIG. 8 is output. The multiplexed output SD1 after this parallel scrambling is b in FIG.
As shown in FIG. 6, the result is the same as that obtained by performing scrambling after multiplexing using the configuration shown in FIG.

[0007]

[Problem to be Solved by the Invention] Since the conventional scrambling method operates as described above, when the degree of the scrambling generating polynomial is k and the number of multiplexing is n, a parallel pseudo-random signal generation circuit is required. The maximum number of shift registers is n×k, and when the number of multiplexed signals increases when high-speed signals are expanded in parallel and processed at low speeds, there is a problem that the circuit becomes large-scale and power consumption also increases. This invention is
The present invention was developed with the aim of solving such problems, and aims to realize a parallel scrambling system that can generate parallel pseudo-random signals corresponding to an arbitrary number of parallels n and that has a small circuit scale.

[0008]

[Means for Solving the Problems] The scrambling method according to the present invention includes n parallel registers for generating n parallel pseudo-random signals from a predetermined serial pseudo-random signal when scrambling into a high-speed signal; A group of n types of combinational exclusive OR circuits that can determine feedback inputs to n parallel registers corresponding to the number of parallelizations n, and one combinational exclusive OR circuit depending on the number of parallelizations n. This is realized by adopting a configuration equipped with a selector circuit that selects the output of.

[0009]

[Operation] In the scrambling method of the present invention, n types of combinatorial exclusive OR circuit groups predetermined corresponding to the number of parallelizations n output their respective operation results so that they are the same as a predetermined generating polynomial. do. The selector circuit selects the output of one combinational exclusive OR circuit from the n types according to the number n of parallelizations. A pattern sequence of n parallel pseudo-random signals is generated by feeding back the output of one selected combinational exclusive OR circuit to n parallel registers that can be used in common regardless of the number of parallels. Since the number of shift registers in the n-parallel pseudo-random signal generation circuit can be minimized, the circuit scale can be reduced and power consumption can be reduced.

0010

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. 1, 21, . . . 2n are the same as in the conventional example. 1
0 is a parallel pseudo-random signal generation circuit, 11 is a parallel register, and 12 is a group of combinational exclusive OR circuits. FIG. 2 shows the configuration of a parallel pseudo-random signal generation circuit according to an embodiment of the present invention. 141 is the combinatorial exclusive OR circuit 1 when n=1, 142 is the combinatorial exclusive OR circuit 2 when n=2, ..., 14n is the combinatorial exclusive OR circuit when n=n The OR circuit n, 15 is a selector. FIG. 3 shows the configuration of the combinational exclusive OR circuit 3 when the number of parallelizations is n=3.

Next, the operation will be explained. In FIG. 1, consider the generator polynomial X7 +X3 +1 and the number of parallelizations n=3. Since the pattern sequence obtained by extracting every 3 bits from the pattern sequence of the serial pseudo-random signal is a shifted sequence of the pattern sequence of the original serial pseudo-random signal, this can be expressed as a generator polynomial as follows: 1=X3
(1)
X=X4
(2)
X2=X5
(3)
X3=X6
(4)
X4=1+X
(5)
X5=X+X2
(6)
X6=X2+X3
(7) becomes. formula(
In 1), the input of shift register SR1 means inputting the output of shift register SR3. Formula (2) ~
The same applies to equation (4). Equation (5) means that the result of exclusive OR of the output of shift register SR1 and the output of shift register SR2 is input to shift register SR5. The same applies to equations (6) to (7).

[0012] Now, seven registers SR1, ..., SR
Initial value load signal 1 is loaded into 7. The operation of the combinational exclusive OR circuit 3 corresponding to the number of parallelizations shown in FIG. 3 will be explained. The combinational exclusive OR circuit 3 is one of the combinational exclusive OR circuits 12 . S
The output data f4 of R4 is set as the input data of SR1, and SR
5's output data f5 is set as the input data of SR2, and SR6
The output data f6 of is set as the input data of SR3, the output data f7 of SR7 is set as the input data of SR4, and f1 and f2
Let the exclusive OR result of f2 and f3 be the input data of SR5, and let the exclusive OR result of f2 and f3 be the input data of SR5.
The exclusive OR result of 3 and f4 is input data to SR7. As a result, the outputs f1, f2, and f3 of each register SR1, SR2, and SR3 become three parallel pseudo-random signals. Similarly, a combinational exclusive OR circuit 1141, a combinational exclusive OR circuit 1142, corresponding to the number of parallelizations,
. . . , n types of combinational exclusive OR circuit groups are constructed from the combinational exclusive OR circuit n14n. The selector circuit 15 selects the output of the desired combinational exclusive OR circuit by the multiplexing number switching signal, and feeds it into the n parallel registers 11 that can be used in common regardless of the number of parallelizations. By doing this, a pattern sequence of n parallel pseudo-random signals can be generated.

[0013]

[Effects of the Invention] Since the present invention is configured as explained above, it can be universally adapted to any number of parallel multiplexing.
Moreover, the number of registers required for the parallel pseudo-random signal generation circuit is n at most, which has the effect of making the circuit scale extremely small and reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a scrambling method showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a parallel pseudo-random signal generation circuit according to the first embodiment.

FIG. 3 is a configuration diagram of a combinational exclusive OR circuit when n=3 in the first embodiment.

FIG. 4 is a configuration diagram of a conventional parallel scrambling method.

FIG. 5 is a configuration diagram of a conventional parallel pseudo-random signal generation circuit.

FIG. 6 is a configuration diagram when a conventional scrambling function is performed on a high-speed signal of multiplexed output.

FIG. 7 shows a serial pseudo-random signal generation circuit for use in FIG. 5;

8 is an operation explanatory diagram comparing the operation of the serial pseudo-random signal generation circuit in FIG. 6 and the operation of the parallel pseudo-random signal generation circuit in FIG. 5;

[Explanation of symbols]

1 Multiplexing circuit 21 ,, 2n EX-OR gate 3 Pseudo-random signal generation circuit 10 Parallel pseudo-random signal generation circuit 11 Parallel register 12 Combination exclusive OR circuit 15 Selector

Claims (1)

[Claims] Claim 1: In a multiplexing method that time-division multiplexes n parallel low-speed signals and converts them into high-speed signals, an exclusive OR operation for performing an exclusive OR operation of n parallel low-speed signals and n parallel pseudo-random signals. a multiplexing circuit that multiplexes the output of the exclusive OR circuit and converts it into a high-speed signal; n parallel registers for generating the n parallel pseudo-random signals; n types of combinatorial exclusive OR circuits that take the output as an input, perform a combinatorial exclusive OR operation selected by a multiplexing number switching signal based on the input, and return the operation result to the parallel register. A scrambling method characterized in that it can be universally adapted to any number of parallel multiplexing systems.