JPS6190543A - Error correction system - Google Patents

Abstract

PURPOSE:To decrease the transmission delay time and memory capacity by providing an interleaving circuit converting periodically the arrangement of a data signal within the same period as an error correction circuit in a data terminator by a 2-wire time division direction control system. CONSTITUTION:A buffer circuit 14 of a transmission section transfers memory content to the interleaving circuit 15 when a bit number corresponding to a burst length is stored. In this case, adjacent bits in the circuit 15 are stored in a location apart by n bits. Each bit in the circuit 15 is transmitted from a terminal 17. The inputted burst signal waveform at the reception side is stored in a buffer circuit 22 according to a reception burst timing signal. After the end of reception of one burst, the content of the circuit 22 is subjected to deinterleaving by a deinterleaving circuit 24. The circuit 24 outputs the interleaved signal to an error correction circuit 25 and a syndrome generating circuit 26 in the unit of code blocks. When the circuit 26 detects an error, it generates an address signal of the erroneous time slot. The circuit 25 uses this signal for error correction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction system for a data line termination device using a two-wire time-division direction control system.

[Prior art]

Possible causes of deterioration in data lines using metallic cables include impulsive noise, crosstalk noise, occasional interruptions, and induced noise. Among these, there are occasional interruptions and induced noises,
It occurs less frequently than other factors, and induced noise is regionally localized. As for crosstalk noise, it is possible to suppress the noise due to cable accommodation limitations, and even if there is occasional disconnection, the frequency of occurrence of crosstalk noise is reduced by superimposing direct current on the line.

In addition, for burst errors caused by impulsive noise, B
By combining the CH code and interleaving, burst errors can be corrected by suppressing/dumbing them, so they can be significantly reduced (for example.

Nikkei Electronics Magazine: ``Error Correction Code J'', which has begun to be actively used in a wide range of fields, 1975.12.15. p.
p37-65). Furthermore, this error correction method is used in the well-known two-wire time-division direction control method (IEICE Communication System Study Group Materials, Kokan, Benjo, Nishizawa [Study on the method of configuring an all-digital telephone subscriber system J, 1978 AC3) -78-,20
) has the disadvantage of increased transmission delay.

This will be explained below.

An example of the configuration of a transmitting/receiving section of a two-wire time-division direction control system incorporating an error correction system is shown in FIGS. 1 and 2. FIG. 1 shows an example of the configuration of the transmitter, and FIG. 2 shows an example of the configuration of the receiver.

In Figures 1 and 2, 11.21 is an input terminal, 12
．． 27 is a speed conversion circuit, 14 and 22 are buffer circuits, 1
3 is a check bit generation circuit, 15 is an interleave circuit, 2
3 is a reception timing generation circuit, 24 is a dinkeep circuit, 25 is an error correction circuit, 26 is a syndrome generation circuit, and 17.28 is an output terminal. Check bit generation circuit 1
3. Error correction circuit 25. The syndrome generation circuit 26 is.

For example, a known circuit used in BCH codes etc. can be used.

Figure 3 shows the operating waveforms of each part of the transmitter when using the conventional increment/dift-leave method.

FIG. 4 shows the operating waveforms of each part of the receiving section. however.

3 shows operating waveforms when the deinterleaf circuit 24 is configured with a shift register.

In FIGS. 3 and 4, (a) is the input waveform of the information bit input to the input terminal 11, and (b) is the input waveform of the information bit input to the input terminal 11.
(C) is the output waveform of the check bit generation circuit 13, and (d) is the output waveform of the speed conversion circuit 12.

The contents of the shift register constituting the buffer circuit 14 at the time when Dn,1 is output, (e) the contents of the shift register constituting the interleave circuit 15 at the same time, (
f) is the output waveform sent out as a burst signal from the output terminal 17, (g) is the burst signal waveform manually input to the input terminal 21, (h) is the output waveform of the reception timing generation circuit 23, (i) is T, , P and P circuit 2 at the time of m input
2, (j) is the content of the shift register that constitutes the Dink Leap circuit 24 at the same time, (k) is the output waveform of the syndrome generation circuit 26,
(t) is the output waveform of the error correction circuit 25, and (2) is the output waveform of the speed conversion circuit 27.

An error correction code is a (p, t) block code (for example, BC
H code) is assumed. In addition, the burst of 2-wire time-division direction control method is n-code pro.

It shall consist of nxp bits.

The signal speed f input to the input terminal 11. information bit (
a) is divided into t bits, and the speed conversion circuit 12 converts the signal speed to the signal speed f on the transmission path, resulting in the signal (b).
). The check bit generation circuit 13 is.

- They are sequentially stored in the buffer circuit 14, which is composed of a shift register having an input/output terminal of OUT. 8777 circuit 1
Buffer circuit 1 at the time when information ping) D is input to 4.
The contents of 4 are as shown in (d). At this point parallel
The memory contents are transferred to an interleaving circuit 15 consisting of a /ftrestor having in/serial-out input/output terminals. however.

It is assumed that the output terminal of the buffer circuit 14 and the input terminal of the interleaving circuit 15 are appropriately connected according to the interleaving method. In this example, the unit delay amount p bits,
The number of stages is p. At this time, the interleave circuit 15 has 2
Since nXp bits of information corresponding to the burst length of the line time division direction control system are stored, the information is sequentially output from the output terminal 17 to the transmission line.

On the reception side, the burst signal waveform (g) input to the input terminal 21 is input to the buffer circuit 22 in accordance with the reception burst timing signal (h) generated by the reception timing generation circuit 23 and is stored. The buffer circuit 22 is composed of a shift register having serial-in/IP parallel-out input/output terminals.

(2) The contents of the buffer circuit 22 after receiving the burst are as shown in (i). The buffer circuit 22 also stores the contents of the burst that preceded the received burst for demetaleaving. A portion of the contents of the buffer circuit 22 is transferred to a dink creep circuit 24 which is constituted by a shift register having serial-in/serial-out input/output terminals. The dinkeep circuit 24 encodes the stored contents.

The output signal is sequentially outputted to the error correction circuit 25 and the non-drome generation circuit 26 in units of frames. When the syndrome generating circuit 26 detects an error 9 occurring on the transmission path, it generates an address signal [present] for the time slot where the error occurred.

The error correction circuit 25 performs error correction based on the address signal (k), and outputs an output signal (t) to the speed conversion circuit 27. The speed conversion circuit 27 is.

The input t bit 11' is the information bit at the 1st position and is converted to the original signal speed f from the signal speed fb on the transmission line. Convert the speed to .

The reproduced signal @) is output to the output terminal 28.

[Problem 3 to be Solved by the Invention As described above, interleaving with an error correction code is possible. However, in the two-wire time-division direction control method, continuous information is transmitted in bursts with speed conversion, so one code block is transmitted in multiple bursts due to interleaving.
The extension time will increase.

For example, in the conventional example shown in FIGS. 3 and 4, on the transmitting side (2
The time (maximum waiting time) from the time when the first information bit constituting the -p)th code block is manually transmitted until the burst containing the last bit in the code block starts to be transmitted to the line is given by the following formula: Become.

On the receiving side, after starting to receive the above burst signal, (2-p
) The time required to start speed conversion of the information bits in the code block is given by the following equation.

Therefore, the total transmission delay time τ is given by the following equation.

τ=τ8+τ8+α Here, α is the delay time on the line.

For example, the signal speed f. is 64 kb/a + signal speed fb on the transmission line is 200 kb/s, burst period is 2
．． +' (12,
s) When applying the BCH code, p=12, 1
=8 and n=20, the total transmission delay time τ is (5,2 ms+α) according to equation 2 (3), which is more than twice the burst period.

Furthermore, the memory capacity required by the buffer circuit 14 on the transmitting side and the buffer circuit 22 on the receiving side is (n+p-3).
Xp+2, (n$p-1)Xp (in the above example, each is 350 bits) and 372 bits, which requires a capacity approximately 1.5 times the burst length of 240 bits.

The present invention makes it possible to correct random errors and burst errors of a certain length or less in a data line termination device using a two-wire time-division direction control method, and allows the increase in transmission speed due to the introduction of the error correction method to be maximized while reducing the circuit configuration. Simplified. The object of the present invention is to provide an error correction method.

[Means for solving the problem] According to the present invention, in a data termination device using a two-wire time-division direction control method, data is transmitted within the same cycle by an error correction circuit and the time-division direction control method. An error correction system is obtained that includes an interleave circuit that periodically converts the arrangement of signals.

[Embodiments of the invention]

FIG. 5 shows operating waveforms of the transmitting section of the embodiment according to the present invention, and FIG. 6 shows operating waveforms of the receiving section.

In Figures 5 and 6, (n) is the input terminal 1 in Figure 1.
1, (O) is the output waveform of the speed conversion circuit 12, (p) is the check bit generation circuit 13.
(q) is the content of the shift register forming the buffer n, m path 14 at the time when the check bit T is output from the check bit generation circuit 13, (r) is the interleaving circuit at the same time (S) is the output waveform sent out as a burst signal from the output terminal 17, (t) is the burst signal waveform input to the input terminal 21, (U) is the reception timing. The output waveform of the generation circuit 23, l is the content of the shift register constituting the buffer circuit 22 at the time of Tn rm input, s (W) is the content of the shift register constituting the demetaleve circuit 24 at the same time, and (X) is the syndrome. The output waveform of the generation circuit 26, (y) the output waveform of the error correction circuit 25, and (2) the output waveform of the speed conversion circuit 27. In FIGS. 5 and 6, the same (p, A) block code as in the conventional example is used as the error correction code, and the burst length is also pXn bits, the same as in the conventional example.

Information on the signal speed f input to the input terminal 11) (
A) is divided into units of t bits, and is converted by the speed conversion circuit 12 to a signal speed f5 on the transmission path to become a signal (,). The check bit generation circuit 13 generates the signal (,) and check bit 0). Signals (o) and (p) are time-division multiplexed and sequentially stored in buffer circuit 14.

When the number of bits corresponding to the burst length is accumulated in the buffer circuit 14, the buffer circuit 14 switches to the interleave circuit 1.
Transfer the memory contents to 5. The output terminal of the buffer circuit 14 and the input terminal of the interleave circuit 15 are connected to connect signal waveforms (q) and (r) in FIG. d
1+j is expressed by the contents of the buffer circuit 14 using a quadratic equation.

Therefore, within the interleaving circuit, adjacent bits are n
Stored bits apart. Each bit in the interleaving circuit is sequentially sent out to the transmission line via the output terminal 17.

On the receiving side, the signal is input to the input terminal 21, is input to the buffer circuit 22, and is stored. The contents of the buffer circuit 22 after one burst reception is completed are as shown in (,). After receiving one burst, the contents of the buffer circuit 22 are
The data is transferred to the leave circuit 24, where it is demetaleaved. The demetaleaving circuit 24 sequentially sends the demetaleaved signal in code block units to the error correction circuit 2.
5 and the syndrome generating circuit 26. When the syndrome generation circuit 26 detects an error occurring on the transmission path, it generates an address signal (X) for the time slot where the error occurred. The error correction circuit 25 performs error correction based on the address signal ←), and outputs an output signal 0) to the speed conversion circuit 27. The speed conversion circuit 27 is.

[Effects of the Invention] As explained above, each bit of burst error of n bits or less in a transmission path is selected to be separated by n bits, unlike the conventional example. The error correction capability can be the same or higher.

The transmission delay time τ' in this embodiment is given by the following equation.

Furthermore, the memory capacity required by the buffer circuit 14 on the transmitting side and the buffer circuit 22 on the receiving side is n x p
becomes. When calculating the total transmission delay time and buffer memory capacity under the same conditions as the conventional example, each (3.9ms + α)
, 240 bits, the transmission delay time can be reduced to about 75 bits, and the memory capacity can be reduced to about 65% compared to the conventional example.

In the above explanation, the speed conversion circuit and buffer circuit are used.

We decided to configure the interleave circuit and demetaleave circuit with shift registers, but some of these circuits,
It goes without saying that the same result can be achieved even if the entire system is configured using random access memory or the like.

[Brief explanation of the drawing]

1 and 2 respectively show configuration examples of a transmitting section and a receiving section of a two-wire time-division direction control system to which the present invention is applied,
3 and 4 are operational waveform diagrams of the conventional transmitter and receiver, respectively, and FIGS. 5 and 6 are operational waveform diagrams of the transmitter and receiver of the present invention, respectively. Speed conversion circuit, 13...Test bit generation circuit, 14...Gutsufa circuit, 15...Interleave circuit, 22...No4 Tsufa circuit, 23...Reception timing generation circuit,
24...Difter 1 nof 9 circuit, 25...Error correction circuit, 26...Syndrome generation circuit, 27...
Speed conversion circuit.

Claims (1)

[Claims] A data line termination device using a one- or two-wire time-division direction control system, comprising an error correction circuit and an interleaving circuit that periodically converts the arrangement of data signals within the same period according to the two-wire time-division direction control system. This error correction method is characterized by the following.