JPS6184198A - Digital processing circuit of video signal - Google Patents

Abstract

PURPOSE:To process signals of NTSC and PAL systems in the same circuit and to scale down a signal processing circuit by constituting such that the phase of decimation is shifted by horizontal synchronizing signal. CONSTITUTION:A three frequency divider circuit 21 divides a sampling pulse fs into three parts, and divided frequency signals f1, f2 and f3 having different phases are produced. A data selector 22 sequentially selects and outputs these divided frequency signals f1, f2 and f3 by horizontal synchronizing signal. Namely the switching is sequentially executed f1 f2 f3 f1 f2... in this order. The timing of the switching is earlier in a horizontal synchronizing signal period. Input data of several bits for coming from the left in the figure is provisionally latched by a latch A23 with the aid of the sampling frequency fs, interpolated by 1/3 in a latch B24 and latched again.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a video signal digital processing circuit, and particularly to a video signal digital processing circuit that samples a video signal at a frequency that is an integral multiple of a horizontal synchronizing signal frequency other than an integral multiple of 3. When performing decimation, by shifting the decimation phase for each horizontal synchronization signal, the NTSC and PAL systems can be processed in the same circuit, and the scale of the signal processing circuit can be reduced. Regarding circuits.

(Prior Art) In recent years, a method has been developed in which a video signal is digitized and then this digital signal is processed.
This has been attempted as a way to reduce the number of capacitors, resistors, coils, or eliminate adjustment, and some manufacturers are commercializing it as a "digital television."

In addition, the current television broadcasting system is NTSC.
The main systems currently in existence are the PAL and 5ECAH systems, but the market for the NTSC and PAL systems is especially large, and the color signal multiplexing system is more popular than the 5ECAH system.
Both of these types have similar characteristics.

Therefore, both the NTSC and PAL systems are the same (
Alternatively, if signal processing can be performed with a circuit similar to that of the conventional one, the benefits would be significant.

Furthermore, since there is no major difference in luminance signals between the NTSC system and the PAL system except for the frequency band, if the color signal processing circuit is shared, it becomes possible to configure the NTSC system and the PAL system with the same circuit.

(Object of the Invention) Therefore, the object of the present invention has been made in view of the above-mentioned prior art, and is to provide a video signal that can process signals of the NTSC system and PAL system in the same circuit, and that can reduce the scale of the signal processing circuit. An object of the present invention is to provide a digital processing circuit.

(Means for Solving the Problems) In order to solve the above object, the present invention samples a video signal at a frequency that is an integer multiple other than an integer multiple of 3 of the horizontal synchronization signal frequency, and performs high decimation. The present invention provides a video signal digital processing circuit characterized in that the decimation phase is shifted for each horizontal synchronization signal.

(Example) Regarding the video signal digital processing circuit according to the present invention,
This will be explained below.

Generally, the frequency at which a video signal is sampled is
According to the "sampling theorem", it must be higher than twice the highest frequency included in the analog signal, usually about 10MHz.
z or higher is suitable (condition ■).

Furthermore, in order to configure a comb-shaped filter for color signal processing, sampling points must be arranged vertically on the screen. In other words, the sampling frequency must be an integral multiple of the horizontal synchronization signal frequency (condition ■).

Furthermore, in the case of the NTSC system, the comb filter is 1
A delay circuit (delay line; memory) for H (H is the horizontal scanning period) is required (in the case of PAL system, for 2 days), but the higher the sampling frequency, the more memory that makes up the filter is used. I will do it. Therefore, since the band of the color signal is narrower than that of the luminance signal, it is effective to perform decimation processing.

By making the subcarrier (color printing carrier wave) frequency common between the NTSC system and the PAL system, color signal processing can be performed for both systems using substantially the same circuit.

Here, the sampling frequency (fs) that satisfies the above conditions (1) and (2) is as shown in the following table.

In addition, in the above table, fH = 15.734265 in case of NTSC system
In the case of kHz PAL method f H = 15.625
Assuming that a composite video signal of the NTSC system or PAL system is sampled at one of the frequencies fs in the kHz table, the signals of both systems can be converted into a luminance signal (Y) using the same circuit.
) and the color signal (C), it is sufficient to convert the frequency of the subcarriers of the color signal so that they are common to each other. By making the above common, the subsequent processing circuits can also be made common.

At that time, the frequency of the subcarrier to be converted is set to +
fs, compared to other Jrfs, D
Both P (differential phase) and DG (differential gain) are minimized.

Here, decimation processing, which is one type of digital signal processing, will be explained. This decimation process divides the sampled data into one piece on the time axis.
Alternatively, it means leaving every two, three, etc. as significant data and lowering the sampling frequency by ÷, +, +, etc.

Furthermore, in digital signal processing of video signals, filters are configured depending on various uses, and the higher the sampling frequency, the larger the filter configuration.

For example, if a two-day comb filter is applied to a PAL video signal converted into an 8-pit digital signal at a sampling frequency of 18 MHz, a memory of 2 x 1152 x 8 bits (18,432 bits) is required. On the other hand, if you perform the old decimation (leaving every second data and setting the sampling frequency to 6MH), the memory required is 6144 pits, which is 12
．． 288 pits can also reduce memory. This is a very small number, which covers the circuitry that is increased by decimation.

As described above, by performing decimation processing, it is possible to significantly reduce the circuit scale, and this can be said to have a large impact on cost, power consumption, reliability, etc.

When performing decimation processing as described above, as shown in Figure 2, if the subcarrier is ten times the sampling frequency (fs), the decimation process (as shown in Figure 2(a)) will occur. However, in the operation of validating every other sampling point, the signal loops back at +fs, resulting in the signal looping back to the subcarrier itself. In addition, in the case of double decimation (as shown in Figure 2 (C)), which is an operation in which every third sampling point is enabled, the subcarrier component disappears and returns to the baseband, resulting in subsequent signal processing. It becomes difficult to handle.

Therefore, blue decimation processing as shown in FIG. 2(b) can be considered. That is, since the blue decimation processing returns the signal at the sound fS, the signal component does not overlap with the original signal, and the band is sufficient (fs), so it is the most effective. Furthermore, this blue decimation process also reduces the number of circuits.

Here, even if we perform blue decimation, still
The frequency at which sampling points for each line (horizontal scanning line) are arranged vertically on the screen is only when the frequency is a multiple of an integral multiple of 3 of the horizontal synchronizing signal frequency. In other cases, the sampling points for each line (horizontal scanning line) will shift.

This means that PAL systems always (in the examples in the table above)
This is because, while the frequency is a multiple of 3, this is not necessarily the case with the NTSC system.

Also, from the table, when it is a multiple of 3, it is 13.50M) 1 and 20
．． 25M) 1g, but 20.25M)lz has a high frequency and is difficult to pump. Furthermore, the band of 13.50 MHz is approximately 6 MH2, which may not be sufficient for the PAL system.

Therefore, as a frequency other than a multiple of 3, for example, 15.7
5 MH a or 18. When OOMH, etc. are selected as the sampling frequency, it is necessary to take measures such that the sampling points after decimation are arranged vertically on the screen.

Therefore, when the frequency is not a multiple of 3, the decimation phase is shifted within the horizontal synchronization signal once per line. In this way, sampling points can be arranged vertically on the screen. For example, sampling frequency f S = 18.00 MHz
, 18.00 MHz = f H (PAL)
1152 (=384 x 3) = f H (NTSC
)X 1144, and for the horizontal synchronization signal frequency f of the PAL system, the above 18.00 > AHz is an integral multiple of three times the horizontal synchronization signal frequency fH (i.e., 1152 (=3
84 x 3)), so even if you perform temple digitization, the sampling points will be lined up vertically (
(shown in FIG. 2(a)).

However, for the horizontal synchronizing signal frequency fH of the NTSC system, 1144 is not a multiple of 3, so when blue decimation is performed, the sampling point shifts.

That is, in the NTSC system, 18.00 MH
When sampling is performed, the result is as shown in Figure 2 (b), for example, 3M (CM is an integer) is the 1143rd, 3M +
1 becomes the 1144th point, and when blue is decimated, the sampling point shifts one by one to the left on the screen.

Therefore, in the case of decimation, which is an operation in which every second sampling point is valid, the sampling is not thinned out at the end of 1H (which is convenient because there is no color during the horizontal blanking period), but only once consecutively. By performing an operation to enable the sampling points, it becomes possible to arrange the sampling points vertically on the screen. That is, it becomes as shown in FIG.

Further, it is possible to perform the same operation when other sampling frequencies fs = (3M + 1)Xf + 4, and further, fs - (3M - 1) xfH (
7) By performing decimation in which the number of sampling points is reduced from 2 to 1, which is thinned out once every 1H, it is possible to arrange the sampling points vertically within the screen.

FIG. 1 is a diagram showing an embodiment of a video signal digital processing circuit according to the present invention, for example, a digital signal processing circuit of a digital magnetic recording and reproducing apparatus that digitally processes a video signal and records and reproduces it on a magnetic recording medium. We will explain what is applied to.

In the figure, 1 is an input terminal, a composite video signal is supplied to this input terminal 1, and this composite video signal is A
The signal is converted into a digital signal by a D converter 2, and its frequency is converted by a frequency converter 3. Here, frequency converter 3
When recording, the frequency ranged from 3.58MHz to 4.5MHz.
The frequency is converted to 629kHz during playback, and 4.5M
The frequency is converted to Hz.

Note that the sampling frequency fs at this time is 18, OOM
Let it be Hz.

Furthermore, a bandpass filter (BPF) for YC separation
After blue is subjected to decimation (thinning) processing in the decimation processing circuit 5 via the digital processing circuit 4, the digital processing circuit 6 performs ACC (automatic color signal level control) and AP.
Digital processing such as C (automatic phase control) is performed, and then the interpolation circuit 9 passes through a signal processing filter 7 and a comb-shaped filter 8 for canceling crosstalk during playback.
Then, decimation processing (interpolation processing) opposite to that of the decimation processing circuit 5 is performed to restore the decimation to its original state.

Then, the signal is frequency-converted again by a frequency converter 11 via an interpolation band-pass filter (BPF) 10. Here, the frequency converter 11 uses 4.5 MH when recording.
The frequency is converted from engineering to 629 to 8, and when playing it is 4.5
The frequency is converted from MH, to 3.58MH. Finally, it is converted into an analog video signal by the DA converter 12 and output from the output terminal 13.

In addition, 14.16 is a data generation excavator for supplying data for frequency conversion to the frequency converter 3.11, and 15 is a data generation excavator for supplying data for frequency conversion to the frequency converter 3.11.
This is a control section that supplies subsurface signals to the digital processing circuit 6 and oscillators 14 and 16 in response to a TSC mode instruction signal. Reference numeral 17 denotes an excavator that supplies a clock signal (sampling frequency fs) to each of the digital signal processing circuits described above.

FIG. 2 is a diagram showing an example of the configuration of the decimation processing circuit 5 in the video signal digital processing circuit according to the present invention shown in FIG. In the same figure, a frequency divider circuit 21 is a circuit that divides the sampling frequency fs by three and generates frequency-divided signals t'+ and f2°fs (shown in the third diagram) having different phases.

The data selector 22 also outputs a 1-horizontal open period signal (H5yn
C), these three frequency-divided signals f1° f2 . This circuit sequentially selects and outputs f. That is,...→f1
→ f2 → f3 → f1 → f2 → . . . Note that the switching timing is set early during the horizontal synchronization signal period.

Also, several bits of input data coming from the left in the diagram are
The signal is once latched at the sampling frequency fs by the latch A23, and further decimated to blue by the latch B24 and launched.

By configuring as described above, one circuit configuration can be made easily, and the sampling frequency fs is selected to be an integral multiple of the horizontal synchronizing signal frequency of the video signal other than an integral multiple of 3, and the kidecimation can be performed. In doing so,
By configuring the decimation phase to be shifted for each horizontal synchronization signal, it becomes possible to process signals for the NTSC system and the PAL system using the same circuit.

(Effects of the Invention) As described above, the video signal digital processing circuit of the present invention has features such as being able to process signals for NTSC and PAL systems using the same circuit and reducing the size of the signal processing circuit. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a video signal digital processing circuit according to the present invention, and FIG. 2 is a diagram showing an example of the configuration of a decimation processing circuit in the video signal digital processing circuit according to the present invention shown in FIG. , FIG. 3 is a diagram for explaining the circuit operation of FIG. 2. 1...Input terminal, 2-...AD converter, 3.11...
・Frequency converter, 4, 10... BPF. 5... Decimation processing circuit, 6... Digital processing circuit, 7... Filter, 8...
...Comb filter, 9...Interpolation circuit, 12...D
A converter, 13... Output terminal, 14, 16.17...
・Development organ, 15...control unit, 21...3 frequency dividing circuit,
22...Data selector, 23, 24...Latch. Patent Applicant: Victor Japan Co., Ltd.

Claims (1)

[Claims] When sampling a video signal at a frequency that is an integer (3M±1, M is a positive integer) times the horizontal synchronization signal frequency other than an integer multiple of 3 and performing 1/3 decimation, the phase of the decimation is set to the horizontal synchronization signal. 1. A video signal digital processing circuit characterized in that the video signal digital processing circuit is configured to shift each time.