JPH0438195B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a video signal digital processing method, and in particular, it is possible to process signals of the NTSC system and PAL system in the same circuit. The present invention relates to a video signal digital processing method that can reduce the scale of a signal processing circuit by using PS (phase shift) processing and decimation processing. (Prior art) In recent years, the method of digitizing and processing video signals has become an excellent method in terms of reducing the number of circuit components (mainly capacitors, resistors, and coils) and eliminating the need for equipment adjustments. Many research and developments related to this have been attempted, and some manufacturers are commercializing it as a "digital television." In addition, the current television broadcasting systems mainly include the NTSC, PAL, and SECAM systems, but the market for the NTSC and PAL systems is especially large, and the color signal multiplexing system is
Compared to the SECAM method, both of these methods have the characteristic of being similar. Therefore, if it were possible to perform signal processing for both the NTSC system and the PAL system using the same (or approximately equivalent) circuit, it would be a great advantage. Furthermore, since there is no major difference in luminance signals between the NTSC and PAL systems except for the frequency band, if the color signal processing circuits are standardized, the NTSC and PAL systems can be used.
It becomes possible to configure the PAL system using the same circuit. (Object of the invention) Therefore, the present invention has been made in view of the above-mentioned prior art, and its object is to provide an NTSC system,
PAL format can be processed in the same circuit,
For example, when digital signal processing is used to process the color signals of a magnetic recording/reproducing device (VTR), video signal digital processing can reduce the size of the signal processing circuit by using PS (phase shift) processing and decimation processing. The purpose is to provide a method. (Means for Solving the Problems) In order to achieve the above object, the present invention changes the sampling frequency when sampling an input analog video signal and converting it into digital data to match the horizontal synchronization of the analog video signal. The frequency is N times the signal frequency (N is an integer), and the integer N is divided by 4 to make N = 4K + M (K is an integer, M is any number of 0, 1, 2, or 3), and the above-mentioned Divide the integer N by 3 to get N=3L+Q (L is an integer, Q is 0,
+1, -1), P=M+
The integer P represented by Q is set to be an even number, and 1/3 decimation processing is performed to leave every second sampling point on the time axis as valid data from among the sampled and converted digital data. The present invention provides a video signal digital processing method. (Example) A video signal digital processing method according to the present invention will be described below. Generally, the frequency when sampling an analog video signal and converting it to digital data must be higher than twice the highest frequency included in the analog signal, according to the "sampling theorem", and approximately 10 MHz or higher is usually suitable ( conditions). Furthermore, in order to configure a comb-shaped filter for color signal processing, sample points must be arranged vertically on the screen. In other words, the sampling frequency must be an integral multiple of the horizontal synchronization signal frequency (condition). Furthermore, in the case of the NTSC system, the above-mentioned comb-shaped filter requires a delay circuit (delay line; memory) for one line (horizontal scanning period).
In the case of PAL system, two lines are required, but
The higher the sampling frequency, the more memory that constitutes the filter will be used. Therefore, since the band of the color signal is narrower than that of the luminance signal, it is effective to perform decimation processing. By making the subcarrier (color subcarrier) frequency common between the NTSC system and the PAL system, color signal processing for both systems can be performed using substantially the same circuit. Here, the above conditions and the sampling frequency (f _S ) that satisfies the conditions are as shown in the following table.

[Table] In the above table, f _H = 15.734265kHz for NTSC system, f _H = 15.625kHz for PAL system, f _H = 15.625kHz for NTSC system, PAL system at any frequency f _S in the table.
Assuming that the composite video signal of each method is sampled, the signals of both methods can be sampled using the same circuit.
For example, in order to separate the luminance signal Y and the color signal C, the frequency of the subcarrier of the color signal is converted,
It would be better to make them common to each other. By making the above common, the subsequent processing circuits can also be made common. At this time, if the frequency of the subcarrier to be converted is, for example, 1/4f _S , both DP (differential phase) and DG (differential gain) will be minimum compared to other cases where it is set to 1/3f _S. Here, decimation processing, which is one of the digital signal processing methods, will be explained. This decimation process divides the sampled data into one, two, or three parts on the time axis.
It means to leave every 1... as significant (valid) data and lower the sampling frequency to 1/2, 1/3, 1/4, etc. In addition, in digital signal processing of video signals, filters are configured depending on various uses.
The higher the sampling frequency, the larger the filter configuration. For example, if a 2H comb filter is applied to a PAL video signal converted into an 8-bit digital signal at a sampling frequency of 15.75MHz,
×8 bits (16.128 bits) of memory is required. On the other hand, if we perform 1/3 decimation processing (leaving every second piece of data and setting the sampling frequency to 1/3 to 5.25MHz), the required memory will be 1/3, 5376 bits, and 10752 bits. Memory can be reduced. This number is enough to compensate for the additional circuitry required by the decimation process. By performing decimation processing in this manner, it is possible to significantly reduce the circuit scale, and it can be said that this has a large impact on cost, power consumption, reliability, etc. When performing the above decimation process, as shown in Figure 2, if the subcarrier is 1/4 of the sampling frequency (f _S ),
Decimation of 1/2 {shown in Figure 2 a}, that is,
An operation in which every other sample point is valid results in the signal aliasing around 1/4f _S , and ending up aliasing back to the subcarrier itself. Furthermore, in the 1/4 decimation {shown in FIG. 2c}, that is, in the operation of validating every third sample point, the subcarrier component disappears and the signal returns to the baseband, making subsequent signal processing difficult to handle. Therefore, 1/3 decimation processing as shown in FIG. 2b can be considered. In other words, since 1/3 decimation processing folds back at 1/6f _S , the signal components do not overlap with the original signal, and the bandwidth is sufficient (±
1/12f _S ), which is the most effective. Furthermore, by processing this 1/3 decimation, the circuit size can also be reduced by 1/3.
Reduce to. Here, even if 1/3 decimation processing is performed, the frequency at which the sample points for each line (horizontal scanning line) are arranged vertically on the screen is an integral multiple of 3 of the horizontal synchronization signal frequency. Only when Otherwise, the sample points for each line (horizontal scanning line) will shift. This is because the PAL system always has a frequency that is a multiple of 3 (in the examples in the table above), whereas the NTSC system does not always have a frequency that is a multiple of 3. By the way, in the color signal processing circuit of a magnetic recording/reproducing device (VTR), the phase of the color signal is shifted (transitioned) by 90 degrees for each line (horizontal scanning period) and recorded. In some cases, so-called PS (Phase Shift) processing is used, or in other cases, so-called PI (Phase Invert) processing is used, in which the phase is inverted and recorded on a line-by-line basis. This demodulation can also be performed by digital processing, and can be performed by a frequency converter in a digital signal processing circuit of a digital magnetic recording/reproducing apparatus, which will be described later. In addition, as processing to remove crosstalk from adjacent signal tracks, PS processing or
This is done by demodulating the PI processed data and performing addition processing between two adjacent lines (horizontal scanning lines).
This is because the phase is reversed and canceled by processing or PI processing). In other words, it is a condition for the above-mentioned addition process that the phases be aligned between two adjacent lines. Therefore, if the sample points shift after decimation, the above addition process cannot be performed even if the phases are aligned. In other words, even if the sample points are shifted, as long as the phases match (align), addition processing can be performed. Let's now consider the phase relationship of the NTSC system. Note that the sampling frequency f _S is an integer N times the horizontal synchronizing signal frequency f _H , and the remainder when dividing the integer N by 4 is M (N = 4K + M, K is an integer, M is 0,
1, 2, or 3), and an integer N
When the remainder when divided by 3 is Q (N = 3L + Q, L is an integer, Q is any number of 0, +1, -1), then P = M + Q. (P is also an integer) Figure 3 shows the sampling frequency f _S =15.75MHz {=
f _H ×1001, M=1 (1001=4×250+1), Q=-
1 (1001=3×334-1), P=1-1=0},
Subcarrier frequency is 1/4f _S
(3.9375MHz), indicating that there are 250.25 subcarrier waves on one line. Also, Figure 3a is the nH line, Figure 3b is the (n
+1) H line, Figure 3c shows the (n+262) H line, and in the figure, ● indicates the sampling frequency.
15.75MHz sample point, ○ indicates the sample point after decimation. In the figure, the nH line in Figure 3a and the (n+1)H line in Figure 3b below it are as follows:
As shown by the waves of 3.9375MHz thick solid lines I and I', 1H
The phase has advanced by 90° compared to before. Also, in the figure, the longer wavelength 1.3125MHz wave,
′ (thin solid line) is decimated by 1/3,
This is a subcarrier folded back to 1.3125MHz. Also, between the nH line and the (n+1)H line,
The phases of the 15.75MHz waves (thick solid lines I and I') are mutually
However, the phases of the 1.3125MHz waves (thin solid line, ′) differ by 30° from each other. However, the sample phases after decimation for the 1.3125MHz wave on both lines are 0°, 90°, 180°,
270°, and the closest points are in the same phase (for example, point x and point x' or point y in the figure
y′ point, z point and z′ point, etc.). Further, the above phase relationship is the same for (n+262)H, which is the crosstalk component in FIG. 3c. Strictly speaking, the sample points are not arranged vertically, but the time is 63 ns (i.e., 1001 ns of one line).
The difference is only 1/1), so there is no problem as long as the phases match. From the above, it can be seen that even if the sample points are shifted, by matching the phases, crosstalk between two lines can be eliminated. The above was an example of 15.75MHz, but in general,
Subcarrier 1/4f _S for sampling frequency f _S
Therefore, the number A of waves in one line and its remainder B can be expressed as f _S = f _H × 4 × A + B, 4 > B ≧ 0. When B is not 0, the phase of the subcarrier for each line is 1. Shift the phase by /4×B. Further, the number of samples C in one line after decimation and its remainder D can be expressed as f _S ÷ f _H =3×C+D, 3>D≧0, and like B, the sampling points are also shifted by D from line to line. If B and D match, a 1H comb-shaped filter or the like in the PS processing described above can be constructed. Further, even if B and D do not match, if B-D=2, it can be easily constructed by replacing the addition circuit of the comb-shaped filter with a subtraction circuit. A specific example is 13.50MHz (M=2, Q=0, P=2). Figure 4 shows the sampling frequency f _S =13.50MHz {=
f _H ×858, M=2 (858=4×214+2), Q=0
(858=3×286+0), P=2+0=2}, and the subcarrier frequency is 1/4f _S (3.375MHz)
This shows that there are 214.5 subcarrier waves in one line. Also, Figure 4a is the nH line, Figure 4b is the (n
+1) H line is shown; in the figure, ● indicates a sample point with a sampling frequency of 13.50 MHz, and ○ indicates a sample point after decimation. In the figure, the nH line in Figure 4a and the (n+1)H line in Figure 4b below it are as follows:
As shown by the thick solid lines I and I′ waves at 3.375MHz, 1H
The phase has advanced by 180° compared to before. Also, in the figure, the longer wavelength 1.125MHz wave,
′ (thin solid line) is decimated by 1/3,
This is a subcarrier folded back to 1.125MHz. Also, between the nH line and the (n+1)H line,
The phases of the 3.375MHz waves (thick solid lines I and I') are mutually
They differ by 180°, but the phases of the 1.125MHz waves (thin solid line, ′) also differ by 180° from each other. However, the sample phases after decimation for the 1.125MHz wave on both lines are 0°, 90°, 180°,
They are the same at 270°, and the closest points are in opposite phase (for example, points x and x', points y and y', and z
point and z′ point, etc.). Including the above two cases, if we generalize the case when there is no surplus of waves (that is, one line's subcarrier is an integer multiple of waves) and the sampling point after decimation does not shift, the sampling frequency is It would be best to choose as follows. That is, the frequency is N times the horizontal synchronization signal frequency of the analog video signal (N is an integer), and
Divide that integer N by 4, N = 4K + M (K is an integer,
M is any number of 0, 1, 2, or 3), and the above integer N is divided by 3 to give N = 3L + Q (L is an integer, Q is any number of 0, +1, -1). , P=M
Make the integer P +Q an even number. FIG. 1 is a diagram showing an embodiment of a circuit to which the video signal digital processing method of the present invention is applied. What is applied to the digital signal processing circuit will be explained. In the same figure, 1 is an input terminal, a composite video signal is supplied to this input terminal 1, this composite video signal is converted into a digital signal by an AD converter 2, and then its frequency is converted by a frequency converter 3. be done. Here, in the frequency converter 3, the frequency is converted from 3.58MHz to 3.9375MHz during recording, and from 629kHz to 3.9375MHz during playback.
PS demodulation processing of the color signal is performed. Note that the sampling frequency f _S at this time is 15.75MHz. Furthermore, after being subjected to 1/3 decimation processing in a decimation processing circuit 5 via a bandpass filter (BPF) 4 for YC separation, ACC (automatic color signal level control) is performed in a digital processing circuit 6. Digital processing such as APC (automatic phase control) and the like is performed, and then the interpolation circuit 9 passes through a signal processing filter 7 and a comb-shaped filter 8 for crosstalk cancellation during playback to the decimation processing circuit 5. A reverse decimation process (interpolation process) is performed to restore the decimation. Then, the signal is frequency-converted again by a frequency converter 11 via a bandpass filter (BPF) 10 for interpolation. Here, in the frequency converter 11, the frequency is converted from 3.9375MHz to 629kHz during recording, and from 3.9375MHz to 3.58MHz during reproduction. Finally, it is converted into an analog video signal by the DA converter 12 and output from the output terminal 13. In addition, 14 and 16 are data generation oscillators for supplying data for frequency conversion to the frequency converters 3 and 11, and 15 is a data generation oscillator for supplying data for frequency conversion to the frequency converters 3 and 11. The digital processing circuit 6 and the oscillator 14,
This is a control unit that supplies control signals to 16. Reference numeral 17 denotes an oscillator that supplies a clock signal (sampling frequency f _S ) to each of the digital signal processing circuits described above. By configuring as described above, the circuit configuration can be simplified, and the sampling frequency f _S can be set to N times the horizontal synchronization signal frequency of the analog video signal as described above (N is an integer), and Divide N by 4 to get N=4K+M (K is an integer, M is any number of 0, 1, 2, or 3), and divide the integer N by 3 to get N=3L+Q (L is an integer, Q is 0). ，
+1, -1), P=M+
By setting the integer P, which is Q, to be an even number, it becomes possible to process signals for the NTSC system and the PAL system using the same circuit. (Effects of the Invention) As described above, according to the video signal digital processing circuit of the present invention, it is possible to process signals of the NTSC system and the PAL system in the same circuit, and for example, it is possible to process the color signal of a magnetic recording/reproducing device (VTR). When digital signal processing is used, it has the advantage that the scale of the processing circuit can be reduced by using PS (phase shift) processing and decimation processing.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a circuit to which the video signal digital processing method of the present invention is applied, and FIG.
Figures a to c, Figures 3 a to c, and Figure 4 a to
FIG. 1B is a diagram for explaining the principle of the video signal digital processing method according to the present invention. 1...Input terminal, 2...AD converter, 3, 11
...Frequency converter, 4,10...BPF, 5...
Decimation processing circuit, 6...Digital processing circuit, 7...Filter, 8...Comb filter,
9...Interpolation circuit, 12...DA converter, 13...
Output terminal, 14, 16, 17... Oscillator, 15...
...control section.

Claims (1)

[Claims] 1. The sampling frequency when sampling the input analog video signal and converting it into digital data is set to a frequency N times the horizontal synchronizing signal frequency of the analog video signal (N is an integer);
Then, divide the integer N by 4 to get N=4K+M (K is an integer, M is any number of 0, 1, 2, or 3), and divide the integer N by 3 to get N=3L+Q (L is an integer). , Q is any number of 0, +1, -1), P = M + Q, so that the integer P is an even number. A video signal digital processing method characterized in that 1/3 decimation processing is performed to leave sampling points as valid data.