JPS6175452A - Interruption circuit - Google Patents

Abstract

PURPOSE:To prevent interruption processing from being interrupted by other interruptions and to initiate an efficient interruption by giving respective interruption requests, having equal priority and inhibiting other interruptions during interruption processing. CONSTITUTION:While a low-priority peripheral device 22 performs interruption processing, a flip-flop 33 and an OR gate 34 detect the peripheral device 22 in the act of performing the interruption processing and inhibits an interruption from a high-priority periphery device 21. Then, the transmission of the interruption inhibition to the low-priority peripheral device 22 by this peripheral device 21 through a daisy chain is cut off by a flip-flop 31 and an OR gate 32, and the interruption permission of the peripheral device 22 is held. Consequently, the interruption of the interruption processing of the peripheral device 22 by other peripheral devices is eliminated. Thus, the interruption is carried out efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an interrupt circuit, and more particularly to an interrupt circuit with equal priorities in a daisy chain.

[Technical background of the invention and its problems]

2. Description of the Related Art One interrupt processing method frequently used in information processing devices such as electronic computers is an interrupt processing method prioritized by a daisy chain.

This daisy chain (prioritization by

In a plurality of information processing devices equipped with input terminals and output terminals for transmitting interrupt requests, each output terminal is connected to the input terminal of the next information processing device, that is, connected in series in the "imozuru style" to form a chain. It is determined by sequentially transmitting chain signals to lower-level devices. That is, when a device generates an interrupt request to the central processing unit (CPU) of a computer, generation of the interrupt request is prohibited to devices connected lower than the device. Therefore, in this method, the end of the chain has a lower priority.

An interrupt circuit using this daisy chain was published in the magazine “
This interrupt circuit is described in "Transistor Technology September 1982 issue", pages 259 and K, pages 260, and this interrupt circuit is shown in FIG. 6, and its outline will be explained below.

In the figure, output terminals for outputting interrupt requests of peripheral devices 11 to 14 are connected to the interrupt request input terminal of the CPU 10 by wired OR, and are pulled up by a resistor R. Also, the interrupt enable input terminal IEI of the device 11 with the highest priority is held at "H". As long as "H" is applied to this interrupt enable input terminal IEI, that device cannot generate an interrupt request. Therefore, the device 11 can always generate an interrupt request. Then, the interrupt enable output terminal IEO of the device 11 is connected to the input terminal IEI of the device 12 having the next lowest priority. When 'L#' is output from the interrupt enable output terminal IEO, 1L" is applied to the input terminal IEI of a device connected below that device, so that device is prohibited from generating an interrupt request. . “L” is output from the output terminal IEO because
When the device generates an interrupt request and disables the interrupt of the lower device, and when the input terminal IEI of the device is
This is a case where interrupts are prohibited by applying L'' and the interrupt prohibition is transmitted to the lower layer.

Below, the output terminal IEO is sequentially converted into the input terminal IEO of the lower device.
The output terminal IEO of the device 14, which has the lowest priority, is left alone. A daisy chain is thus formed between devices 11-14, with device 11 having the highest priority and device 14 having the lowest priority.

In the interrupt circuit configured as described above, in the initial state, the input terminals IEI of all the devices 11 to 14 are @H#, so any device can issue an interrupt request. Here, if the device 13 generates an interrupt request to CPU10, this device 13 outputs the output terminal IEO to °L#
, and prohibits generation of interrupt requests from lower-level devices 14.

When the device 13 that has issued the interrupt request receives an interrupt response from the CPU 10, it sends its own vector via the data bus of the CPU 10, skips the program of the CPU 10 to the interrupt processing routine, and performs the interrupt processing.

At this time, the device 14 that has a lower priority than the device 13 that is processing the interrupt has its input terminal IEI set to L''.
is being applied, it is not possible to issue an interrupt request. On the other hand, devices 11 and 12 that have higher priority than device 13
Since "H" remains applied to its input terminal IEI, an interrupt request can be generated even when the device 13 is processing an interrupt.

In the above description, the devices 11 to 14 are general information processing devices, but if they are connected to a communication line and receive and process transmitted data via the communication line, for example, the following problems arise. That is, when data is transmitted from a communication line connected to the device 13 and the device 13 issues an interrupt request and is processing the reception of the transmitted data, the device 13 is connected to the device 11 or device 12 with a higher priority. When data is transmitted from the communication line, the device 11
．． 12 issues an interrupt request and performs reception processing, so
There is a problem in that the interrupt processing of the device 13 is interrupted, making it impossible to receive transmitted data.

The problem with this problem is that when a specific interrupt occurs, interrupts with lower priorities can be disabled, but interrupts with higher priorities cannot be disabled. This is due to the fact that there is no such thing.

As another interrupt processing method, there is a method in which each peripheral device freely generates an interrupt request without prioritizing it, and the CPU grants interrupt permission in response to the interrupt request, but the process of granting the interrupt permission is very difficult. has the disadvantage of becoming complicated. Furthermore, since the processing becomes complicated, the time required to grant and register an interrupt increases, resulting in the disadvantage that high-speed interrupt processing becomes extremely complicated.

[Purpose of the invention]

An object of the present invention is to provide an interrupt circuit using a daisy chain, which can give equal priority to each interrupt request and prohibit other interrupts while 11 interrupts are being processed. be.

[Summary of the invention]

In this invention, in an interrupt circuit using a daisy-9 chain, when the peripheral device 22 shown in FIG. interrupts of peripheral devices 21 are prohibited. The above purpose is achieved by blocking the peripheral device 21 from transmitting interrupt disabling to the lower peripheral device 22 through a daisy chain using the 7 lip-flop 31° OR gate 32 and maintaining the interrupt permission of the peripheral device 22. .

[Embodiments of the invention]

An embodiment in which the interrupt circuit of the present invention is applied to two peripheral devices will be described below with reference to the drawings.

In FIG. 1 showing the circuit diagram of this embodiment, the CPU 20
The interrupt request input/terminal type of is connected to the interrupt request output terminals INT of peripheral devices 21 and 22 that perform information processing by wired OR, and is pulled up by a resistor R. The interrupt-enabled output terminal IEO of device 210 and the interrupt-enabled output terminal IEI of device 22 are connected through interrupt control circuit 30 to form a daisy chain.

Furthermore, the output terminal IEO of the device 22 is connected to the control circuit 30.
is connected to the input terminal IEI of the device 21 via.

Here, T1 to T4 are terminals of the control circuit.

The D-type flip 70 (hereinafter referred to as FF) 31 of the control circuit 30 is a circuit that maintains interrupt permission for the device 22 and outputs an enable signal when the device 22 is disabled during interrupt processing. This enable signal, together with the interrupt enable signal output from the output terminal IEO of the device 21,
An input terminal IEI of device 22 is provided by OR gate 32 . Furthermore, the FF33 and the OR gate 34 are connected to the device 22.
This circuit detects that the interrupt is being processed and, if the interrupt is being processed, outputs "L" as an interrupt detection signal to the terminal T2.Then, this terminal T2 is connected to the input terminal IEI of the device 210. By connecting to the above interrupt detection number 18, the generation of an interrupt request of the device 21, which originally has a higher priority than the device 22, is prohibited.
A system reset terminal RESET (not shown) is connected to the clear terminal CL of FF31, 33, and
Set the initial state of F31 and F33.

Next, the operation of the embodiment will be described with reference to FIG. 2g, which shows waveforms at various parts of the circuit diagram shown in FIG.

Set the RESET signal (Fig. 2g) to 11L for initial setting.
and release it at time t1. As a result, FF31.3
Q output of 3 (Fig. 2 g, f) iJl both K"L' (
! :Become. Here, since the device 21 has not issued an interrupt request, the output of the output terminal IEO (FIG. 2b) is 'H', and the enable signal 'H' (FIG. 2d) is output from the OR gate 32.
) is output and supplied to the input terminal IEI of the device 22. Since the device 22 also does not issue an interrupt request, the output of the output terminal IEO (Fig. 2g) becomes 'H', and the OR gate 32 outputs 'H' (Fig. 2g) as a detection signal. This g″H'H' output 210 input terminal IE
I to maintain permission for generation of interrupt requests. As described above, according to the initial settings, both devices 21 and 22 are in a standby state in which they can generate an interrupt request.

Therefore, a case where the device 21 generates an interrupt request will be explained. When the device 21 generates an interrupt request from the output terminal INT to the input terminal INT of the CPU 20 and the request is accepted by the CPU 20 at time t2, the output of the output terminal IEO of the device 21 (FIG. 2b) becomes "L". ” becomes. As a result, the output of the OR gate 32 (FIG. 2 d) becomes "L#", which prohibits generation of an interrupt request from the devices 22 connected in the daisy chain. Since the Q output of the FF 33 (FIG. 2 f) rises to H'', it holds that the interrupt request generation is prohibited from the device 21.

At time t3, which is delayed by a predetermined time from time t2, the output terminal IEO of the device 22 in which interrupts are disabled outputs "L" in order to transmit the interrupt disable signal transmitted from the higher-level device 21 to the lower-level device. be done. However, in this embodiment, since there is no device lower than the device 22, the information is not actually transmitted. Since the Q output of the FF 33 is "H", the signal "L" output from the output terminal IEO of the device 22 is an OR gate indicating the interrupt disable signal transmitted from the upper device 21. 34, and "H" indicating that the clutter device 22 is not being interrupted is output from the OR gate 34 (Fig. 2g)
. Therefore, H# is output from the OR gate 34 and supplied to the input terminal IEI of the device 210, so the device 2
1 can continue interrupt processing.
When the device 21 completes the interrupt processing at time t4, the output of the output terminal IEO changes from ``L'' to 1H'', thereby canceling the interrupt inhibition of the lower device 22.

The output terminal IEO of the device 22 whose interrupt prohibition has been canceled by this interrupt enable signal outputs "H" at time t5 in order to transmit the enable signal transmitted from the upper device 21 to the lower device. ``The above-mentioned FF 33, which holds the generation of interrupt request prohibition from the device 21 using the output as a clock, is set to ``L''. As a result, device 2
1.22 returns to the above-mentioned standby state.

Next, a case will be described in which the device 22 generates an interrupt request. The device 22 generates an interrupt request from the output terminal INT to the input terminal INT of the CPU 20, and when the request is accepted by the CPC 20 at time t6, the output terminal IE of the device 22
The output (Fig. 2 e) of
This is one input of 4. Here, the output terminal I of the device 21
Since @H” is still output from EO, FF33
The state of Q does not change, and the Q output remains uLs and becomes the other input of ORG-34. Therefore, the signal @L'' output from the output terminal IEO of the device 22 is detected by the OR gate 34 as a signal indicating that the device 22 is processing an interrupt.

Signal @LM indicating that an interrupt is in progress is OR gate 3
C82 diagram g) output from 4). The output "L" of this OR gate 34 is supplied to the input terminal IEI of the device 210, which is a higher-level device than the device 22, through the terminal T2, and the highest-level device 21 is prohibited from generating requests for interrupt processing. Ru. Also, the output of this OR gate 34 is FF3
Since it is supplied to the preset terminal PR of FF3, when this output falls from "H" to @L", FF3
The Q output of 1 (FIG. 2C) becomes H#. This prevents the interrupt of the device 22 from being interrupted by the interrupt disabling signal output from the output terminal IEO of the higher-level device 21 connected to the device 22 in a daisy chain.

At time t7, the device 21 outputs 'L' from the output terminal IEO in order to transmit the interrupt disable signal from the OR gate 34 to the lower device 22. However, as described above, the Q output of the FF 31 is In order to avoid interruption of the interrupt processing due to the interrupt disable signal transmitted from the device 21, H'' is held from time t6, so the OR gate 32 randomly outputs H# (FIG. 2d), and the device 22 remains enabled for interrupts.

When the device 22 finishes the interrupt processing at time t8, the output terminal I
The output of EO is changed from "L" to "H". In response to this interrupt enable signal, the OR gate 34 outputs °H# and cancels the interrupt prohibition of the device 21. When the interrupt prohibition is canceled, the device 21 outputs At time t9 after a predetermined time from terminal IEO, it outputs 'H' in order to transmit an interrupt enable signal to lower-order devices. Using this “H” output as a clock,
The above FF that holds interrupt permission for the device 21
Set 31 to 1L". This will complete the installation!!21.
22 returns to the above-mentioned standby state.

Here, the functions of the interrupt control circuit 30 will be explained. As described above, the FF 31 blocks the interrupt disabling signal from the daisy-chained higher-level device when the lower-level device is processing an interrupt, and maintains interrupt permission for the lower-level device. Output enable signal.

This enable signal is output from the OR game 32 together with an interrupt enable signal from a higher-order device and is supplied to the terminal T3. That is, an interrupt enable/permit signal for the lower level is output from the terminal T3.

Further, the FF 33 detects that interrupts of lower-order devices are prohibited and outputs a Q signal. On the other hand, from the output terminal IEO of the lower device, there is an interrupt disable signal that is used to transmit the interrupt disable signal transmitted from the upper device to the lower device, and an interrupt disable signal that is used when the lower device itself is processing an interrupt. An interrupt disable signal is output to disable interrupts from lower-level devices. Therefore, by gating the interrupt disable signal output from the output terminal IEO with the Q output of the FF33, it is possible to detect whether or not the lower device is interrupting, and the detection output is supplied to the terminal T2. Ru.

Then, from the interrupt detection signal outputted from this terminal T2, an interrupt disable signal to the highest-level device is generated and applied to the input terminal IEIK of the highest-level device.

As explained above, according to this embodiment, Daisy
When the lower device 21 of two devices connected by a chain is processing an interrupt, it is possible to prevent the higher device 22 from interrupting the interrupt processing of the device 21 and processing the interrupt. That is, the interrupt priorities of the device 21 and the device 22 can be made equal.

Next, an embodiment in which n peripheral devices are given equal interrupt priorities will be described with reference to the circuit diagram shown in FIG.

In FIG. 3, the interrupt request input terminal I of the CPU 40
The NT has peripheral devices 41, 42, 4 that perform information processing.
The interrupt request terminals INT of 3, . . . , 4n are connected by wired-OR and pulled up by a resistor R. Devices 41, 42, 43. . . , 4n are connected via the interrupt control circuit 30 to form a daisy chain. Here, the control circuit 30 has the same function as the control circuit 30 shown in FIG. Further, control circuits 30-2, 30-3, . . .

The output from 2 at each terminal of 30-n is AND gate 5
0, and the output of this AND gate 50 is supplied to the interrupt enable input terminal IEI of the topmost device 41.

As described above, the terminal T2 of the control circuit 30 outputs an interrupt detection signal from a lower-order device. For example, if the device 42 is processing an interrupt, "L" is output from the terminal T2 of the control circuit 30-2 as a detection signal. Therefore 1. Control circuit 30-2.30-3.

30-n to which each terminal T2 is connected) 5
From 0, devices 42, 43 . ..., any 1 of 4n
If the device 41 is processing an interrupt, wI, s is output, and the device 41 at the highest level generates an interrupt request in a standby state without supplying an interrupt disable signal to the device 41. When the interrupt request is accepted by the CPU 40, the device 41 sends the lower devices 42, 43, . . .
, 4n, outputs an interrupt disable signal from the output terminal IEO. This inhibition signal is sent to the lower devices 42, 43 . . . in a daisy chain.・
..., 4n, and each device is prohibited from interrupting. Here, the control circuits 30-2, 30-3, ..., 3
Since no interrupt detection signal is output from the terminals T2 of 0-n and all of them are at °H', "H" is supplied from the AND gate 50 to the input terminal IEI of the top device 410, and the signal of the device 41 is Interrupt status is retained. and,
When the device 410 interrupt processing is completed, an inhibit release signal is output from the output terminal IEO of the device 41, and is sequentially propagated to each device by the daisy chain. This causes all devices to be in an interruptible state, that is, in a standby state.

Next, a case will be described in which the device 43 performs interrupt processing. When the interrupt request is accepted by the CPU 40, the device 43
outputs 1L'' from the output terminal IEO to inhibit interrupts from lower-order devices.At the same time, the control circuit 30-3 detects the interrupt from the device 43 and supplies a detection signal "L" to the AND gate 50. Therefore, the top game device 50 outputs a prohibition signal @L'' which prohibits the top-level device 410 from interrupting, and the device 41 is prohibited from interrupting. Furthermore, this device 41 propagates the inhibit signal to lower-level devices through the output terminal IEO, and the device 42 is also inhibited from interrupting. An inhibit signal is also output from the output terminal IEO of this device 42, but since the terminal T3 of the control circuit 30-3 holds the interrupt permission for the device 43 as described above, the device 43
can continue processing the interrupt. And device 4
30 When the interrupt processing is completed, the output terminal I of the device 43 is
A prohibition release signal is output from the EO and is sequentially transmitted to lower-order devices through a daisy chain. In addition, the control circuit 3
The interrupt detection signal is not outputted from the terminal T2 of 0-3, but ``H'' is outputted. Therefore, the AND gate 50 outputs the interrupt enable signal ``H'', and the highest level device 41 does not accept the interrupt. The device 42 is also released.

As explained above, according to this embodiment, when one device among the n devices performs interrupt processing, no other device can process the interrupt, so the interrupt processing is not interrupted. do not have. That is, the interrupt priorities of n devices can be made equal. Therefore, even if the information processing device is connected to a communication line and receives and processes transmitted data via the communication line, no other interrupt request will be generated until the interrupt being processed is completed, and the This solves the problem of missing data inside.

Next, another embodiment will be briefly described with reference to FIGS. 4 and 5. In this method, peripheral devices having the same rotational order are formed into groups, and different optical rotation orders are set for these groups.

In FIG. 4 showing the circuit diagram of the embodiment, the interrupt request input terminal INT of the CPU 60 is connected to the interrupt request output terminals INT of the peripheral devices 61 to 66 that perform information processing in a wired-OR manner, and is pulled by a resistor R. Will be uploaded. The devices 61, 62, via the control circuit 30,
4 to 66 form a digital m-chain via a control circuit 70. Here, the control port WIA 70 is connected to the AND gate 7 in the control circuit 30, as shown in detail in FIG.
5. The circuit has an additional terminal T5.

In the embodiment with the above configuration, the devices 61 and 62 are in the first group, the device 63 is alone in the second group, and the devices 64 to 66 are in the second group.
form the third group, and the priorities within the group are equal. Also, since the groups are simply connected in a daisy chain, the first group has the highest priority and the third group has the lowest priority.

Here, the functions of the control circuit 700 will be explained. An interrupt disable signal from the upper group device 63 is applied to the terminal T5, and this disable signal gates the interrupt enable/permit signal from the OR gate 32. As a result, when a higher-level group generates an interrupt request,
Interrupt inhibition can be output from terminal T3.

As explained above, according to this embodiment, interrupt priorities can be set on a group-by-group basis.

〔Effect of the invention〕

According to the present invention, it is possible to provide interrupt circuits with equal priorities with a simple configuration, so that there is an advantage that efficient interrupt processing can be performed without being interrupted by interrupts from other peripheral devices during interrupt processing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the interrupt circuit of the present invention, FIG. 2 is a time chart explaining the operation of each part of the embodiment shown in FIG. 1, and FIGS. FIG. 5 is a circuit diagram showing some details of the embodiment shown in FIG. 4, and FIG. 6 is a circuit diagram showing a conventional interrupt circuit. 20...CPU 21.22...Peripheral device 31.33...Flip frog 32.34...Or gate

Claims (1)

[Claims] A plurality of peripheral devices whose interrupt priorities can be determined by daisy-chained connections, and interrupt disable signals transmitted from the peripheral devices connected above to the peripheral devices connected below. an interrupt permission retaining means for retaining interrupt permission for peripheral devices connected at the lower level; an interrupt detecting means for detecting the interrupt state of a peripheral device other than the peripheral device connected at the highest level; An interrupt circuit comprising an interrupt disabling means for disabling interrupts of a peripheral device connected to the highest level and disabling interrupts of a lower peripheral device by daisy chaining based on a detection result.