JPS6163048A - Memory module - Google Patents

Memory module

Info

Publication number
JPS6163048A
JPS6163048A JP59185042A JP18504284A JPS6163048A JP S6163048 A JPS6163048 A JP S6163048A JP 59185042 A JP59185042 A JP 59185042A JP 18504284 A JP18504284 A JP 18504284A JP S6163048 A JPS6163048 A JP S6163048A
Authority
JP
Japan
Prior art keywords
leads
package
flat package
ultraviolet
ultraviolet ray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59185042A
Other languages
Japanese (ja)
Inventor
Seiichi Kageyama
影山 精一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59185042A priority Critical patent/JPS6163048A/en
Publication of JPS6163048A publication Critical patent/JPS6163048A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/107Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/145Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To produce memory module with high mounting concentration by a method wherein a flat package of ultraviolet ray elimination type EPROM with an ultraviolet ray transmission window is deposited on flat patterns of other memory elements with the same dimension while exposing this window to atmosphere to connect these leads with circuit substrate provided on both sides. CONSTITUTION:A flat package 1 of ultraviolet ray elimination type EPROM with an ultraviolet ray transmission window such as glass on the surface is deposited on a laminated body of three static RAMs 3 with the same shape, width between leads. Next a pair of circuit substrates 4, 5 provided with conductive patterns on both sides of packages 1 and 3 are arranged in parallel with each other to insert leads 1a of package 1 and leads 3a of package 3 respectively into through holes 4a and 5a made into the circuit substrates 4, 5 and then bonded to each other using solder 6. Besides, dip leads 7 are fixed to the lower ends of substrate 4, 5 to connected to the conductive patterns on the substrates 4, 5.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は紫外線消去型EPROMを他のメモリ素子とと
もにQf、度で実装してなるメモリモジュールに関する
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory module in which an ultraviolet erasable EPROM is mounted with other memory elements in a Qf, degree.

[発明の技術的背景とその間Wi点] 紫外線消去型EPROM′チップは、書込まれたメモリ
データが紫外線を照射することにより消去されるように
構成されている。
[Technical Background of the Invention and Other Points] The ultraviolet erasable EPROM' chip is constructed such that written memory data is erased by irradiation with ultraviolet rays.

従来から、このような紫外線消去型EPROMチップを
実装してメモリモジュールを構成する場合には、EPR
OMのペアチップを他のメモリ素子とともに同一パッケ
ージ内に封入するとともに、このパッケージに紫外線透
過窓を設けることが行われている。
Conventionally, when configuring a memory module by mounting such ultraviolet erasable EPROM chips, EPR
A pair of OM chips is sealed together with other memory elements in the same package, and the package is provided with an ultraviolet light transmitting window.

しかしながら、このようなメモリモジュールにおいては
、大きなパッケージ全体を紫外a透過窓を有する特殊な
構造のものにしなければならないため、コストが高くな
るという問題があった。
However, in such a memory module, the entire large package must have a special structure having an ultraviolet a-transmitting window, resulting in an increase in cost.

また、EPROMのペアチップでは、書込みおよび消去
の性能を完全に保証することが難しいため、製品全体の
歩留りが悪く山彦が難しいという問題があった。
In addition, with EPROM pair chips, it is difficult to completely guarantee writing and erasing performance, so there is a problem that the yield of the entire product is poor and Yamahiko is difficult to manufacture.

さらにペアチップは、その表面にごみが付着して消去不
良を生じるおそれがあるため、チップの搭載およびパッ
ケージの組立の際の清浄度をより一層高くしなければな
らないという問題があった。
Furthermore, since there is a risk that dust may adhere to the surface of paired chips and cause erase failure, there is a problem in that the level of cleanliness must be even higher when mounting the chips and assembling the package.

C発明の目的コ 本発明はこれらの問題を解消するためになされたもので
、紫外線消去型EPROMを実装し高品質で実装密度の
高いメモリモジュールを提供することを目的とする。
CObject of the Invention The present invention has been made to solve these problems, and an object of the present invention is to provide a high-quality memory module with a high packaging density in which an ultraviolet erasable EPROM is mounted.

[発明の概要] すなわち本発明のメモリモジュールは、紫外線透過窓を
有する紫外a消去型EPROMのフラットパッケージと
、これとほぼ同サイズの他のメモリ素子のフラットパッ
ケージあるいはメモリ素子搭載基板とを前記EPROM
のフラットパッケージが最外側で紫外線透過窓が外側に
露出するようにv4重し、これらの各リードを対向配置
された一対の回路基板のスルーホールにそれぞれ挿入し
各回路基板上の導体パターンと電気的に接続してなるこ
とを特徴としている。
[Summary of the Invention] That is, the memory module of the present invention includes a flat package of an ultraviolet-a erase type EPROM having an ultraviolet-transmitting window, and a flat package of another memory element or a memory element mounting board of approximately the same size as the EPROM.
The flat packages are stacked one on top of the other so that the ultraviolet transmitting window is exposed on the outermost side, and each lead is inserted into the through hole of a pair of circuit boards placed opposite each other to connect the conductor pattern and electricity on each circuit board. It is characterized by being connected to each other.

[発明の実施例] 以下凹面に基づいて本発明の詳細な説明Jる。[Embodiments of the invention] The detailed description of the present invention will be given below based on concave surfaces.

第1図は本発明の一実施例のメモリモジュールの部分断
面図である。
FIG. 1 is a partial sectional view of a memory module according to an embodiment of the present invention.

図において符号1はガラスからなる紫外線透過窓2が上
面に設けられた紫外線消去型EPROMのフラットパッ
ケージを°示しており、その下側には、このフラットパ
ッケージと同一形状でリード間の幅寸法の等しい3個の
スタティックRAMのフラットパッケージ3が積み重ね
られて配置されている。
In the figure, reference numeral 1 indicates a flat package of an ultraviolet erasable EPROM, which has an ultraviolet transmitting window 2 made of glass on its upper surface. Three equal static RAM flat packages 3 are stacked and arranged.

これらの紫外線消去型EPRO〜1のフラットパッケー
ジ1およびスタティックRAMのフラットパッケージ3
は、それぞれのり−ド1a、3aがこれらを挾んで対向
配置された一対の回路基板4.5のスルホール4a 、
5aにそれぞれ挿入され、半田6により回路基板4.5
の導体パターン(図示を省略)に電気的に接続されてい
る。
Flat package 1 of these ultraviolet erase type EPRO~1 and flat package 3 of static RAM
are the through-holes 4a of a pair of circuit boards 4.5, which are arranged opposite to each other with the glues 1a and 3a sandwiching them, respectively;
5a respectively, and are connected to the circuit board 4.5 by soldering 6.
It is electrically connected to a conductor pattern (not shown).

また、回路基板4.5の下縁端にはD(P型の複数個の
リード7が突設されている。これらのリード7はそれぞ
れ回路基板4.5上の導体パターンに電気的に接続され
ており、このモジュールをマザーボードとなる他の回路
基板に電気的に接続させる。
Further, a plurality of D (P type) leads 7 are protruded from the lower edge of the circuit board 4.5.These leads 7 are electrically connected to the conductive patterns on the circuit board 4.5. This module is electrically connected to another circuit board, which becomes the motherboard.

このように構成される実施例のメモリモジュールにおい
ては、完全に封止され品質°の保証された紫外線消去型
EPROMのフラットパッケージ1が使用され、これが
スタティクRAMのフラットパッケージ3とともに積重
されて実装されているので、EPROMの紫外線消去を
簡単に行なうことができ、しかも高い実装密度を得るこ
とができる。
In the memory module of the embodiment configured in this manner, a flat package 1 of ultraviolet erasable EPROM which is completely sealed and whose quality is guaranteed is used, and this is stacked together with a flat package 3 of static RAM for mounting. Therefore, the EPROM can be easily erased by ultraviolet rays, and high packaging density can be obtained.

すなわち、第1図に示す実施例において、例えば紫外線
消去型EPROMおよびスタティックRAMの各メモリ
容量を64にビット、各メモリ構成を8にバイトとした
とき、これらのフラットパッケージは一般にリードピッ
チが1.27aでパッケージ厚が2〜3uであるので、
全体の厚さが10〜15+nと極めて薄く、幅寸法も標
準のJEDECの28ビンDIRに近い極めて高密度の
メモリモジュールが得られる。
That is, in the embodiment shown in FIG. 1, if the memory capacity of each of the ultraviolet erasable EPROM and static RAM is 64 bits and each memory configuration is 8 bytes, these flat packages generally have a lead pitch of 1. Since the package thickness is 27a and 2~3u,
An extremely high-density memory module with an extremely thin overall thickness of 10 to 15+n and a width close to the standard JEDEC 28-bin DIR can be obtained.

第2因は、本発明の他の実施例のメモリモジュールの断
面図である。なお第2図において、第1因と共通する部
分には同一符号が付しである。
The second factor is a cross-sectional view of a memory module according to another embodiment of the present invention. In FIG. 2, the same reference numerals are given to the parts common to the first factor.

この実施例においては、紫外線消去型EPR(5Mのフ
ラットパッケージ1およびスタティックRAMのフラッ
トパッケージ3とともにこれらと形状および幅寸法の°
異なるフラットパッケージ型■C8が以下のようにして
実装されている。
In this embodiment, an ultraviolet erasable EPR (5M flat package 1 and static RAM flat package 3) is used, as well as a
A different flat package type ■C8 is implemented as follows.

すなわち、このフラットパッケージ型IC8は、別の回
路基板9上に平面実装されており、この搭fIR回路基
板は、その回路基板9に設けられたスルーホール9aに
、対向配置された回路基板4.5下端のリード7が挿入
され半田6により同容されることによりモジュールに組
込まれている。
That is, this flat package type IC 8 is planarly mounted on another circuit board 9, and this IR circuit board has a through hole 9a provided in the circuit board 9, and a circuit board 4. The lead 7 at the lower end of the module 5 is inserted and held together by the solder 6, thereby being incorporated into the module.

なお、本発明においては、別の回路基板上に、フラット
パッケージ型1Cばかりでなく他のチップ部品や抵抗、
コンデンサ等も平面実装し、これを第2図に示した実施
例と同様にしてモジュールに組込むことも可能である。
In addition, in the present invention, not only the flat package type 1C but also other chip components, resistors,
It is also possible to planarly mount capacitors and the like and incorporate them into the module in the same manner as the embodiment shown in FIG.

[発明の効果1 以上説明したように、本発明めメモリモジュールにおい
ては、品質が保証され完全に封止された紫外線消去型E
PROMのフラットパッケージが他のメモリ素子のフラ
ットパッケージ等と梢単されて実装されているので、実
装密度が高く、しかも製造の際の歩留りが高゛く製造コ
ストも低くおさえることができる。また、最外側に紫外
線消去型EPROMのフラットパッケージの紫外線透過
窓が位置するように配置されているので、EPROMの
紫外線消去も容易に行なうことができる。
[Effects of the Invention 1] As explained above, the memory module of the present invention has an ultraviolet erasable type E which has guaranteed quality and is completely sealed.
Since the PROM flat package is mounted on top of other memory element flat packages, the packaging density is high, and the manufacturing yield is high and manufacturing costs can be kept low. Furthermore, since the ultraviolet transmitting window of the flat package of the ultraviolet erasable EPROM is located at the outermost side, the EPROM can be easily erased with ultraviolet light.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の部分断面図、第2図は別の
実施例の部分断面図である。 1・・・・・・・・・・・・・・・紫外線消去型EPR
OMのフラットパッケージ 2・・・・・・・・・・・・・・・紫外線透過窓3・・
・・・・・・・・・・・・・スタティックRAMのフラ
ットパッケージ 4.5.9・・・回路基板 6・・・・・・・・・・・・・・・半 田7・・・・・
・・・・・・・・・・リード8・・・・・・・・・・・
・・・・フラットパッケージ型IC第1図 第2図
FIG. 1 is a partial sectional view of one embodiment of the present invention, and FIG. 2 is a partial sectional view of another embodiment. 1・・・・・・・・・・・・・・・Ultraviolet erasing type EPR
OM flat package 2・・・・・・・・・・・・Ultraviolet transmission window 3・・・・
..........Static RAM flat package 4.5.9...Circuit board 6...Solder 7...・・・
・・・・・・・・・Lead 8・・・・・・・・・・・・
...Flat package type IC Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)紫外線透過窓を有する紫外線消去型EPROMの
フラットパッケージと、これとほぼ同サイズの他のメモ
リ素子のフラットパッケージあるいはメモリ素子搭載基
板とを前記EPROMのフラットパッケージが最外側で
紫外線透過窓が外側に露出するように積重し、これらの
各リードを対向配置された一対の回路基板のスルーホー
ルにそれぞれ挿入し各回路基板上の導体パターンと電気
的に接続してなることを特徴とするメモリモジュール。
(1) A flat package of an ultraviolet erasable EPROM having an ultraviolet transmitting window and a flat package of another memory element of approximately the same size or a memory element mounting board are arranged so that the flat package of the EPROM is the outermost part and the ultraviolet transmitting window is The leads are stacked so as to be exposed to the outside, and each lead is inserted into a through hole of a pair of circuit boards arranged opposite each other, and electrically connected to a conductor pattern on each circuit board. memory module.
JP59185042A 1984-09-04 1984-09-04 Memory module Pending JPS6163048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59185042A JPS6163048A (en) 1984-09-04 1984-09-04 Memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185042A JPS6163048A (en) 1984-09-04 1984-09-04 Memory module

Publications (1)

Publication Number Publication Date
JPS6163048A true JPS6163048A (en) 1986-04-01

Family

ID=16163775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59185042A Pending JPS6163048A (en) 1984-09-04 1984-09-04 Memory module

Country Status (1)

Country Link
JP (1) JPS6163048A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988008203A1 (en) * 1987-04-17 1988-10-20 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
JPH02260448A (en) * 1989-03-30 1990-10-23 Mitsubishi Electric Corp Semiconductor device and radiating fin
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
KR20010086476A (en) * 2001-07-13 2001-09-13 신이술 Printed circuit board and package method of stacking semiconductor using therof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988008203A1 (en) * 1987-04-17 1988-10-20 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
JPH02260448A (en) * 1989-03-30 1990-10-23 Mitsubishi Electric Corp Semiconductor device and radiating fin
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
USRE36916E (en) * 1995-03-21 2000-10-17 Simple Technology Incorporated Apparatus for stacking semiconductor chips
KR20010086476A (en) * 2001-07-13 2001-09-13 신이술 Printed circuit board and package method of stacking semiconductor using therof

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