JP3123338B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device on which semiconductor IC chips and electronic components are mounted at high density.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller,
High integration and high density mounting are required for the integrated memory circuits used therein. Semiconductor integrated circuit devices that integrate semiconductor IC chips and electronic components are currently
Used in various electronic circuit devices. In a conventional semiconductor integrated circuit device, an IC chip having a plastic package structure formed by resin molding is planarly mounted on a printed wiring board (hereinafter, referred to as a “wiring board”). The connection between each IC chip and the wiring board is often made by soldering.

[0003]

However, the conventional planar mounting type integrated memory circuit has the following problems.

(1) With the improvement of CPU performance,
It is necessary to increase the memory capacity of the main storage circuit. In order to double the memory capacity by using memory ICs having the same performance, the number of memory ICs used is also doubled. However, in the case of a conventional planar mounting type integrated memory circuit, the wiring required for mounting is required. The substrate area also doubles or more at the same time. As a result, downsizing of the electronic circuit device including the integrated memory circuit does not progress.

(2) The enlargement of the wiring board area as in the above (1) causes an increase in the cost of the integrated memory device because the unit price per wiring board area is high. Further, since the length of the wiring on the wiring board becomes longer, the wiring impedance increases. As a result, problems such as deterioration of transmission characteristics such as deformation of a signal waveform and deterioration of response characteristics to a high-frequency signal occur.

(3) The use of a memory IC having a smaller package area by narrowing the terminal intervals to a small pitch can suppress an increase in the wiring board area required for mounting to a certain extent. However, the conventional mounting technology cannot be used for the memory IC having the narrow terminal pitch, and a new problem that the mounting technology needs to be advanced occurs.

In order to overcome the above-mentioned problems of the conventional planar mounting type integrated memory circuit, a multi-layer integrated memory circuit in which a plurality of memory IC chips are stacked in multiple layers and mounted is disclosed in No. 5,144,427 and U.S. Pat. No. 4,982,265. In these multi-layer integrated memory circuits, a lead terminal (hereinafter, referred to as a “selection terminal”) to which a signal for selectively accessing one of the memory IC chips of each layer is input has a terminal shape for each layer. And different positions, and each is independently connected to the wiring board. On the other hand, a terminal (hereinafter, referred to as a “common terminal”) to which a signal having the same function is input to a memory IC chip of each layer, such as a power terminal and a ground terminal,
They are connected to each other by soldering or the like and connected to the same pad on the wiring board.

However, the conventional multi-level integrated memory circuit having the above-described lead terminal connection structure has the following problems.

(1) As for the common terminal, the lead terminal of the memory IC chip of each layer is directly soldered.
The mechanical strength of the connection is not sufficient. In addition, since a sufficient connection area cannot be secured, it may become electrically unstable in terms of contact resistance and the like.

(2) Since all the common terminals of the memory IC chips of each layer are soldered together, if the memory IC chip of any layer has a defect and a repair operation is required, the repair target is one. Even if it is a hierarchy, all the hierarchies must be removed once.

Japanese Patent Laying-Open No. 4-26152 discloses a multi-level integrated memory circuit having different shapes for the purpose of solving the above problems. In this multi-layer integrated memory circuit, the terminals of each IC are formed at different positions so that the lead terminals of the respective memory ICs to be multi-layered do not overlap. That is, by providing the lead terminals only in a part of the outer periphery of each IC, even if the layers are multi-layered, all the terminals can be independently connected to the wiring board without overlapping the lead terminals of each layer.
With such a structure, it is possible to remove only the memory IC of a certain specific hierarchy, and the efficiency of the repair work is improved.

However, in this structure, unless the terminal interval is narrowed, the number of terminals of each IC must be smaller than that of the conventional IC, and there is a case where the function is restricted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. (1) High-density mounting by multi-layering, (2) Signal transmission characteristics and high-frequency characteristics (3) the repair work efficiency due to the failure or failure of the mounted semiconductor element is improved, and (4) the bit width of the input / output data signal can be easily selected. It is an object to provide an integrated circuit device.

[0014]

In order to solve the above problems, an integrated circuit device according to the present invention comprises a module having the same structure.
Multiple module units stacked vertically
An integrated circuit device mounted on a board, wherein the
Joule is a board on which a plurality of semiconductor elements are mounted,
Two leads provided along opposite outer perimeters of the substrate
A terminal row, and one of the lead terminal rows is the semiconductor element.
From a non-connect terminal that has no signal assigned to
And the other row of lead terminals is connected to the semiconductor element.
If it consists of signal assignment terminals with signal assignment
The lead end on the non-connect terminal side of the lower module
Child row and lead terminal row on the signal assignment terminal side of the upper module
The upper module is connected to the lower module so that
The configuration is such that it is arranged to be rotated by 180 ° with respect to the joule .

[0015]

With this configuration, the electronic circuit device can be mounted only by inserting and connecting the card edge connector attached to the motherboard, and the soldering step is not required.

A module unit to be mounted on an electronic circuit device having a limited area can be stacked in accordance with the circuit scale, so that high-density mounting can be realized.
Deterioration of signal transmission characteristics due to long wiring length,
The high frequency characteristics do not deteriorate.

[0017]

The present invention will be described below with reference to examples. In the following description, the present invention is applied to a memory circuit, and the multi-layer semiconductor integrated circuit device of the present invention will be described as a multi-layer integrated memory circuit.

Embodiment 1 FIG. 1 is a perspective view of a module board 8 on which a multi-level integrated memory circuit according to a first embodiment of the present invention is mounted.

In the integrated memory circuit of the present invention, high integration and high-density mounting of the circuit are realized by using a module having a plurality of semiconductor elements. Specifically, two modules are prepared, one of which is a first module 3 and the other is a second module 4. Then, the first module 3 is stacked on the second module 4 to form the module unit 2. In the example of FIG.
Nine module units 2 consist of copper-clad laminated wiring board 1
(Hereinafter, referred to as a “wiring board”) to constitute a module board 8. The size of the module board 8 is typically 107.95 mm × 24.5 mm
It is. Also, the first and second modules 3 and 4
Is typically 11 mm × 16 mm.

A gull-wing type lead terminal 6 is formed on the second module 4 and is electrically connected to the wiring board 1. Further, the first module 3 is formed with a square lead terminal 5 having a U-shape, and is electrically connected to the gull-wing lead terminal of the second module 4. Thereby, both the first and second modules 3 and 4 are electrically connected to the wiring board 1. As described later in detail, the first and second modules 3 and 4 have the same structure except that the shape of the lead terminal is a gull-wing type or a square type. I have.

By making the lead terminals of the first module 3 mounted on the upper layer of the multi-layer structure square, the multi-layer integrated memory circuit of the present invention has a sufficient connection area between the lead terminals of each module. Can be secured. Thereby, the mechanical strength and electrical stability of the connection part of the lead terminal can be ensured. Further, when it is desired to increase the connection area between the lead terminals, it can be easily realized only by a simple design change.

The module board 8 preferably has a male connector 7 of a card edge connector. Each module board 8 has such a male connector 7 of a card edge connector, and an electronic device to which these module boards 8 are to be mounted is provided with a motherboard provided with a large number of female connectors of the corresponding card edge connector. If provided, the memory capacity can be easily increased or decreased only by inserting and removing the card edge connector.

In the example shown in FIG. 1, the rows of the gull-wing type lead terminals 6 and the square type lead terminals 5 of each module unit 2 are arranged so as to be parallel to the terminal rows of the male connection part 7 of the card edge connector. are doing. However, it is not limited to such a direction.

Next, referring to FIG. 2, first and second modules 3 and 4 (hereinafter collectively referred to as “module 1
0 ”) will be described.

Each module 10 has a module substrate 11 as a wiring substrate in a quadrangular insulating frame 16. A plurality of memory IC chips 12 and a plurality of surface mount chip capacitors 13 (hereinafter, referred to as “chip capacitors”) are mounted on the module substrate 11.

The electrical connection between the mounted memory IC chip 12 and chip capacitor 13 and the external circuit is as follows.
Lead terminal row 1 in which a plurality of lead terminals 14 are arranged in parallel
5 is performed. The lead terminal row 15 extends through the frame 16 on the outer periphery of the module 16 opposite to the frame 16.
0 is formed so as to protrude inside and outside.
Each lead terminal 14 is held by a frame 16. Of the lead terminals 14, the portion protruding inside the frame 16 is the inner lead 14a, and the portion protruding outside the frame 16 is the outer lead 14b.

As described above, the first module 3 and the second module 4 differ only in the shape of the lead terminal row 15. That is, in the first module 3, the lead terminal row 15 is formed in a square shape, while in the second module 4, the lead terminal row 15 is formed in a gull wing type.

In the memory IC chip 12, for example, a bump is formed on an electrode pad (not shown) on the memory IC chip 12, and the bump and a wiring pattern (not shown) of the module substrate 11 are face-down bonded. Implemented by: Alternatively, the memory IC chip 1
2 is die-bonded to the module substrate 11 so that the electrode pads on the memory IC chip 12 and the module substrate 11
May be connected by wire bonding.

In the embodiment shown in FIG. 2, the memory IC chips 12 are arranged such that the long sides and short sides of the chips adjacent to each other are adjacent to each other, and are mounted in a square area on the module substrate 11. Have been. The four chip capacitors 13 are mounted in a similar arrangement in a square area generated in the central portion of the memory IC chip 12 arranged as described above. Each of these chip capacitors 13 is connected between a power supply line connected to each memory IC chip 12 and a ground line. By arranging and mounting the memory IC chip 12 and the chip capacitor 13 on the module 10 as described above, high-density mounting that saves a mounting space becomes possible.

Next, the circuit of the module 10 will be described with reference to FIG. In the present embodiment, four 4Mbi as four memory IC chips mounted on the module 10
t DRAMs 120 to 123 (hereinafter, “DRAM # 0 to DRAM # 0”
# 3 "). Therefore, one module 10 has a total storage capacity of 16 Mbit.

Address buses (A0 to A10) 21 for supplying address signals to these DRAMs # 0 to # 3
And a / WE signal line 28 for supplying a data write signal (write enable signal) is commonly connected. Although not shown in FIG. 3, a power supply line and a ground line are commonly connected to each of the DRAMs # 0 to # 3.
Further, the chip capacitor 13 shown in FIGS.
(Not shown in FIG. 3) is connected between the power supply line and the ground line for the purpose of surge absorption or the like.

As a line for supplying a column address strobe signal, / RA connected to DRAMs # 0 and # 1
There is a S0 line 22 and a / RAS1 line 23 connected to DRAMs # 2 and # 3. Applying a row address strobe signal to each DRAM / CAS0- / CA
S3 lines 24 to 27 and data buses (D0 to D3) 29 to 32 for inputting / outputting data from / to each DRAM are
One DRAM is connected to each of the DRAMs # 0 to # 3. It should be noted that data is input / output one bit at a time from each of the data buses (D0 to D3) 29 to 32.

Module 1 having such a circuit configuration
At 0, the column and row address strobe signal lines (/
RAS0, / RAS1, and / CAS0 to / CAS3) are appropriately combined to input a signal, so that the bit width of input / output data can be set in units of 1 bit, 2 bits, and 4 bits.
It can be set in bit units.

For example, all column and row address strobe signal lines (/ RAS0, / RAS1, / CAS)
0 // CAS3) without short-circuiting and providing independent signals to each other, the data buses D0-D0 in the DRAMs # 0- # 3
Data is input / output from D3 in 1-bit units. on the other hand,
If all the / CAS0 to / CAS3 signal lines are short-circuited outside the module 10 and the / RAS0 and / RAS1 signal lines are kept independent, the combination of the data buses D0 and D1 and the combination of D2 and D3 can be used as a unit. And 2b
Data can be input and output in it units. further,
/ RAS0, / RAS1 and / CAS0 // CAS3
When all the signal lines are short-circuited outside the module, data is input / output in units of 4 bits in units of combinations of the data buses D0 to D3.

Next, with reference to FIG. 4, a method of allocating signals of the lead terminal array 15 of the module 10 will be described.

As described above, each module 10
Are two lead terminal rows 15a along the opposite outer periphery.
And 15b. One of the terminals, for example, the terminal of the lead terminal row 15b on the left side in FIG. 4 is configured by a non-connect terminal (hereinafter, referred to as an “NC terminal”) to which signals of circuits constituting the module 10 are not allocated. . A signal is actually assigned to each terminal of the other lead terminal row 15a. The assignment is performed, for example, in order from one end to the other end, a ground line terminal 20a, an address bus (A0 to A10) terminal 21a, and a column address strobe signal line (/ RAS0 and / RAS1) terminal 22.
And 23, row address strobe signal lines (/ CA
S0 / CAS3) terminals 24a-27a, write enable signal line (/ WE) terminal 28a, data bus (D
0 to D3) terminals 29a to 32a and a power supply line terminal 33a.

In actual mounting, the lead terminal row 1
Two modules 10 having the same structure in which signals are allocated to 5a and 15b as described above are prepared. One of the two modules includes lead terminal rows 15a and 15a.
b is formed into a square shape to obtain a first module 3. In the other module, the lead terminal rows 15a and 15b are formed into a gull-wing type to form a second module 4.

Then, the first module 3 is turned 180 degrees so that the terminal row 15a on the signal allocation side of the first module 3 is arranged on the lead terminal row 15b on the NC terminal side of the second module 4. Rotate °. In this manner, the first and second modules 3 and 4 are stacked, and the respective lead terminals at opposing positions in the lead terminal rows 15a and 15b are connected to each other by soldering, so that the module unit 2 shown in FIG. To form The module unit 2 is thereafter mounted on the wiring board 1.

As described above, in the module 10 used in the present embodiment, the column and row address strobe signal lines (/ RAS0, / RAS1, / CAS0 // CAS0) are used.
CAS3) are appropriately short-circuited and combined, and a signal is input to each combination, so that the bit width of the input / output data can be set in units of 1 bit, 2 bits, or 4 bits. If the signal line is similarly short-circuited to the module unit 2 formed by laminating two modules 10, data can be input / output in units of 1 to 8 bits.

For example, in order to input / output data in 1-bit units, the first and second modules 3 and 4
All of the / RAS signal line terminals and / CAS signal line terminals may be made independent to provide independent signals.

In order to input / output data in units of 2 bits, the corresponding address bus (A0 to A10) terminals of the first and second modules 3 and 4 (for example, the A0 bus of the first module 3) The terminal and the A0 bus terminal of the second module 4 are short-circuited outside the module 10, and the other terminals are handled independently. In this case, a combination constituted by the corresponding bus lines of the first module 3 and the second module 4 (for example, both D0 buses) is a data input / output unit. On the other hand, even if the / CAS signal line terminal of the first module 3 is short-circuited outside the module, the / CAS signal line terminal of the second module 4 is short-circuited outside the module, and the other terminals are handled independently, Input / output of data in units of 2 bits becomes possible. In this case, the combination of the D0 bus and the D1 bus of the first module 3, the D2 bus and the D3 bus, the D0 bus and the D1 bus of the second module 4, and the D2 bus and the D3 bus are data input / output. Unit.

To input and output data in 4-bit units, the following terminals are connected. The corresponding address buses (A0-A) of the first and second modules 3 and 4
10) The terminals (for example, the A0 bus terminal of the first module 3 and the A0 bus terminal of the second module 4) are short-circuited outside the module 10 and the / CAS signal line terminal group of the first module 3 ,and/
The RAS signal line terminal group, the / CAS signal line terminal group of the second module 4 and the / RAS signal line terminal group are short-circuited outside the module for each group. Then, an independent signal may be given to each group. In this case, the combination of the D0 to D3 buses of the first module 3 and the combination of the D0 to D3 buses of the second module 4 are data input / output units.

Alternatively, the first and second modules 3
And 4 corresponding address bus (A0 to A10) terminals are short-circuited outside the module 10, respectively, and the / CAS signal line terminal group of the first module 3 and the / CAS signal line terminal group of the second module 4 are shorted. May be short-circuited for each group, and the remaining terminals may be handled independently. Thereby, the D of the first module 3
Data can be input / output in units of 4 bits by using a combination of four buses of 0 and D1 and D0 and D1 of the second module 4, and a combination of the remaining four buses as units.

Further, in order to input / output data in units of 8 bits, the corresponding terminals of the address buses A0 to A10 of the first and second modules 3 and 4 are short-circuited outside the respective modules, and the first The / CAS signal line terminal group of the module 3, the / CAS signal line terminal group of the second module 4, and all the / RAS signal line terminal groups of the first and second modules 3 and 4, Short circuit outside of module. If an independent signal is given to each group, a combination of 8 bits composed of eight terminals of all data buses of the first and second modules 3 and 4 is a unit of data input / output.

Next, a peripheral circuit of the lead terminal array 15 of the module unit 2 will be described with reference to FIG. FIG.
FIG. 3 is a circuit diagram when wiring is performed so that data can be input and output in units of 8 bits.

The module unit 2 shown in FIG.
This is configured by laminating a first module 3 and a second module 4 having the structure, circuit, and lead terminal arrangement described in FIGS. As already explained,
The first and second modules 3 and 4 each have 1
Since it has a storage capacity of 6 Mbits, the module unit 2 as a whole has a storage capacity of 32 bits in total.

As described with reference to FIG. 3, each of the modules 3 and 4 has address buses A0 to A10, data buses D0 to D3, and / WE, / RAS0, / RAS.
The signal lines RAS1 and / CAS0 to / CAS3 are connected.

The address bus 36, the / WE signal line 43, and the / CAS signal lines 39-42
Are short-circuited outside the module unit 2 and are wired so as to give the same signal to the opposite terminals of the first and second modules 3 and 4, respectively. Also, two / RAS signal lines of the first module 3,
And the two / RAS signal lines of the second module 4 are each short-circuited outside the module unit 2,
Applying one / RAS signal to the first module 3 / R
1 for AS0m signal line 37 and second module 4
/ RAS1m signal line 38 which provides one / RAS signal
Is composed.

On the other hand, as for the data bus, 4-bit data buses 44 and 45 each composed of data buses D0 to D3 are formed for each of the first module 3 and the second module 4. Furthermore, a data bus 46 having an 8-bit width of Du0 to Du7 is configured by putting them together.

FIG. 5 does not show the wiring patterns of the power supply line and the ground line.

In this circuit, each bus and line 36 to
By giving each independent signal to 42, 8b
Data is input and output in 8-bit units from the data bus 46 having an it width.

Next, a circuit diagram of a memory block 160 composed of a plurality of module units 2 and other modules will be described with reference to FIG.

The memory block 160 shown in FIG. 6 has four module units (# 0 to # 3) 480 to 483,
It has an extra module 47 independent of the module unit and a driver module 63. Of these, the extra module 47 has the circuit configuration described with reference to FIG. 3, is equipped with a total of four 4 Mbit DRAMs, and has a total storage capacity of 16 Mbit.

On the other hand, four module units (# 0 to # 0)
# 3) As described with reference to FIG. 5, each of the terminals 480 to 483 is connected such that data input / output is performed in units of 8 bits. Each of the module units (# 0 to # 3) 480 to 483 is also shown in FIG.
As described with reference to, the storage capacity is 32 Mbit in total. Each module unit (# 0 to # 3) 480
Buses and lines (A0 to A
10, / WE, / RAS0m, / RAS1m, / CAS
0 // CAS3) have functions equivalent to those of the buses and lines described with reference to FIG. Further, the data buses Du0 to Du7 connected to the respective module units (# 0 to # 3) 480 to 483 are, as described with reference to FIG.
It is configured to input and output data in bit units.

These module units (# 0 to #
3) Wiring to 480-483 and extra module 47 is described as follows.

The address bus 49 is commonly connected to all the module units (# 0 to # 3) 480 to 483 and the extra module 47. Similarly, /
The WE signal line 56 is also commonly connected to all the module units (# 0 to # 3) 480 to 483 and the extra module 47. Therefore, the address signal and / WE signal are commonly applied to all memory IC chips included in memory block 160.

The / RAS signal line and the / CAS signal line are connected to the module units (# 0 to # 3) 480 to 4
It is selectively shorted to selectively provide a signal to some of the 83 and extra modules 47.

For example, module units # 0 and #
2 and the / RAS0 signal line of the extra module 47 are all short-circuited to one signal line (RA
S0) 50. Similarly, all the remaining / RAS signal line terminals are short-circuited to form another signal line (RAS1) 51.

Further, all the / CAS signal line terminals of the module unit # 0 and the / CAS0 signal line terminal of the extra module 47 are short-circuited into one signal line (CAS0) 52. ing. Similarly, all / C of module unit # 1
AS signal terminal and / CAS1 of extra module 47
Signal line terminals, all / CAS of module unit # 2
/ CAS of signal line terminal and extra module 47
2 signal line terminals, all / CAS signal line terminals of module unit # 3 and extra module 47
/ CAS3 signal line terminals are short-circuited to separate lines (CAS1, CAS2, CAS3) 53-
It is 55.

On the other hand, the data bus is composed of 8-bit buses 57 to 60 composed of data buses Du0 to Du7 of the respective module units # 0 to # 3, and data buses D0 to D3 of the extra module 47. 4 bit unit buses 61 are bundled, and Db0 to Db
The data bus 62 of 36 bits of b35 is obtained.

The memory block 160 in FIG. 6 further has a driver module 63. This driver module 63 includes first and second driver IC chips 64 and 6 for driving 11 signals in a non-inverting manner.
5 and a sub-memory IC chip 74 are mounted. The sub memory IC chip 74 includes the memory block 16
0 is provided for the purpose of replacing the function of the defective IC when any one of the memory IC chips existing in the memory IC 0 is defective or has a failure and needs to be replaced. , Which will be described later in detail).

The driver module 63 has a gull-wing type lead terminal like the second module described with reference to FIG. On the other hand, the extra module 47 described above has square lead terminals like the first module. When mounting the driver module 63 and the extra module 47, the extra module 47 corresponding to the first module is stacked on the driver module 63 corresponding to the second module. Thereby, other module units 480-4
Like 83, it is unitized and mounted on a wiring board.

As the first and second driver IC chips 64 and 65 included in the driver module 63,
In this embodiment, SN74ABT5400 manufactured by Texas Instruments Japan Limited is used. However, the present invention is not limited to this type of IC, and may be replaced with another driver IC as long as it has an equivalent function.

Address signals A0 to A10 are input from an input line 66 of the first driver IC chip 64. The first driver IC chip 64 outputs address signals A0 to A10 to an address bus 49 connected to each of the module units # 0 to # 3. On the other hand, the / RAS signal, the / CAS signal, and the / WE signal line are input to seven input lines 67 to 73 among the input lines of the second driver IC chip 65, and the corresponding seven output terminals are: / RAS0 signal line 50, / RAS1 signal line 51, / CAS0 // CAS3 signal lines 52-55
And / WE signal 56.

By connecting the wirings in this manner, the signal waveform of each signal line input to the memory block 160 is refresh-shaped by the first and second driver IC chips 64 and 65 prior to the input. At the same time, each signal waveform is re-energized
As a result, the driving capability is reproduced, and the device can be connected to and driven by a large number of memory chips. Therefore, it is possible to supply a good signal without deteriorating the transmission capability to many memory IC chips mounted in the memory block 160.

FIG. 6 does not show the wiring patterns of the power supply line and the ground line. Also, a chip capacitor connected between the power supply line and the ground line is not shown.

The memory block 1 configured as described above
At 60, the / RA of the second driver IC chip 65
Data input / output is performed in units of 9 bits, 18 bits, and 32 bits by selectively shorting some of the S signal and / CAS signal input lines and providing a signal to each group as a group to which the same signal is input. It becomes possible. For example, a combination of the RAS0 signal input line 67 and the CAS0 signal input line 69,
0 signal input line 67, CAS0 signal input line 69, and CAS1 signal input line 70, or R
If the AS0 and RAS1 signal input lines 67 and 68 are combined with all the CAS signal input lines 69 to 72, the data width of the input / output data is 9 bits and 18 bits, respectively.
bit, 32 bit unit.

Next, with reference to FIG. 7, the signal assignment of the lead terminal array of the driver module 63 will be described.

The terminal arrangement of the driver module 63 is basically the same as the terminal arrangement of the general module 10 described with reference to FIG. That is, in FIG. 7, one lead terminal row 115a has the same terminal arrangement as 15a described in FIG. On the other hand, input lines to the driver module 63 are arranged in order in the other lead terminal row 115b, which is an NC terminal in FIG. Specifically, the power supply line terminal 165c, the terminal 66c of the address bus 66, the terminals 67c and 68c of the / RAS signal lines 67 and 68, the terminals 69c to 72c of the / CAS signal lines 69 to 72, the NC terminal (one), Sub memory I
Terminal 75c of data bus (Dn) 75 of C chip, NC
The terminals (two) and the ground line 76c are arranged in this order.

Further, an extra module 47 is stacked on the driver module 63. In that case, the driver modules 63 having the same terminal arrangement
And the terminal row 15a of the extra module 47, and the other terminal row 115a of the driver module 63 and the NC terminal row 15b of the extra module 47 are stacked. Each terminal row 1
The terminals at the corresponding positions of 5a, 15b, 115a and 115b are electrically connected by soldering or the like. Thereby, each output line 49-56 of the driver module 47 can be provided without adding an external line.
Connection is completed.

The extra module 4 at a position corresponding to each input line terminal of the driver module 63
7 are NC terminals, so that the input signal to the driver module 63 does not affect the extra module 47 at all. Therefore, there is no need to design and manufacture a module for stacking on the driver module 63, and the general first module 3 may be stacked as it is.

Next, the sub memory IC chip 74 will be described. The sub memory IC chip 74 is a 4 Mbit DRAM of the same type as the memory IC chip used in each module unit, and is similar to the one described so far with reference to FIGS. Each bus and signal line are connected. The wiring is the same as the wiring of each of the module units # 0 to # 3 in the memory block 160 described with reference to FIG. That is, the address bus (A0 to A10) 49 is connected to the first driver IC.
Connected to the output of chip 64. On the other hand, the / RAS signal line and the / CAS signal line are connected to the second driver I
One of the output lines of the C chip 65 (in the example of FIG. 6,
RAS0 signal line 50 and CAS0 signal line 5
2) is connected. The / WE signal line is connected to the WE signal line 56 of the second driver IC chip 65.

On the other hand, the data bus (Dn) 75 of the sub memory IC chip 74
Each module unit # 0 to # 3 or one of the data buses 57 to 61 of the extra module 47 can be connected. For the connection, the data bus switching unit 170 sets the module unit # 0
Is provided in the vicinity of.

Referring to FIG. 8, data bus switching unit 1
The configuration and function of 70 will be described. Module unit # 0
Data bit lines Du forming the data bus 57 of
Branches 157-0 to 157-7 are provided for 0 to Du7, respectively, and are drawn into the data bus switching unit 170. On the other hand, a branch 175 is also provided in the data bus (Dn) 75 of the sub memory IC chip 74, and is similarly drawn into the data bus switching unit 170. Data bus Dn
Branch 175 is further subdivided by a data bus switching unit to form sub-branches 175-0 to 175-7.
Branch 157-0 of data bit lines Du0 to Du7
157-7 are arranged so as to face each other at a slight distance. Branch 15 of data bit lines Du0 to Du7
7-0 to 157-7 and the sub-branch 17 of the data bus Du
Semi-circular solder pads are formed at the tips of 5-0 to 175-7, respectively.

If the inspection before mounting the module or the module unit on the memory block 160 reveals that a certain memory IC chip already mounted on the module unit or the module is defective, the following procedure is taken. A defective memory IC chip can be replaced with a sub-memory IC chip.

First, the defective memory IC chip is electrically separated from the circuit. When the memory IC chip is mounted on the substrate by wire bonding, the wiring wires may be cut. If the chip is mounted by face-down bonding, the defective memory IC chip is removed.

Next, the module or module unit including the defective memory IC chip is assigned to module unit # 0 in FIG.
To be implemented. The data bus of the defective memory IC chip is the data bus (Db00 to Db3) of the memory block 160.
5) One bit of 62 bits. Therefore, the data bus switching unit 170 electrically connects the branch of the data bit bus, which should have been connected to the defective memory IC chip, to the sub-branch of the data bus of the sub memory IC chip, which is opposed thereto. I do. As a result, the defective memory I
While the C chip is electrically excluded from the circuit of the memory block 160, the sub memory IC chip 74 is incorporated in the circuit, and the replacement of the function is completed.

In the above description, the data bit line Du
Branches 157-0 to 157-7 of 0 to Du7 and a sub-branch 175-0 of the data bus Dn of the sub memory IC chip
175-7 is initially electrically isolated, and only data bit lines corresponding to defective memory IC chips are connected by soldering. However, the method of connecting them is not limited to soldering, but may be other methods obvious to those skilled in the art. Alternatively, the branches 157-0 to 157-7 of the opposing data bit lines Du0 to Du7 and the sub-branches 175-0 to 175-7 of the data bus Dn are electrically connected in advance by a wiring pattern or the like. Alternatively, the portion other than the portion where the defective memory IC chip needs to be replaced may be cut off.

Further, a plurality of data bus switching units 170 may be provided, for example, one in the vicinity of all the module units # 0 to # 3. In this case, the module unit or module including the defective memory IC chip is
This eliminates the restriction that it must be assigned to module unit # 0. Also, a plurality of sub-memory ICs
It is also possible to improve the circuit of the memory block 160 so as to include a chip to cope with a plurality of defective memory IC chips.

Sub-memory IC having the above functions
By providing the chip 74 in the memory block 160 and adopting the wiring configuration and the replacement operation for the memory IC chip as described above, the integrated memory circuit of the present embodiment improves the work efficiency of the repair work of the defective memory IC chip. I do.

Next, a module board 180 composed of two memory blocks 160 will be described with reference to FIG.

The first module board 180 has
The memory block 180a and the second memory block 180b have the same structure as the memory block 160 described with reference to FIG. 6, and each have a storage capacity of 4M words. First and second memory blocks 180a
And 180b, as in the previous example, the address lines (A0 to A10) 76
Have / WE signal lines 85, / RAS signal lines and / CAS signal lines 77 to 84, and are connected to data buses (Db00 to Db35) 86 and 87.

The data buses (Db00 to Db3)
5) 86 and 87 are the respective memory blocks 18
From 0a and 180b, data buses 86 and 87 in 35-bit units are output, and these are bundled to form a final data bus 88 in 36-bit units.
The address bus 76 and the / WE signal line 85
Correspond to the first and second memory blocks 180a and 180a.
80b are commonly connected.

On the other hand, as the / RAS signal line, the first
/ RAS connected to the / RAS0 signal line terminal and the / RAS1 signal line terminal of the memory block 180a.
There are a 0 signal line 77 and a / RAS1 signal line 78, and a / RAS2 signal line 79 and a / RAS3 signal line 80 connected to the / RAS0 and / RAS1 signal terminals of the second memory block 180b.

Further, as the / CAS signal line, the first
/ CAS0 and / CAS of memory block 180a
/ CAS0 signal line 81 which connects two signal lines by short-circuiting, and / CAS0 signal of the first memory block 180a.
/ C3 short and connect the / CAS3 signal line
The AS1 signal line 82 and the / CAS2 signal line 83 wired to the second memory block 180b in the same manner as the two / CAS signal lines 81 and 82.
And / CAS3 signal line 83.

For the module board 180 having the above-described circuit configuration, based on the same idea as before, the / RAS0 // RAS3 signal lines 77-80 and the / CAS0 // CAS3 signal lines 81-84. By appropriately short-circuiting and selectively inputting signals, the final input / output width of data from the data bus 88 can be changed.

For example, the / RAS0 signal line 77 and / C
AS0 signal line 81, / RAS0 signal line 77 and /
CAS0 signal line 81 and / CAS1 signal line 82,
Alternatively, if the / RAS0 signal line 77, the / RAS1 signal line 78, the / CAS0 signal line 81, and the / CAS1 signal line 82 are respectively combined and selectively input signals, the signals can be input in units of 9 bits, 18 bits or 36 bits. Data can be input and output.

In the description of the first embodiment of the present invention with reference to FIGS. 1 to 9, a module or a module unit is mounted on only one surface of the wiring board 1. However, mounting is performed on the other surface of the wiring board 1 in the same manner,
If both sides are used for mounting, it is possible to increase the storage capacity per area of the same wiring board or to reduce the area of the wiring board required for mounting a memory having the same storage capacity, thereby realizing higher-density mounting.

In the above description, the first and second modules having the same structure are stacked to form a module unit 2 and the module unit 2 is connected to the wiring board 1.
The module board 8 was obtained by mounting a plurality of the modules. However, since each of the modules 3 and 4 is manufactured by mounting a plurality of memory IC chips at high density, even if the modules 3 and 4 are mounted on the wiring board 1 in a single layer without being stacked. Thus, high-density mounting of the integrated memory circuit is realized.

In the above embodiments, the multi-level semiconductor integrated circuit device and the electronic circuit device of the present invention have been described by taking a memory circuit as an example. However, the present invention is not limited to the above-described memory circuit, and is similarly applicable to a semiconductor circuit device having another function such as a logical operation circuit.

[0091]

According to the present invention, a multi-layered semiconductor integrated circuit can be easily obtained by using modules having the same structure. As a result, high-density mounting and prevention of deterioration of signal transmission characteristics and high-frequency response characteristics are realized.

[Brief description of the drawings]

FIG. 1 is a perspective view of a module board having a multi-level integrated memory circuit according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a structure of a module which is a main part of the same.

FIG. 3 is a circuit diagram of a module which is a main part of the same.

FIG. 4 is a signal assignment diagram of lead terminals of a module which is a main part of the same.

FIG. 5 is a circuit diagram of a peripheral circuit connecting the module unit and an external circuit.

FIG. 6 is a circuit diagram of a memory block as a main part of the same.

FIG. 7 is a signal assignment diagram of lead terminals of a driver module, which is the main part of the same.

FIG. 8 is a diagram showing a data signal switching unit which is the main part.

FIG. 9 is a circuit diagram of a module board having two memory blocks, which are the main parts.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Module unit 3 1st module 4 2nd module 5 Square lead terminal 6 Gull wing type lead terminal 7 Male connection part of card edge connector 8, 180 Module board 10 Module 12 Memory IC chip 13 Chip capacitor 14 Lead terminal 15 Lead terminal row 47 Extra module 63 Driver module 74 Sub IC chip

Continued on the front page (72) Inventor Hideo Kurokawa 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. References JP-A-4-26152 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 25/10

Claims (12)

(57) [Claims] 1. A module having the same structure is vertically stacked.
Module units on the motherboard
Integrated circuit device, wherein the module comprises a plurality of modules.
The substrate on which the semiconductor element is mounted, and the substrate
It has two lead terminal rows provided along the outer periphery.
One of the lead terminal rows is a signal for the semiconductor element.
Consists of non-connect terminals without
Is the assignment of signals to the semiconductor elements
In addition to the signal
Of the lead terminals on the non-connect terminal side of the
Module is connected to the lead terminal row on the signal assignment terminal side.
The upper module to the lower module so that
Integrated circuit device which is arranged to rotate by 180 ° . 2. The method according to claim 1 , wherein at least one of the plurality of semiconductor elements includes:
The integrated circuit device according to claim 1, wherein the integrated circuit device is a memory element . 3. Non-connectors of upper and lower modules
The lead terminal rows on the connector terminal side and signal assignment terminal side
2. The integrated circuit device according to claim 1, wherein the integrated circuit device comprises a square terminal . 4. The non-connect terminal side of the upper module.
Are the lead terminal rows on the signal assignment terminal side square terminals?
The lower module's non-connect terminal side and
The lead terminal row on the signal assignment terminal side has a gull-wing shape.
2. The integrated circuit device according to claim 1, comprising a terminal . 5. The method according to claim 1 , wherein the number of the plurality of semiconductor elements is four,
Four semiconductor elements are adjacent to each other in a square mounting area.
The semiconductor device is arranged so that the long side and the short side
Integrated circuit device according to claim 1, wherein there. 6. At least at the center of the square mounting area
The integrated circuit device according to claim 5, wherein one or more capacitors are mounted . 7. A wiring pattern on a substrate and a plurality of semiconductor elements.
The child is electrically connected by face-down bonding.
2. The integrated circuit device according to claim 1, wherein the integrated circuit device is connected. 8. A method for forming a plurality of semiconductor elements for die bonding.
Therefore , the plurality of semiconductor elements are mounted on a substrate, and the
The wiring pattern on the board is
2. The integrated circuit device according to claim 1, wherein the integrated circuit device is connected pneumatically. 9. A tape carrier comprising a plurality of semiconductor elements.
TAB package chip processed into a package structure
Integrated circuit device according to claim 1, wherein that. 10. A card edge connector on a motherboard.
2. The integrated circuit device according to claim 1 , wherein a male connection portion is formed . 11. One of the module units is used for another module.
Driver hand re-exciting the input signal to the Joule unit
The integrated circuit device according to claim 1 , including a driver module having a stage . 12. One of the module units is connected to the other half.
A module with an alternative semiconductor device that replaces the function of a conductor device
2. The integrated circuit device according to claim 1 , further comprising a module .