JPS6155137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device that transfers data from a peripheral device to a storage device.

Conventionally, a data transfer device is comprised of a single address counter that holds the storage address of transfer data and a single length counter that holds the number of data to be transferred. In this configuration, when one data block is transferred from the peripheral device to the storage device, it is stored in a single area of the storage device, and when there are multiple data blocks, it is stored in a single area of the storage device.
Each time the data block is switched, the contents of the address counter and length counter are changed and stored in multiple areas of the storage device. Therefore,
Because it is not possible to store part or all of the same data block in multiple areas of the storage device during data transfer, a data block from a peripheral device is stored at a specific address in the storage device, and then part or all of it is stored in multiple areas of the storage device. The disadvantage is that the address must be moved to another address.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer device that eliminates the above-mentioned drawbacks.

The device of the present invention is a data transfer device that transfers data from a peripheral device to a storage device, and includes a plurality of address storage means for storing addresses of the storage device that stores transferred data; Transfer scheduled number storage means for storing the number of data bytes scheduled to be transferred from the peripheral device, counter means for counting the number of data bytes transferred from the external device, and corresponding to the address storage means, respectively. transfer start data byte number storage means for storing a predetermined number of data bytes transferred from the peripheral device to indicate the start of data transfer to the storage device; and a count result of the counting means and the start of transfer. The present invention is characterized in that it comprises comparison means for comparing the number of data bytes in the data byte number storage means, and when a match is found by the comparison means, the data is transferred to the storage device.

Next, the present invention will be explained in detail with reference to the drawings.

The first embodiment of the present invention shown in FIG. A selector 1 inputs the output of the first address counter and the output of the second address counter and selects an address to be sent to a storage device (not shown), which is transferred in correspondence with the first and second address counters. retains the number of data,
The number of data to be transferred is set when starting data transfer in correspondence with the first length counter 4 and the second length counter 5 that subtract the value "1" each time the data is transferred, and the first and second address counters. A first start register 6 and a second start register 7 A data counter 8 that adds a value "1" for each transferred data, A comparison circuit 1 that compares the value of the first start register 6 and the value of the data counter 8
0, a comparison circuit 11 that compares the value 7 of the second start register and the value of the data counter 8, a zero detector 12 that detects when the content of the first length counter 4 becomes zero, and a second length counter a zero detector 13 for detecting that the contents of the counter 5 have become zero;
A first search flip-flop 14 detects the start point of the first data transfer, and a second search flip-flop 1 detects the start point of the second data transfer.
5. AND circuits 18 and 19; first data flip-flop 16 indicating that the first data is being transferred;
a second data flip-flop 17 indicating a second data transfer width; a data register 9 storing data to be transferred to a storage device (not shown); a first data flip-flop 16; A flip-flop 17 controls the interface with the selector 1 and a storage device (not shown), and controls the timing of incrementing the first and second address counters 2 and 3 by 1, and the timing of incrementing the first and second length counters 4. And the timing of -1 at 5,
A control circuit that controls the timing of incrementing the data counter 8 by 1 and the timing of setting and resetting the first and second search flip-flops 14 and 15 and the first and second data flip-flops 16 and 17. It consists of 20.

Note that reference symbols S1 and S2 in FIG.
are activation signals for starting the operation of the first and second sides, respectively, reference symbols S3 and S4 are transfer signals indicating that data is being transferred on the first and second sides, respectively, and reference symbol S5 is a storage device ( Reference numeral S6 is a data signal sent to a storage device (not shown).

First, write address A to the first address counter 2,
Address B in the second address counter 3, N in the first length counter 4, M in the second length counter 5, logic "0" in the first start register 6, and N in the first length counter 4, logic "0" in the first start register 6, and 7 with value “c”
is set, the first and second search flip-flops 14 and 15 receive the activation signal S1.
and S2.

The data counter 8 is set to an initial value of "0". Since the first and second search flip-flops 14 and 15 are set, the first and second comparison circuits 10 and 11 are inactivated. Since the data counter 8 is logic "0", it matches the first start register 6,
The first search flip-flop is reset;
The first data flip-flop 16 is set and the first side is ready for data transfer.
At this time, when data is given to the data register 9 from the peripheral device (not shown), the first transfer signal S3 is in the logic "1" state, so the control circuit 2
0, the output of the first address counter 2 is selected from the selector 1, the contents of the first address counter 2 are sent to a storage device (not shown) as an address signal S5, and a data signal S6 is written at that address. be included. After that, the value "1" is added to the contents of the first address counter 2, the value "1" is subtracted from the contents of the first length counter 4, and the value "1" of the data counter 8 is added. . This is repeated every time data enters the data register 9, and the first zero detector 12 detects that the first register counter 4 becomes the value "0", and the first data flip-flop This will continue until you reset 16. If the value of the data counter 8 becomes "c" before the first zero detector 12 detects zero, a match is made with the second start register 7, so the second search flip-flop 15 is reset. Then, the second data flip-flop 17 is set, and the second side also becomes ready for data transfer. 1st
Since both the transfer signal S3 and the second transfer signal S4 are set, the control circuit 20 first causes the selector 1 to select the output of the first address counter 2 and transfer the first address to the storage device. Send the contents of address counter 2 as address signal S5,
The contents of the data signal S6 are written to that address.
Next, the selector 1 selects the address of the second address counter 3, sends the contents of the second address counter 3 to the storage device as a signal S5, and writes the contents of the data signal S6 at that address. In this way, the data register 9 is placed at the address indicated by the first address counter 2 and the second address counter 3.
The contents of are written. After this, the contents of the first and second address counters are each set to the value “1”.
The contents of the first and second length counters 4 and 5 are each subtracted by the value "1", and the value of the data counter is incremented by the value "1". When the content of the second length counter 5 is subtracted to the value "0", the second data flip-flop 17 is reset and the process ends. As a result,
Part or all of the same data block is stored in N storage areas from address A and M storage areas from address B of the storage device. Although this embodiment has been described with respect to only two sets, it goes without saying that it can be applied to three or more sets.

The present invention has the advantage that part or all of the same data block can be stored in multiple areas on a storage device.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention. In the figure, 1...Selector, 2, 3...Address counter, 4, 5...Length counter,
6, 7... Start register, 8... Data counter, 9... Data register, 10, 11... Comparison circuit, 12, 13... Zero detector, 14, 15...
...Flip-flop, 16, 17... Data flip-flop, 18, 19... AND circuit, 20
...Control circuit, 21...Comparison control circuit, S1, S
2...Start signal, S3, S4...Transfer signal, S5
...address signal, S6...data signal.

Claims (1)

[Scope of Claims] 1. A data transfer device that transfers data from a peripheral device to a storage device, comprising: a plurality of address storage means for storing addresses of the storage device that stores transferred data; and each of these address storage means. Transfer scheduled number storage means for storing the number of data bytes scheduled to be transferred from the peripheral device, counter means for counting the number of data bytes transferred from the external device, and corresponding to the address storage means, respectively. transfer start data byte number storage means for storing a predetermined number of data bytes transferred from the peripheral device to indicate the start of data transfer to the storage device; and a count result of the counting means and the start of transfer. 1. A data transfer device comprising: comparison means for comparing the number of data bytes in the data byte number storage means, and when a match is found by the comparison means, the data is transferred to the storage device.