JPS6151662A - Signal detection circuit - Google Patents

Signal detection circuit

Info

Publication number
JPS6151662A
JPS6151662A JP17477184A JP17477184A JPS6151662A JP S6151662 A JPS6151662 A JP S6151662A JP 17477184 A JP17477184 A JP 17477184A JP 17477184 A JP17477184 A JP 17477184A JP S6151662 A JPS6151662 A JP S6151662A
Authority
JP
Japan
Prior art keywords
voltage
input voltage
input
peak
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17477184A
Other languages
Japanese (ja)
Inventor
Akira Ikeda
明 池田
Jiyunichirou Harada
洵一朗 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP17477184A priority Critical patent/JPS6151662A/en
Publication of JPS6151662A publication Critical patent/JPS6151662A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To attain sure signal detection even if the level of an input voltage is fluctuated by comparing an input voltage with the input voltage through an anti-parallel circuit comprising rectifier elements and a capacitor. CONSTITUTION:The input voltage such as an AC signal is compared with a positive or negative voltage corresponding to a peak of the input voltage outputted when the peak potential difference is a prescribed value or over in response to the peak of the input voltage through a circuit 2 consisting of an anti- parallel circuit comprising diodes D1, D2 and a capacitor C connected thereto by a comparator 1. The positive or negative detection pulse is given as the output and even if the level of the input voltage is fluctuated and the peak level is fluctuated due to noise in the range where the peak level is within a prescribed value, the detection signal is detected surely.

Description

【発明の詳細な説明】 3.1 産業上の利用分野 この発明は、入力電圧より信号を取出すために使用され
る信号検出回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION 3.1 Industrial Application Field This invention relates to a signal detection circuit used to extract a signal from an input voltage.

3.2 従来技術とその欠点 記録媒体に磁気的に記録された信号又は光学的に記録さ
れた信号を読出すためには、従来は、読出ヘッド及び増
幅回路を経て入力される電圧を、スライサ又はリミッタ
などの波形処理回路を用いて振幅選択による波形操作を
行なっているが、従来の波形処理回路に設定されるレベ
ルは常に一定である。従って、第3図(イ)に示される
ように入力電圧が安定した波形のものである場合は、所
定レベルj!、、zzによって同図の下側に示すように
、入力波形に忠実に対応する出力が得られるが、記録媒
体の搬送条件や記録密度、又は増幅率などとの関係によ
り入力電圧が(ロ)に示すように所定レベル以下になっ
た場合は、その下側に示すように、出力が入力波形に対
応しなくなり、信号読出精度が低い欠点があった。
3.2 Prior Art and Its Disadvantages In order to read signals recorded magnetically or optically on a recording medium, conventionally, a voltage input via a read head and an amplifier circuit is applied to a slicer. Alternatively, a waveform processing circuit such as a limiter is used to manipulate the waveform by selecting the amplitude, but the level set in the conventional waveform processing circuit is always constant. Therefore, if the input voltage has a stable waveform as shown in FIG. 3(a), the predetermined level j! ,,zz can provide an output that faithfully corresponds to the input waveform as shown in the lower part of the figure. When the level falls below a predetermined level, as shown below, the output no longer corresponds to the input waveform, resulting in low signal readout accuracy.

3、−3 この発明の目的 この発明は、上記の点に鑑み、入力電圧のレベルが記録
媒体の搬送条件、記録密度又は増幅率などにより変動し
ても、これに左右されずに、確実に信号を検出すること
ができるようにした信号検出回路を提供することを目的
とする。
3.-3 Purpose of the Invention In view of the above points, the present invention provides a reliable system that is independent of the fluctuations in the input voltage level due to the transport conditions of the recording medium, the recording density, the amplification factor, etc. An object of the present invention is to provide a signal detection circuit capable of detecting a signal.

この発明は、とくにカードなどに磁気的、又は光学的に
バーコードで記録されている信号を読出す場合に適用し
て有効であるが、これに限定されるものではなく、ピー
クを含む交流信号により入力される場合に、その信号を
検出するために広く利用しうるちのである。
The present invention is particularly effective when applied to reading signals magnetically or optically recorded as barcodes on cards, etc., but is not limited to this, and is applicable to AC signals including peaks. It can be widely used to detect signals when they are input by

3.4 この発明の実施例 次に、この発明を、第1図ないし第3図の図面に基いて
説明する。
3.4 Embodiments of the Invention Next, the invention will be explained based on the drawings of FIGS. 1 to 3.

第1図は、この発明に係る信号検出回路であり、差動増
幅回路などからなる電圧比較器1と、その電圧比較器の
負入力端子に接続された回路2とから構成されている。
FIG. 1 shows a signal detection circuit according to the present invention, which is composed of a voltage comparator 1 consisting of a differential amplifier circuit, etc., and a circuit 2 connected to the negative input terminal of the voltage comparator.

回路2は、二つの整流素子D1.’Dzをその順方向電
流の向きが互いに逆になるように接続してなる並列回路
2aと、その並列回路と前記電圧比較器との間に設けた
コンデンサCよりなっている。
Circuit 2 includes two rectifying elements D1. It consists of a parallel circuit 2a formed by connecting Dz's in such a way that the directions of their forward currents are opposite to each other, and a capacitor C provided between the parallel circuit and the voltage comparator.

整流素子Ds 、D2は、その順方向電流の電圧降下特
性を利用するもので、ダイオードを用いる。また、コン
デンサCは、入力電圧が正負の各ピークを過ぎたときに
、その時点よりコンデンサの放電電圧が入力電圧と等し
くなるまで、ピーク時の電圧を保持するためのものであ
る。
The rectifying elements Ds and D2 utilize the voltage drop characteristics of their forward currents, and use diodes. The capacitor C is used to hold the voltage at the peak when the input voltage passes each positive and negative peak until the discharge voltage of the capacitor becomes equal to the input voltage.

このような構成により、今、入力端子3に、交流入力信
号が入力したとすると、電圧比較器1の第1入力■の波
形は、第2図に実線で示すように、交流入力信号と同一
の波形であり、℃1時点までは増加傾向にあるため、電
流は整流素子D1を順方向に流れる。そして、整流素子
D1の順方向特性により、第2入力■の電圧は■の電圧
よりMDIだけ降下した電圧で追従する。しかし、入力
電圧がピークを越えると、コンデンサCの作用により、
■の電圧が入力電圧のピーク時の電圧を保持する結果、
t2の時点において、比較器の第1入力■の電圧と第2
入力■の電圧が等しくなる。従って、へ領域では、電圧
比較器1にVDlの電圧がかかるため、この信号検出回
路の出力■は、第2図の下側に示されているように、正
となる。
With this configuration, if an AC input signal is now input to the input terminal 3, the waveform of the first input ■ of the voltage comparator 1 will be the same as the AC input signal, as shown by the solid line in FIG. Since the waveform is increasing up to the point of 1 degree Celsius, the current flows in the forward direction through the rectifying element D1. Then, due to the forward characteristic of the rectifying element D1, the voltage at the second input (2) follows the voltage at the second input (2) at a voltage that is lower than the voltage at (2) by MDI. However, when the input voltage exceeds the peak, due to the action of capacitor C,
■As a result, the voltage maintains the voltage at the peak of the input voltage,
At time t2, the voltage of the first input (■) of the comparator and the voltage of the second input
The voltages of input ■ become equal. Therefore, in the region 1, the voltage of VDl is applied to the voltage comparator 1, so the output 2 of the signal detection circuit becomes positive as shown in the lower part of FIG.

Bの領域では、第1入力■は減少傾向にあるため、電流
が■から整流素子D2を通って■に向って流れ、D2の
順方向電圧によりVD2が比較器1にかかり、その出力
■は負となる。
In region B, the first input ■ tends to decrease, so the current flows from ■ through the rectifier D2 toward ■, VD2 is applied to comparator 1 due to the forward voltage of D2, and its output ■ becomes becomes negative.

以下、C,D、Eの領域においても同様に、入力信号の
レベルに関係なく、それぞれ入力信号の各ピークに対応
して、正、負の出力となる。
Similarly, in regions C, D, and E, positive and negative outputs are produced corresponding to each peak of the input signal, regardless of the level of the input signal.

Fの領域においては、入力信号が小ざなピークpt、I
)zを有するが、ピーク間電圧が整流素子D2の順方向
電圧VDzよりも小さいので、整流素子の電流方向を変
えるには至らず、出力に反映されない。入力信号の正電
圧側において小さなピークが発生した場合も、整流素子
D1によって同様な作用がされる。
In the region F, the input signal has small peaks pt, I
)z, but since the peak-to-peak voltage is smaller than the forward voltage VDz of the rectifying element D2, it does not change the current direction of the rectifying element and is not reflected in the output. Even when a small peak occurs on the positive voltage side of the input signal, the same effect is performed by the rectifying element D1.

このような小さなピークは、一般にノイズにより発生す
る。従って、この信号検出回路の前段において、混入し
たノイズが並列回路の各整流素子の順方向電圧より小さ
くなるような増幅率に設定することにより、この信号検
出回路をノイズの影響を受けないものとすることができ
る。
Such small peaks are generally caused by noise. Therefore, by setting the amplification factor at the front stage of this signal detection circuit so that the mixed noise is smaller than the forward voltage of each rectifying element in the parallel circuit, this signal detection circuit can be made unaffected by noise. can do.

3.5 この発明の効果 上述のように、この発明によれば、入力電圧のピークを
検出するたびに正負の変化する信号を出力するので、入
力信号のレベルの変動に左右されずに確実に信号を検出
することができる。
3.5 Effects of the Invention As described above, according to the invention, a signal that changes in positive or negative is output every time a peak of the input voltage is detected, so that the signal can be reliably obtained without being affected by fluctuations in the level of the input signal. signal can be detected.

また、前後のピークの電位差が一定レベル以下である場
合は、これを無視して出力しないので、ノイズの影響を
受けない信頼性の高い信号検出回路を提供することがで
きる。
Further, if the potential difference between the front and rear peaks is below a certain level, this is ignored and no output is performed, so it is possible to provide a highly reliable signal detection circuit that is not affected by noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例を示す回路図、第2図は第1
図の■、■の符号で示された第1入力及び第2入力の波
形と■の符号で示された出力の波形を示す図である。第
3図は従来技術を説明する図である。 1・・・電圧比較器 2・・・回路 2a・・・並列回路 Dl、Dz・・・整流素子 C・・・コンデンサ 第1図 第3区 (=)
Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing the waveforms of the first input and the second input indicated by the symbols ■ and ■ in the figure, and the waveform of the output indicated by the symbol ■. FIG. 3 is a diagram illustrating the prior art. 1... Voltage comparator 2... Circuit 2a... Parallel circuit Dl, Dz... Rectifying element C... Capacitor Figure 1 Section 3 (=)

Claims (1)

【特許請求の範囲】[Claims] 入力電圧を、一つには直接に電圧比較器にその第1入力
として、もう一つには、二つの整流素子を順方向電流の
向きが互いに逆になるように接続した並列回路にコンデ
ンサを接続してなる回路を経て、前記電圧比較器にその
第2入力としてそれぞれ与えるようにしたことを特徴と
する信号検出回路。
The input voltage is applied directly to a voltage comparator as its first input, and on the other hand, a capacitor is connected to a parallel circuit in which two rectifying elements are connected so that the forward current directions are opposite to each other. A signal detection circuit characterized in that the signal is supplied to the voltage comparator as its second input through a connected circuit.
JP17477184A 1984-08-22 1984-08-22 Signal detection circuit Pending JPS6151662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17477184A JPS6151662A (en) 1984-08-22 1984-08-22 Signal detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17477184A JPS6151662A (en) 1984-08-22 1984-08-22 Signal detection circuit

Publications (1)

Publication Number Publication Date
JPS6151662A true JPS6151662A (en) 1986-03-14

Family

ID=15984379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17477184A Pending JPS6151662A (en) 1984-08-22 1984-08-22 Signal detection circuit

Country Status (1)

Country Link
JP (1) JPS6151662A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0469664U (en) * 1990-10-26 1992-06-19
JP2005329030A (en) * 2004-05-20 2005-12-02 Elsol Products Kk Compact container for cosmetic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0469664U (en) * 1990-10-26 1992-06-19
JP2005329030A (en) * 2004-05-20 2005-12-02 Elsol Products Kk Compact container for cosmetic

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