JP2856787B2 - Binarization circuit, intermediate level detection circuit, and peak envelope detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarization circuit for binarizing an analog image signal output from a photoelectric conversion element or the like, an intermediate level detection circuit, and a peak envelope detection circuit. Things.

(Prior Art) In a typical image input device, an analog image signal read from a photoelectric conversion element is quantized by a binarization circuit. Such analog image signals contain noise of low frequency components due to shading distortion of the reading optical system, have a color on the background of the read document, and draw light images such as characters and figures. For example, the dynamic range (amplitude value, that is, the difference between the white level and the black level) of the signal may fluctuate. If a constant threshold level is set when binarizing such an image signal,
A correct binary signal cannot be obtained. For this reason, a binarization circuit that varies the threshold level in conjunction with the envelope of the maximum value or the minimum value of the analog image signal or the variation of each intermediate level is used.

Conventionally, the above-described binarization circuit includes a comparator 41, a local maximum value detecting unit 42, a local minimum value detecting unit 43, and an intermediate level detecting unit 44, as shown in FIG. An analog image signal output as an electric signal from the photoelectric conversion element and amplified to an appropriate level is supplied to one input terminal of a comparator 41 via an input terminal IN, and is also detected by a local maximum detecting unit 42 and a local minimum value detecting unit 43. Is also supplied. Local maximum detector 42 and local minimum detector
An intermediate level between the local maximum value and the local minimum value of the analog image signal detected at 43 is output from an intermediate level detection unit 44 composed of a synthesizing circuit with the same resistance value, and supplied to the other input terminal of the comparator 41 as a threshold voltage. You.

As shown in FIG. 5, the local maximum value detecting section 42 includes a diode.
It is composed of D1, a capacitor C1, and a resistor R1.
As shown in FIG. 6, the minimum value detecting section 43 includes a diode D
2. Consists of a capacitor C2, a resistor R2 and a constant voltage source DC.

(Problems to be Solved by the Invention) In the binarization circuit shown in FIG. 4, the discharge time constant C1 · R1 of the local maximum value detecting unit 42 in FIG. 5 and the local minimum value detecting unit 43 in FIG.
There is a problem that it is difficult to obtain a correct binarized signal even if the discharge time constants C2 and R2 are adjusted to various values.

That is, as shown in the waveform diagram of FIG. 7, the black-and-white pattern of the original to be read is as shown in FIG. 7A, and the analog image signal obtained by reading this is as shown in FIG. Shall be. In this case, if each of the above time constants is set to a large value, the output of the local maximum value detecting unit 42 becomes as shown by a broken line α, and the output of the local minimum value detecting unit 43 becomes as shown by a dashed line β. The threshold value γ is as shown by the dotted line. In the example of FIG. 7, a correct binarized signal cannot be obtained for the low frequency part (a) and the high frequency part (b). When each of the above time constants is set to a small value, as shown in FIG. 8, the output of the local maximum value detecting section 42 is as shown by a broken line α, and the output of the local minimum value detecting section 43 is as shown by a dashed line β. And a threshold γ based on these intermediate levels
Is as shown by the dotted line. In the example of FIG.
The problem of the high frequency part (b) is solved, but the problem of the low frequency part (a) is not solved yet.

JP-A-51-50555 "waveform shaping circuit" separately holds peak and minimum levels of a waveform shaping target signal, and sets an average level of the held maximum peak value and minimum peak value as a threshold. A circuit that slices a waveform shaping target signal and binarizes the signal is disclosed. However, in this waveform shaping circuit, since the peak hold circuit including the peak detector and the hold circuit operates with an appropriate time constant, if this time constant is increased, the low-frequency portion and the high-frequency portion of the signal to be waveform-shaped are reduced. If a correct binarized signal cannot be obtained and the time constant is reduced, the problem of the high frequency portion is solved, but the problem of the low frequency portion remains unsolved.

Japanese Patent Application Laid-Open No. Sho 56-2728, "Binarization processing circuit" is provided with a second envelope detection circuit that follows a change in white level and a third envelope detection circuit that follows a change in black level. A circuit is disclosed in which outputs of both detection circuits are combined to form a threshold value for binarization. However, also in this case, the time constant of the second and third envelope detection circuits influences the determination of the threshold value defined as the average value of the white level and the black level, and particularly, only the white level is maintained or the black level is maintained. There were problems such as difficulty in maintaining an accurate threshold value when the level continued.

Japanese Unexamined Patent Publication No. Sho 62-237808 discloses a circuit in which the time constants of an upper limit peak holding circuit and a lower current peak holding circuit are varied according to the frequency of an input signal. In this device, the time constant is switched to a larger value as the input signal becomes lower in frequency. However, since the time constant is changed according to the conduction resistance of the transistor, it is difficult to ensure linearity with respect to the input signal frequency. In addition, the relationship between the frequency band of the input signal frequency and the time constant has to be determined through trial and error, and has a problem that it is difficult to obtain versatility.

(Means for Solving the Problems) A binarization circuit according to the present invention receives an analog signal to be binarized at a first input terminal and sets a threshold value which varies according to the variation of the analog signal to a second input terminal. A comparator for receiving the signal and performing binarization based on the comparison result; a comparator with hysteresis for comparing the magnitude of the analog signal with its delay signal; detecting a rising point of the output of the comparator with hysteresis; A local maximum point detection unit that outputs a local maximum point pulse indicating a local maximum point that appears therein, detects a falling point of the output of the comparator with hysteresis, and outputs a local minimum point pulse that indicates a local minimum point that appears in the analog signal. A local minimum point detector that holds the level of the local maximum point of the analog signal indicated by the local maximum point pulse until the next local maximum point pulse is supplied. A local maximum holding unit, a local minimum holding unit that holds the level of the local minimum of the analog signal specified by the local minimum pulse until the next local minimum pulse is supplied, and a holding value of the local maximum holding unit. An intermediate level generating unit that generates an intermediate level with a value held by the minimum value holding unit and supplies the intermediate value to the second input terminal of the comparator as the threshold value.

Further, the intermediate level detection circuit of the present invention detects a comparator with hysteresis for comparing the magnitude of an analog signal and its delay signal, and detects a rising point of an output of the comparator with hysteresis, and detects a maximum point appearing in the analog signal. A maximum point detection unit that outputs a maximum point pulse, and a minimum point detection unit that detects a falling point of the output of the comparator with hysteresis and outputs a minimum point pulse indicating a minimum point that appears in the analog signal. A local maximum value holding unit that holds the level of the local maximum point of the analog signal indicated by the local maximum point pulse until the next local maximum point pulse is supplied, and a local minimum point of the analog signal indicated by the local minimum point pulse. A minimum value holding unit for holding a level until a next minimum point pulse is supplied; a holding value of the maximum value holding unit; It is characterized in that an intermediate level generator for generating an intermediate level between the holding value of the parts.

Furthermore, the peak envelope detection circuit of the present invention includes a comparator with hysteresis for comparing the magnitude of the analog signal and its delay signal, a rising point of the output of the comparator with hysteresis, and a local maximum appearing in the analog signal. A maximum point detection unit that outputs a maximum point pulse indicating a point, and a minimum point detection unit that detects a falling point of the output of the comparator with hysteresis and outputs a minimum point pulse indicating a minimum point appearing in the analog signal. A maximum value holding unit that holds the level of the local maximum point of the analog signal indicated by the local maximum point pulse until the next local maximum point pulse is supplied; and a local minimum of the analog signal specified by the local minimum point pulse. A minimum point holding unit for holding the point level until the next minimum point pulse is supplied. .

 Hereinafter, the operation of the present invention will be described together with examples.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a binarization circuit according to an embodiment of the present invention, wherein 1 is a comparator, 10 is a local maximum point detector and a local minimum point detector, and 20 is a local maximum. A value holding unit, 30 is a minimum value holding unit, and 40 is an intermediate level generation unit.

An analog image signal output as an electric signal from the photoelectric conversion element and amplified to an appropriate level is supplied to one input terminal of the comparator 1 through an input terminal IN, and is also detected by a maximum point detection unit and a minimum point detection unit 10. Is also supplied. The local maximum point detecting unit and the local minimum point detecting unit 10 include a comparator 11, a delay unit 12, a local maximum point pulse generating circuit 13, and a local minimum point pulse generating circuit 14. The analog video signal is directly supplied to one input terminal of the comparator 11 as the voltage Vo, and is also supplied to the other input terminal of the comparator 11 as the voltage Vd while being delayed by a predetermined time in the delay unit 12. . As the delay time of the delay unit 11, a value that is about half the minimum pixel period of the analog image signal is set. The comparator 11 has a function to prevent malfunctions caused by noise included in the analog image signal and unnecessary components of high frequency due to minute irregularities on the background of the document.
Hysteresis characteristics of an appropriate size are given by the feedback resistor Rf.

Therefore, as shown in FIGS. 2A and 2B,
When Vd becomes larger than voltage Vo by a predetermined value based on the hysteresis characteristic, output Vc of comparator 11 rises from low to high. Next, when the voltage Vd becomes smaller than the voltage Vo by a predetermined value based on the hysteresis characteristic, the output Vc of the comparator 11 falls from high to low. The maximum point pulse generator 13 detects the rising point of the output Vc of the comparator 11 and outputs a maximum point pulse Va as shown in FIG. 2 (C). The minimum point pulse generation unit 14 detects the falling point of the output Vc of the comparator 11 and
A minimum point pulse Vb as shown in FIG.

In the maximum value holding unit 20, the switch 21 is closed by the maximum point pulse Va output from the maximum point pulse generation circuit 13, and the analog signal voltage appearing at the input terminal IN is composed of the diode D1, the capacitor C1, and the resistor R1. The voltage is supplied to the peak hold unit 22 and held by the capacitor C1. Similarly, in the minimum value holding unit 30, the switch 31 is closed by the minimum point pulse Vb output from the minimum point pulse generation circuit 14, and the analog signal voltage appearing at the input terminal IN is changed to the diode D2, the capacitor C2, the resistor The voltage is supplied to the bottom hold unit 32 composed of R2 and the constant voltage source B, and is held by the capacitor C2. Discharge time constant C1
R1 and the time constants C2 and R2 for charging the bottom hold unit 32 are both set to large values.

Therefore, as shown in the waveform diagram of FIG. 3, the black and white pattern of the document to be read is as shown in FIG.
If the analog image signal obtained by reading the signal is as shown in FIG.
The output of 20 is a peak envelope connecting the local maximum values in a step-like manner as indicated by a dashed line α, and the output of the local minimum value holding unit 30 is a peak envelope connecting the local minimum values in a step-like manner as indicated by a dashed line β. Become. Further, the intermediate level γ generated by the intermediate level detecting section 40 which connects the resistors 41 and 42 having the same resistance value and uses the intermediate point as an output terminal is as shown by a dotted line. The intermediate level indicated by the dotted line is supplied to the other input terminal of the comparator 1 as a threshold voltage.

As a result, the binary signal output from the comparator 1 is as shown in FIG.
A correct binarized signal is obtained for both the high frequency part and the high frequency part (b). 3 (D) and 3 (E) show the maximum point pulse Va output from the maximum point pulse generation circuit 13 and the minimum point pulse Vb output from the minimum point pulse generation circuit 14.

The configuration in which the intermediate level between the local maximum value held in the local maximum value holding unit 20 and the local minimum value held in the local minimum value holding unit 30 is generated and used as the threshold value of the binarization comparator 1 has been exemplified. However, a voltage smaller than the maximum value held in the local maximum value holding unit 20 by a predetermined value or a voltage larger than the local minimum value held in the local minimum value holding unit 30 by a predetermined value is set to the threshold value of the binarizing comparator 1. It can also be.

Also, the present invention has been described for the case of a binarization circuit.
However, the present invention can also be applied to an intermediate level detection circuit for detecting an intermediate level of various analog signals and a peak envelope detection circuit for detecting only a maximum value and a minimum value or only one of them.

(Effect of the Invention) As described in detail above, the binarization circuit of the present invention
The analog signal to be binarized and its delay signal are compared in magnitude with a comparator with hysteresis, and the maximum value of the analog signal is detected based on the rising point of the comparison output, and the minimum point of the analog signal is determined based on the falling point of the comparison output. Since detection is performed, the maximum point and the minimum point of the analog signal can be accurately detected, and the analog signal level is maintained with a large time constant between the adjacent maximum point and the adjacent minimum point thus detected. To be
An intermediate level can be generated with sufficient accuracy even for an analog signal that slowly changes at a low frequency, and can be supplied as a threshold value to a comparator for binarization, enabling high-precision binarization. A comparator with hysteresis also has, for example, an inverting input terminal to which an analog signal is supplied, a non-inverting input terminal to be supplied via a delay device for delaying the analog signal by a time shorter than its minimum change period, and a non-inverting input terminal. And an output terminal connected via a feedback resistor to the inverting amplifier, so that excellent effects such as setting a hysteresis characteristic according to the resistance value of the feedback resistor can be obtained. .

Also, by extracting and combining the components of the binarization circuit of the present invention, an intermediate level detection circuit for detecting an intermediate level of various analog signals, a maximum value and a minimum value of an analog signal, or only one of them. And a peak envelope detection circuit for detecting the peak envelope can be formed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a binarizing circuit according to the present invention, and FIG. 2 is a diagram for explaining the operation of a local maximum value detecting unit and a local minimum value detecting unit shown in FIG. FIG. 3 is a waveform diagram for explaining the operation of the binarization circuit shown in FIG. 1, FIG. 4 is a block diagram showing an example of the configuration of a conventional binarization circuit, and FIG. FIGS. 6 and 7 are circuit diagrams showing the configuration of the local maximum value detecting unit and local minimum value detecting unit shown in FIG. 4, and FIGS. 7 and 8 show the operation of the conventional circuit shown in FIG. FIG. 9 is a waveform diagram illustrating a case where the constant is large and a case where the constant is small. 1 ... Comparison for binarization 10 ... Maximum value detection unit and minimum value detection unit 11 ... Comparator 12 ... Delay device 13 ... Maximum point pulse generation circuit 14 ... Minimum point pulse generation circuit 20 ... Maximum value holding section 21 Switch 22 Peak hold section 30 Minimum value holding section 31 Switch 32 Bottom hold section 40 Intermediate level generation section

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 5/00

Claims (3)

(57) [Claims] An analog signal to be binarized is received at a first input terminal, and a threshold value fluctuating according to the fluctuation of the analog signal is received at a second input terminal.
A comparator for performing value conversion, a comparator with hysteresis for comparing the magnitude of the analog signal with a delay signal thereof, a maximum point indicating a maximum point appearing in the analog signal, detecting a rising point of an output of the comparator with hysteresis. A local maximum point detector that outputs a point pulse, a local minimum point detector that detects a falling point of the output of the comparator with hysteresis, and outputs a local minimum point pulse indicating a local minimum that appears in the analog signal; A maximum value holding unit that holds the level of the local maximum point of the analog signal indicated by the point pulse until the next local maximum point pulse is supplied, and the level of the local minimum point of the analog signal indicated by the local minimum point pulse. A minimum value holding unit that holds until the next minimum point pulse is supplied, a holding value of the maximum value holding unit, and a holding value of the minimum value holding unit Binarizing circuit interlevel generates, characterized in that an intermediate level generator for supplying to the second input terminal of said comparator as said threshold. 2. A comparator with hysteresis for comparing the magnitude of an analog signal with its delay signal, a rising point of an output of the comparator with hysteresis is detected, and a maximum point pulse indicating a maximum point appearing in the analog signal is output. A local minimum point detecting unit, a local minimum point detecting unit that detects a falling point of the output of the comparator with hysteresis, and outputs a local minimum point pulse indicating a local minimum point appearing in the analog signal, and instructs by the local maximum point pulse. A maximum value holding unit that holds the level of the maximum point of the analog signal until the next maximum point pulse is supplied, and sets the level of the minimum point of the analog signal indicated by the minimum point pulse to the next minimum point. A minimum value holding unit that holds the pulse until the pulse is supplied, and an intermediate level between a holding value of the maximum value holding unit and a holding value of the minimum value holding unit. Intermediate level detection circuit, characterized in that an intermediate level generator for generating. 3. A comparator with hysteresis for comparing the magnitude of an analog signal with its delay signal, a rising point of an output of the comparator with hysteresis is detected, and a maximum point pulse indicating a maximum point appearing in the analog signal is output. A local minimum point detecting unit, a local minimum point detecting unit that detects a falling point of the output of the comparator with hysteresis, and outputs a local minimum point pulse indicating a local minimum point appearing in the analog signal, and instructs by the local maximum point pulse. A maximum value holding unit that holds the level of the maximum point of the analog signal until the next maximum point pulse is supplied, and sets the level of the minimum point of the analog signal indicated by the minimum point pulse to the next minimum point. A peak envelope detection circuit, comprising: a minimum value holding unit that holds the pulse until a pulse is supplied.