JPS5925267B2 - optical character reader - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a character reading device equipped with a slice level generation function that quantizes analog signals obtained according to the shading of characters written on a form into accurate electrical signals regardless of the shading of the characters. It is related to the device.

A conventional device of this kind photoelectrically converts characters written on a form using a device as shown in FIG. That is, in Figure 1, 1 is a form, and the characters "1", "2", etc.
......, "a", "i", ......
Light is irradiated onto this form 1 from a light source 2, the reflected light is focused by a lens 3, reflected by a reflecting mirror 4, and then decomposed into picture elements by a sensor 5, which is photoelectrically converted. It is amplified by an amplifier 7 and sent to one input side of a comparator 8. Note that 6 is a circuit that drives the sensor 5. A predetermined voltage E (hereinafter this voltage will be referred to as a slice level) is applied to the other input side of the comparator 8. As a result, the comparator 8 uses the analog signal from the sensor 5 and the slice level E.
A digital signal for each character is extracted from the output side 9 of the comparator 8 as a character signal. However, in such a conventional device, the characters written on the form 1 have shading, and when this is photoelectrically converted, it is detected as a large or small amount of information.

If the previous slice level E is fixed at this time, some parts of a certain character will not be detected.
Further, as the brightness of the light source 2 in the apparatus of FIG. 1 decreases, the voltage level of the entire analog signal from the sensor 5 decreases. Therefore, if the slice level E for separating white and black is set higher than the previous analog signal, a state will arise in which data cannot be detected at all. In this case, even if the slice level E was set low, it was difficult to balance the shape and shading of the characters. In order to eliminate these drawbacks, the present invention detects the peak value of the white part and the peak value of the black part of the character part on the document in a preset scanning interval of the sensor from the analog signal obtained by the sensor, and The average value of each of the n peak values in a scanning interval that is n times the interval (n is 1 or more) is calculated, and the slice level is set based on the average value of these peak values. be. Embodiments of the character reading device of the present invention will be described below. FIG. 2 is a block diagram showing one embodiment of the present invention, in which an analog signal S1 obtained by amplifying an analog signal from a sensor with an amplifier is introduced into the input of the sample hold section 11.

Next, the output S2 of the sample and hold section 11 which sampled and held the analog signal S1 is outputted to the input side of the white peak detection and hold circuit 21 surrounded by a broken line, the input side of the black peak detection and hold circuit 31, and one input of the comparator 51. It is starting to be introduced on the side. The output S3 of the white peak detection and hold section 21 is introduced into the input side of the AD converter 22, and the output S4 of this AD converter 22 is introduced into one input side of the adder 23 as a 5-pit digital signal. . Further, the output S5 of the adder 23 is composed of 8 bits, and this output S5 is introduced into the input side of the 8-bit register 24. The output of this 8-bit register 24 uses only the upper 5 bits and is returned to the other input side of the adder 23 and introduced. Note that the adder 23 and the 8-bit register 24 perform the AD operation a predetermined number of times.
After adding the output S4 of the converter 22, the upper five bits of the digital signal S6 are sent to a control section (not shown) through a gate (not shown). Below, the configurations of the black peak detection and hold circuit 31, AD converter 32, adder 33, and 8-bit register 34 are the same as above, and the output S7 obtained there is also a digital signal using the upper 5 bits. It is designed to be sent to the control unit as The control unit calculates the difference between the average white peak voltage and the average black peak voltage to an appropriate voltage value, and this calculated voltage value is used as the slice level for detecting characters written on the form. A 5-bit digital signal S8 is introduced into the input side of the DA converter 41.

The output S9 which has been DA converted by the DA converter 41 is sent to the comparator 51.
The output of this comparator 51 is sent out as a quantized character signal SlO. Next, the operation of the character reading device configured as above will be explained. First, the waveform drawn with a solid line in Fig. 3 is the analog signal S1 for one scan of the sensor, which is actually 128 bits, but for convenience of explanation, it is 128 bits.
Only the waveform for the 0 bit is shown.

Here, the waveform drawn by the broken line is the waveform of the output S2 obtained by holding the voltage peak of the signal S1 from the previous sensor for each bit in the sample hold section 11 in FIG. A white peak detection and hold circuit 21 surrounded by a broken line is introduced. Here, the configuration and operation of the white peak detection and hold circuit 21 will be explained. This circuit 21 includes a first differential amplifier A1, a second differential amplifier A2 (
voltage follower), a first junction field effect transistor F1 and a second junction field effect transistor F2 connected to the input side of the first differential amplifier A, and the input side of the second differential amplifier A2. a transistor TRl connected to
and a peak detection and hold diode D connected between the first differential amplifier A1 and the transistor TRl.
1 and a capacitor C, and a first differential amplifier A1 and a second differential amplifier A2 form a closed loop to detect and hold the peak value of the analog signal. Note that an amplifier with a very high slew rate is used as the first differential amplifier A1 to reduce the delay between the input signal and the output signal.

To explain this circuit 21 in detail below, first, the drain of the first field effect transistor F and the source of the second field effect transistor F2 are connected to the first input terminal of the first differential amplifier A1. ing. The source of the first field effect transistor F is the input terminal of the circuit 21, a bias resistor R is connected between the source and the gate, and a gate control diode D is connected to the gate.
One end of 2 is connected. The other end of the diode D2 serves as an input end for a signal section setting signal Sll that controls conduction/non-conduction of the first field effect transistor F1.
A speed-up capacitor C2 is connected to both ends of the diode D2. The drain of the second field effect transistor F2 is grounded, a bias resistor R3 is connected between the drain and the gate, and one end of a gate control diode D3 is connected to the gate. The other end of the diode D3 serves as an input end for a signal Sl2 for setting an initial reference potential that controls conduction/non-conduction of the second field effect transistor F2, and a speed-up capacitor C3 is connected to both ends of the diode D3. is connected.
Further, a capacitor C4 is connected between the first input terminal of the first differential amplifier A1 and ground.

Next, a peak value detection diode D1 and a hold capacitor C are connected between the output terminal of the first differential amplifier A1 and the ground.
1 series circuit is connected, and a transistor TRl for setting a hold time and its collector resistor R4 are connected between the midpoint of the connection between the diode D1 and the capacitor C1 and the ground, and the collector of the transistor TRl is connected to a second series circuit. It is connected to the first input terminal of the differential amplifier A2. Further, one end of the bias resistor R5 is connected to the base of the transistor TRl, and the other end of the resistor R5 is connected to the base of the transistor TRl.
Hold time setting signal Sl that controls conduction/non-conduction of l
It is the input terminal of 3. Next, the second differential amplifier A2
The output terminal of the circuit 21 is the output terminal of the circuit 21, and this output terminal is connected to the second input terminal of the second differential amplifier A2 to form a first feedback loop, and the feedback resistor R , to form a second feedback loop. Further, the output terminal of the first differential amplifier A is connected to the first differential amplifier A1 via a resistor R6.
is connected to the second input terminal of the input terminal to form a third feedback loop. Further, a capacitor C5 and a diode D4 are connected in parallel between the output terminal of the first differential amplifier A1 and the second input terminal, and the diode D4 is connected between the output terminal of the first differential amplifier A1 and the second input terminal.
The capacitor C5 is used to speed up the diode D4.The capacitor C5 is used to speed up the diode D4.

The resistor R6 serves not only as a feedback resistor but also as a capacitor C4 connected to the first input terminal of the first differential amplifier A.
and a second differential amplifier A for the input signal of the first differential amplifier A.
This is to prevent an abnormal voltage due to a delay in the output signal of the differential amplifier A2.

White peak detection and hold circuit 21 configured as above
The operation is as follows: First, in order to detect a white peak value higher than the ground potential within a preset time (in this example, the signal interval for one scan of the sensor), the signal Sl2 for setting the initial reference potential is set. Therefore, the second field effect transistor F2 is rendered conductive. Next, the signal S2 from the sample and hold section 11 described above is input to the first differential amplifier A1 only within a preset time by making the first field effect transistor F1 conductive using the signal interval setting signal Sll. . The peak of the voltage amplified by the first differential amplifier A1 is detected by the diode D1, and the peak value is held in the capacitor C1.

This hold voltage is constantly updated and held as higher peak values appear. This hold voltage is then amplified by the second differential amplifier A2 and output as a white peak voltage S3 to its output terminal. Further, the hold time can be changed as appropriate depending on the number of characters read per second, etc. That is, this is performed by discharging the hold voltage by the transistor TRl driven in accordance with the signal Sl3. The output signal S3 of the circuit 21 obtained in this manner has a waveform shown by a solid line in FIG.

Note that the waveform indicated by the broken line is the output signal S2 of the sample and hold section 11. Next, similarly to the white peak detection and hold circuit 21, the output signal S of the sample hold section 11 is
The black peak detection and hold circuit 31 in which 2 is introduced will now be described.

The configuration and operation of this circuit 31 are roughly the same as the white peak detection and hold circuit 21, but the second junction field effect transistor F2l, capacitor Cll, and transistor TRll are not grounded but connected to a +V1 [V] voltage source. This is to detect and hold a lower black peak value with the voltage +V1 as a reference. Note that this voltage +1 is always set higher than the voltage of the output signal S1 from the sensor.

Further, the signal Sl3 that drives the transistor TR,l is as follows, since the transistor TRll is a PNP transistor.
Signal Sl3 in white peak detection and hold circuit 21
This is a contradictory signal. The output signal S3l obtained by the black peak detection and hold circuit 31 in this manner has the waveform shown by the solid line in FIG.

Note that the waveform indicated by the broken line is the output signal S2 of the sample and hold section 11. Next, the white peak hold voltage and black peak voltage obtained as described above are each subjected to AD conversion, and the results are sequentially converted eight times (this number may be determined as appropriate).
Add the result and send the result to the control unit.

Here, the reason for performing the addition eight times is to average the results of eight AD conversions, and in order to reduce the influence of singular points on the form, the calculation is performed in a scan interval that is n times the scan interval set in advance. It is to calculate the average value. The control section calculates a slice level based on the white peak voltage average and the black peak voltage average, and sends out a 5-bit digital signal S8 for the next row or for rescanning. Note that the setting of the slice level during reading can be changed appropriately not only for each line but also for each character. Next, the DA converter 41 converts the 5-bit signal S8 received from the previous control unit into a DA converter and applies it to the other input side of the comparator 51, thereby producing a signal obtained by sampling and holding the signal S1 from the previous sensor. The slice level is set to S2, and the characters written on the form are quantized and output SlO
It is said that

As explained above, according to the present invention, the slice level can be changed appropriately according to the shading of the characters by providing the circuits as shown in Fig. 2 and making them interrelated, so that it is not affected by the shading of the characters. It can be read as accurate information using a simple circuit.

Furthermore, by setting the slice level based on the average value obtained by adding n peak values in a scanning section that is n times the scanning section, it is possible to reduce the influence of singular points on the form. In addition, the voltage level of the character analog signal fluctuates due to fluctuations in the brightness of the light source in the optical system, but since the slice level can be changed appropriately according to fluctuations in this voltage level, each character can be It has the advantage of being able to obtain accurate information every time. Furthermore, since the peak detection and hold circuit in this embodiment constitutes a closed loop with the first differential amplifier and the second differential amplifier, voltage and phase errors can be reduced. The first field effect transistor connected to the input side of the differential amplifier forms a gate that allows the input signal to pass through only an arbitrary section, so it eliminates the effects of noise and external signals other than the input signal. The second field effect transistor connected to the input side of the first differential amplifier can set the initial reference potential within the signal section to be set, and the second field effect transistor can set the initial reference potential within the set signal interval. It has the advantage that the hold time can be changed as appropriate by the transistor connected to the input side of the dynamic amplifier. As described in detail in the embodiments above, the present invention has the advantage of being able to obtain accurate character information without being affected by variations in the shading of characters or the brightness of the light source. It can be used in photoelectric conversion units such as FAX and POS.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a photoelectric conversion section of a conventional character reading device, FIG. 2 is a block diagram and circuit diagram of an embodiment of the present invention, and FIG.
5 to 5 are signal waveform diagrams of various parts in FIG. 2. 11...Sample hold section, 21...
・White peak detection and hold circuit, 22, 32...
...AD converter, 23, 33...Adder, 24
, 34... 8-bit register, 31...
・Black peak detection and hold circuit, 41...D
A converter, 51... Comparator, Al, A2...
... Differential amplifier, Fl, F2, F2l ... Field effect transistor, TRl, TRll ... Transistor, D1-D4 ... Diode, R1
~R6...Resistance, C1-C5, C, l...
... Capacitor, S1 ... Signal obtained by amplifying the analog signal from the sensor, S2 ... Output signal of sample hold section 11, S3 ... White peak detection and hold circuit 21 output signal, S4...A
Output signal of D converter 22, S5...Adder 23
S6... Averaged output signal of 8-bit register 24, S7... Averaged output signal of 8-bit register 34, S8... Control Output signal from S9...-DA converter 41
output signal, SlO... output signal of comparator 51, Sll... signal section setting signal, Sl2...
... Signal for initial reference potential setting, Sl3, Sl3
...Hold time setting signal, S3l...
- Output signal of black peak detection and hold circuit 31.

Claims (1)

[Claims] 1 A means for sampling and holding an analog signal obtained by a sensor according to the shade of characters on a form, a means for detecting and holding a peak value of a white part on a form in a preset scanning interval of the sensor, means for detecting and holding a peak value of a black portion of a character in a preset scanning section, and an average of each of the n white peak values and the n black peak values in a scanning section that is n times the scanning section; and means for setting a slice level according to the white peak average value and the black peak average value, and quantizes the signal from the sensor according to the slice level. Character reading device.