JPS6142031A - Sorting processor - Google Patents

Abstract

PURPOSE:To execute a merge operation in the time being proportional to the number of data by providing a sorting means for extracting the maximum and the minimum data from plural data, and determining a data train based on an identifier by adding and detaching to and from the sorted data. CONSTITUTION:In an initial sorting stage, an operation in a conventional sorting processing is executed, and plural strings are obtained in a buffer memory 15. Subsequently, in a merge stage, with regard to (k) pieces of strings stored in the buffer memory 15, one data of the maximum or the minimum is outputted as a result of merge by using a sorting circuit 7. Next, the next minimum or maximum data is fetched from the string in which the data outputted as a result of merge has been contained, inputted to the sorting circuit 7, joined together with the remaining data of (k)-1 pieces, and the extracting operation is executed repeatedly plural times. A bank address is cut from (k) pieces of data to which the bank address has been given, and given to an address generating circuit 13, and a data address to be read out in the next time to the buffer memory 15 is determined.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sort processing device, and particularly to a sort processing device that can sort a large amount of data in ascending order or descending order in a short time.

[Prior art]

Sorting is a process of rearranging a collection of obtained data in a predetermined order. Sorting processing in electronic computers means that data given as numerical values or character strings is expressed inside the computer as a binary code of ``OII'' or ``l''.

Based on the numerical meaning of the binary code, the given data are compared with each other, and depending on the magnitude relationship of each data, ascending order (from the smallest to the largest) or descending order (from the largest to the smallest) Traditionally, this kind of sorting process involves sorting the data in the order of
When executed on a general-purpose computer configured with a memory device and central processing unit I (CPU) as its core, data transfer and comparison between the memory device and central processing unit are sequential processes, and two If a large amount of data is to be processed in the sorting process, the time required for the process becomes extremely long due to reasons such as the ability to compare only individual pieces of data.

As a conventional technique for solving the problem regarding the sort processing time, a dedicated sort processing vlW1 is used.

4. There is a method of determining the magnitude relationship by comparison and transmitting data in a wave train to increase the speed. FIG. 2 shows an example of the configuration of a sorting circuit used in the sorting processing device.
and second memory 2, comparison [I3. a flag register 4 for holding the determination result obtained by the comparator 3;
It has a configuration in which a plurality of units 6 consisting of input/output circuits 5 and 5 are connected one-dimensionally, and with the single circuit, mutual comparison and transfer of data can be performed simultaneously in multiple units, so the operation described below is as follows. According to this principle, sorting processing can be performed in a time proportional to the number of data.

FIG. 3 is a diagram showing the operating principle of the sorting circuit shown in FIG. This shows the operation when six pieces of data of I are sorted in descending order.

Note that, in FIG. 3, only the first memory 1, second memory 2, and flag register 4 in FIG. 2 are simply shown, and other circuits are omitted.

In performing the sorting process, first, the contents of memory 1 of I5t and memory 2 of @2 of all units are initialized. At this time, when sorting in descending order, set 0 as the minimum value of the data.

When sorting in ascending order, 9 is set as the maximum value of data. Figure 3 shows the case of sorting in descending order.
In this single circuit, the second memory l9.2 is set to 0, and the sorting process is performed using an input operation that sequentially inputs data and an output operation that sequentially outputs data. In each unit, data is transferred to the right and a comparison is made between two pieces of data. In this case, the data to be transferred are two pieces of data held in the first and second memories 1.2. This is the smaller of the data. At this time.

One piece of data is input to the sorting circuit in synchronization with the data transfer, and the data is input to the first memory 1 or the second memory of the leftmost unit.
The data is held in one of the memories 2 that is emptied by the transfer. (-T1 to T6) When this input operation is repeated and all six pieces of data have been input, the data is sequentially transferred to the adjacent left unit by an output operation. At this time, the data to be transferred is the larger of the two pieces of data in the unit, and 0 is input to the rightmost unit of Iα. (T7~T
12) As described above, data is sequentially input by repeating the input operation, and by executing the output operation when the data input is completed, data is sequentially extracted in descending order starting from the maximum value. In the example of the sorting process described here, by using three units, the sorting of six pieces of data can be performed by the sixth input operation and the sixth output operation, so generally the sorting circuit shown in Figure 2 is used. Now, assuming that there is one input operation and one output operation, and 11, r cycles, ascending or descending sort processing can be performed with the number of input cycles and output cycles equal to the number of data.

1. This sorting circuit is used in an electronic computer. 'f1 side device i! (Sort processing bag WI), when used in, the data to be sorted, which is stored in advance in the memory of the W1 child computer, is sequentially input to the sort processing device via the data transfer path of the computer, Next, the sorted data is sequentially stored in the original memory or the like via the same data transfer path.

In this case, by overlapping the data transfer time to determine the size by comparison, sorting can be performed within the data transfer time, and the time required for sorting can be significantly reduced. .

In the sorting circuit shown in FIG. 2 described above, when L units are connected one-dimensionally to take in two data items per l unit, it is possible to sort up to 2L data items at a time. However, when such a sorting circuit is installed as a peripheral device of a computer, it is necessary to assume in advance the upper limit of the number of data to be processed in the sorting process, and to provide a sufficiently large number of units to correspond to this upper limit. There is a problem in that the scale of the sort processing device becomes large and uneconomical. Furthermore, once the number of units has been determined and the sorting processing device has been configured, there is a problem that the sorting processing device cannot perform sorting that exceeds the permissible number of data. For this reason, conventionally, when a large amount of data needs to be sorted for the first time in t4j, the entire data is divided into pieces that can be sorted by a sort processing device, and then each piece is sorted by the sort processing device. General-purpose needle T! C on the plane
Merge by means of software using PU equipment (
A sorting method called the merge-sort method has been used.

Generally, a data string in which several pieces of data are arranged according to a certain rule is called a string. In the merge sort method, two or more strings are combined into one string and merged. At this time, the number of strings that can be merged at once is called the number of merge ways.If there are currently 16 strings, and the number of merge ways is 2, then
The number of strings decreases from 16 to 8, 4, 2, and 1, and the sorting process ends. - In the same merge operation, a number of data equal to the number of merge ways are compared with each other, and based on the comparison result, all data are moved to be rearranged. In the above example, this merge operation would be 4
The number of merge operations required is determined by the relationship between the number of strings m and the number of merge ways.
km can be obtained, so to merge a total of N data pre-sorted into 1m strings.

NXlogbm data movements are required.

Generally, in a general-purpose computer, the number of merge ways is 2 because the comparison is performed using one CPU device. For this reason, even when a dedicated sort processing device is added to a general-purpose computer, the amount of data is extremely large, and the number of strings is m.
When sorting a large amount of data, multiple merge operations are required, resulting in a huge amount of processing time. Therefore, with the progress of information processing technology for databases today, the number of data items to be processed in sorting processing tends to increase more and more, and the problems of the prior art have been solved. There is a need for a sort processing device with high processing capacity that can flexibly handle extremely large amounts of data. The object of the present invention is to provide a sorting process V&I suitable for sorting a large amount of data.

[Structure and operation of the invention]

The present invention provides a sorting means capable of outputting 1* minimum or maximum data from at least 2 data, and 11* data from among a plurality of sorted data strings. an input processing means for selecting the data string of 1 and extracting the data, attaching an identifier to the extracted data and inputting it to the sorting means; and an output processing for cutting out the identifier from the data extracted by the saw means. The sorting processing device comprises at least means.

The merge operation is performed by determining a data string to be selected by the input processing means based on the identifier obtained by the output processing means. Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 1 is a block diagram of a sort processing apparatus according to an embodiment of the present invention. In the figure, 7 is a sorting circuit, 8 is a control circuit, 9 is an input register, 10 is an output register, and 11 is a bank address generation circuit.

12 is a sort input/output switching circuit, 13 is a read L5 address generation circuit, 14 is a write address generation circuit, 1
5 is a buffer memory, 16 is an address switching circuit, 1
7 is a data switching circuit, 18 is a switching control 1it (
ST), 19 is a bank address (BA), 20 is an I-phase signal line (1), 21 is a ■-phase signal line (n), and 22 is a state control line (INT).

23 is the input control line (PUSH), 24 is the output control line (P
OP), 25 is an input/output control line (PUP).

26 is a data input/output line (DIO).

In the above configuration, the sorting circuit 7 constitutes a sorting means for extracting the minimum value or maximum value.1. The input register 9, the sort input/output switching circuit 12, and the read address generation circuit 13 constitute an input processing means, and the output register 10 and the bank address generation circuit 11. The write address generation circuit 14 constitutes an output processing means.

In this embodiment, the sorting circuit 7 has the same configuration as the sorting circuit shown in FIG. 2.

In this circuit, when the number of units is L, it is possible to sort data having a relationship of L≧/2 (L, k: integer). However, in the present invention.

The second two-toro path is only used as a means to rearrange the unsorted data in Fl order or descending order by repeating the input operation once and repeating the output operation once again, as in the prior art. Rather, it is used as a means for sequentially extracting the smallest or largest data from a set of data when each piece of data is updated. In other words, in the sorting circuit shown in Fig. 2, as explained in Fig. 3, if an input operation is performed on each piece of data in the procedure of sorting in ascending or descending order, the data will not be input.・Because the minimum or maximum data is held in the unit closest to the input/output terminal, 1. This minimum or maximum data can be extracted by performing one output operation after the second. 1 like this
The principle that the minimum and maximum data can be extracted from the data stored by the number of output operations is based on the number of input operations that have already been performed, the number of output operations that have been performed, and the combination of input and output operations. It is guaranteed as long as there is data in the sorting circuit.Therefore, in order to use this sorting circuit as a means to extract the minimum or maximum data as described above, it is necessary to This can be done by performing the input operation in advance and then repeating the output operation and the input operation alternately.Whether to extract the minimum data or the maximum data is determined.

This is set in advance depending on whether the sorting process is to be performed in ascending or descending order.

Next, the operation of the sorting device according to the embodiment of the present invention shown in FIG. 1 will be explained with reference to FIG. 4. The sorting process of the six-piece sorting device includes an initial sorting stage and a merging stage. Consists of. This switch.

This is done by the switching control line (ST) 18, and when 5T18 has a logic level of 11177, it is the initial sorting stage, and when it is "o", it is the merging stage. - At the bottom,
The initial sorting stage (ST = "BI') will be explained. In the initial sorting mN, the unaligned data to be sorted which is obtained from the outside is partially sorted by the sorting circuit 7 to form a string, and the string is stored in the buffer memory 15. 8 At this time, perform the process of storing it in .

Unaligned data is transferred from outside via data input/output line (DID) 26.
are given sequentially via Input this data into register 9
Then, the sorting circuit 7 is manually input via the sorting input/output switching circuit 12. As shown in FIG. 3, the sorting circuit 7 outputs a sorted data sequence, that is, a string, by repeating several input operations and multiple output operations. This string is stored in the buffer memory 15 via the sort input/output q1 switching circuit 12 and the output register IO. Buffer memory 1 at this time
The write address (ADW) No. 5 is generated by the write address generation circuit 14.

As described above, in the initial sorting stage, the present sorting processing apparatus performs operations similar to those in the sorting processing of the prior art shown in FIG.
1 string multiple times within 5! ), the triangles in the buffer memory 15 in FIG. 4 indicate the individual strings obtained in this initial sorting stage, in this figure the case where kl strings were obtained.

Next, the merge stage (ST="O") will be explained.

In the merging stage, by performing the initial operation and normal operation described next, the 2 strings stored in the buffer memory 15 are merged using the sorting circuit 7, and the data input/output line (D I 0 ) 26 to output the data as sorted data.
The minimum or maximum data is taken out from each of the strings stored in the buffer memory 15, and the taken out data are sent to the input register 9 and k
The data is input to the sorting circuit 7 by the input operation twice.

Whether to extract the minimum data or the maximum data is determined by sorting in W order or descending order. In the next normal operation, the smallest or largest piece of data is output as a merge result from the pieces of data input to the sorting circuit 7 through one output operation. At this time, the output data can be sorted in ascending order as above, or sorted in descending order.
I'll do it.

Decide whether to output the minimum data or the maximum data, and output it to the outside as sorted data from the data input/output 8 (DIO) 26 via the sort input/output switching circuit 12 and the output register 10. . Next, the next minimum or maximum data is extracted from the string containing the JJ data output as a merge result and inputted to the circuit 7 of the saw 1.

In addition to the (k-1) pieces of data remaining in the sorting circuit 7, 0 or more operations are performed to extract the second minimum or maximum data among the pieces of data, and the merge result is output in sequence. The margin operation is completed by repeating this until all the data in the string is exhausted.

To repeat the above normal operations 8 times.

An identifier is added in advance to the data input to the sorting circuit 7 by the input processing means for identifying which string the data is extracted from,
Then, by referring to the identifier of the minimum or maximum data output from the sorting circuit 7 by the output processing means, it is determined from which string the data to be input next should be extracted. This identifier only needs to be able to determine which of at least two strings it is, and if it is expressed in binary, then log
,, k bits. This binary-expressed identifier is called a bank address.

Next, a method of assigning bank addresses will be explained. In the initial operation, the bank address is initialized from O to (k
-1) The bank address generation circuit 11 generates 9 addresses, and the input register 9 assigns them to the data to be sorted. By manual operation, the 9 data with the bank addresses assigned are sorted. Output switching circuit 1
2 to the sorting circuit 7. At the time of output, data to which a bank address is assigned from the sorting circuit 7 is sent to the output register 1 via the sorting input/output switching circuit 12.
Stored at 0. Address generation circuit 1 reads out a bank address (that is, an identifier) from this data.
Give to 3: by.

This read address generation circuit 13 determines the address of data to be read next in the buffer memory 15. At this time, the output l nozzle 10? ! )I:.

Data other than the specified identifier (originally attempted to be sorted)

data) is sent via the data switching circuit 17,
Data input/output line (DIO):! When 0 and 2 are output from G, the output data is sorted in 11th order or descending order.

Next, the operation of each part of the tree saw l-processing device in the merging stage will be explained in detail. This sorting processing device.

The entire system is formed by a synchronization cycle yδ using the signals for the (2) phase and (2), and the data of 1-] is rearranged in one cycle from the (2) phase and (4). 20.21 in Figure 1 is right.
These are the phase and ■ phase clock lines. There are 22 status signal lines, and the initial operating status and normal operating status are set by this status signal line 22. If you set the state fll (, No. 1 122 to "l" in the logic 1 novel, it will be in the initial operation state,
In the stage III operation of the initial sorting stage and the merging stage,
It is possible to perform either an operation of successively storing data in the sorting circuit 7 or an operation of successively extracting data in ascending or descending order. When the status signal line 22 is at a logic level of 0'', it is a normal operation state in which data input and output operations are performed alternately and merged.

FIG.

When storing data continuously, the bank address can be uniquely determined by processing such as incrementing from the previous bank address.

As shown in the figure, data can be stored in the sorting circuit 7 twice in one cycle according to the procedure of bank address calculation→read address calculation→data reading. As a result, the storage of data into the sorting circuit 7, which is performed in the initial operation to perform a k-way merge sort, is completed in 2/2 hours.

FIG. 6 is a time chart of a normal operation in which data input processing and output processing to the sorting circuit 7 are performed alternately. By output processing, the bank address is extracted from the data extracted from the two-way road 7.

This is the bank address for the next input data. Determine the read address based on this bank address.1. Reading data from buffer memory 15 and sorting circuit 7
Enter. During the second cycle, data already read out in the previous cycle and held in the manual register 9 is input to the sorting circuit v87. In this way, by shifting data input processing and data output processing by 172 cycles, it is possible to perform address calculation and input/output to the sorting circuit by inserting them. The input/output of one piece of data is completed. Therefore, in a single sort processing device, if the number of data is N, the merge operation can be performed in N cycles.

Next, the detailed circuit configuration of each part of the nine-piece sort processing device will be shown.

　゛ FIG. 7 is a detailed diagram of the control circuit 8 shown in FIG. 1.

In the figure, 27 is reset (, looking at `` (R3T)).

28 is an OR gate, 29 is an ANr) gate, 1IO1
:t inverter, 31 is an up/down counter, and 32 is a flip-flop circuit. up/down counter 3
1 indicates the number of data currently stored in the sorting circuit 7, and the counter value increases or decreases depending on the number of input operations and the number of output operations to the sorting circuit 7. As a result, it is detected that the number of data currently stored in the sorting circuit 7 is 0 pieces, and it is also detected that the number of pieces of data is 0 pieces.
The flip-flop circuit 32 may be set. Set the beam. PU which is the output of the flip-flop circuit 32
The sort input/output switching circuit 12 is controlled by the P signal 25, and the input/output direction of data is determined.

Figure 8 shows the sort input/output switching circuit 12 shown in Figure 1.
The area within the dotted line frame in Figure 1, which is a detailed diagram of , shows only l bits, and 33 is a tri-state buffer gate. When the logic level of the PUr' signal 25 is "BI°", it is an input operation, and the data in the input register 9 is input to the sorting circuit 7.

On the other hand, when the r'Ur' signal 25 is at a logic level of 0'°, it is an output operation, and the data flow is switched in the direction of storing the output data of the two-way path 7 in the output register 10.

FIG. 9 is a detailed diagram of the bank address generation circuit shown in FIG. 1. Reference numeral 371 in FIG. 1 is a counter, which generates continuous bank addresses in the initial operation. Bank address and counter 3 extracted from output register 10
Switching with the address generated in step 4 is performed using the status signal pf line 22.

1O and 11 are detailed diagrams of the address switching circuit 16 and data switching circuit 17 shown in FIG. 1, respectively. In these circuits, the switching control line (
ST) 18 performs switching between addresses and data.

FIG. 12 is a detailed diagram of the read address generation circuit 13 shown in FIG. 1. One circuit consists of two counters 35 and 36.
and multi-bit shift circuit 371-bit addition circuit 38
It consists of Counter 35 is a counter for setting an address indicating which number of data is to be extracted next in each of the 7,1 strings, and this address is called an in-bank address. Counter: 1G
is a counter for generating the address of bits higher than the bank address in the data read address. The multi-bit shift circuit 37 shifts the output of the counter 3G and the bank address (BA) to an arbitrary position,
The output of this shift circuit 37.

The multi-bit adder circuit 38 adds the in-bank address to the read address (ADR in the figure), thereby making it possible to vary the number of data constituting a string at m-th power of 2.

In the processing sorting stage described above, consecutive memory areas are accessed using the initial bank address by moving the bank address to the least significant bit side of the read address using the multi-bit shift circuit 37.

FIG. 13 is a detailed diagram of the write address generation circuit shown in FIG. 1. This circuit is composed of a counter 39, and in the initial sorting stage, it generates write addresses for successively storing data as a result of merging in the buffer memory 15 in synchronization with pop decoding.

The sort processing device of this embodiment explained above is composed of a counter, a switching circuit, an nQl ΔAND gate, an OR gate, etc.
It can be constructed using conventionally known n-way means such as an S transistor.

In the embodiment of the present invention described above, the configuration is shown in which the same sorting means is used to sort the entire data in the initial sorting stage and the merging stage.

The configuration has both a sort "f, p2 which performs an initial sorting stage and a sort 1 stage which performs a merging stage.

Or merge! ! It is also possible to perform a configuration in which only 111 is performed.

In addition, in this embodiment, a case is shown in which several strings are made into one string by one merge operation, but
By providing the buffer memory 15 with a capacity sufficient to store the data to be sorted and the memory *it, it is possible to repeat the merging operation multiple times using one sorting processing device, and it is possible to generate strings with a value greater than or equal to . can also be configured to be easily sortable. Furthermore, by using multiple J+ sort processing devices and connecting them in multiple stages.

Sorting processing can be performed in a shorter time than when a single sorting processing device repeatedly performs merging operations.

In this case, the merge results obtained by multiple previous-stage sorting devices, that is, the strings stored in the buffer memory, are sequentially merged by multiple sorting devices connected so that they are directly input to the next-stage sorting device. By performing this operation, a merge operation can be performed on the wave train, thereby reducing the overall sorting processing time.

In addition, in this embodiment, a case is shown in which the conventional sorting circuit shown in FIG. As a means for extracting the value or minimum value, it is also possible to apply an associative memory or the like.

Further, in this embodiment, it is used as the buffer memory 15.

We have shown the case where randomly accessible memory is used, but it is also possible to store strings in addition to 29, and store sequentially accessible data that can read or write data sequentially from the smallest value or the largest value. You can also apply the means.

In addition, when the sort processing device of this embodiment is connected as an accessory device to a computer, the buffer memory 15 is
A configuration in which it is used in combination with the machine's main memory, etc. is also possible.

Furthermore, in this embodiment, the operation of assigning an identifier to the data input to the sorting circuit 7 is performed after extracting the data from the buffer memory 15. However, when storing the data as one ring in the buffer memory 15, 1. <The configuration is also easy to implement.

〔Effect of the invention〕

As explained above, in the sorting processing device of the present invention, the sort processing apparatus according to the present invention can perform sorting in the "f" stage, which can extract the minimum or maximum data of at least ¥ Y - yen.

a hexagonal processing means for selecting one of the pre-sorted data strings, extracting the data, assigning an identifier to the extracted data, and inputting the extracted data to the sorting means;

A sorting process \i[ is configured with an output processing means for cutting out an identifier from the data 9 extracted by the sorting means,
As a result, it is possible to perform a merge operation with an extremely large number of merge ways, which was not possible with the prior art, in a time proportional to the number of data. In addition to Kosushi, it is now possible to use the same sorting method in combination with initial sorting using the conventional sorting method.With the second feature, even if the number of data to be sorted is large, the entire data can be sorted with a small number of merge operations. , which has the advantage of being able to sort large amounts of data in a short time. In addition, since the data itself is handled by being assigned an identifier (bank address), there is no limit to the number of data that can make up one string. It has the advantage of being able to sort even data.

Furthermore, the sorting processing device of the present invention includes a memory.

It can be configured using conventionally known circuit means such as counters, switching circuits, AND gates, and OR gates, and expands the capacity of the buffer memory. Since the number of data to be sorted can be easily expanded by the above method, it is possible to achieve an extremely high performance ratio (2) compared to expanding the sort processing device according to the prior art.

[Brief explanation of drawings]

FIG. 1 is a sorting process which is the first implementation of the present invention]'II
IV! A configuration diagram of the device, FIG. 2 is a configuration diagram of a conventional sort processing circuit used as a peripheral device of a general-purpose vI machine, and FIG. 3 is a diagram of the operating principle of the sort processing date '111 shown in FIG. 2.
Figure 4 shows l1lI+ of the sorting process νi shield shown in Figure 1.
('+' principle diagram, Figures 5 and 6 are time charts for explaining the operation of the 1st rlI sort processing device, Figure 7 is a detailed diagram of the control circuit in Figure 1, and Figure 8 is the diagram in Figure 1. 9 is a detailed diagram of the bank address generation circuit of FIG. 1, FIG. 10 is a detailed diagram of the address switching circuit of FIG. 1, and FIG. 11 is a detailed diagram of the address switching circuit of FIG. 1. FIG. 12 is a detailed diagram of the read address generation circuit of FIG. 1, and FIG. 13 is a detailed diagram of the write address generation circuit of FIG. 1. 7... Sort Circuit, 8... Control circuit, 9
Manual register, 10...output register,
11... Bank address generation circuit 12... Sort input/output switching circuit, 13... Read, address generation circuit, l/l... Write at L/large generation circuit. 15... Buffer memory, 16... Address switching circuit, 17... Data switching circuit. Fig. 2 Fig. 3 PUP Next Season Y Sufu 10 22 INT HA”TSURETSUADW ADR Fig. 11 r --------/ '1 DW

Claims (2)

[Claims] (1) A sorting means that can store at least k pieces of data (k<1: integer) and extracts the minimum or maximum data from the stored data, and k pieces of data sorted in advance in ascending or descending order. Selecting one data string from among the columns, extracting the minimum or maximum data in the data string and inputting it to the sorting means, and indicating in the input data from which data string the data was extracted. The data string is provided with an input processing means for assigning an identifier, and an output processing means for cutting out the identifier from the data extracted by the sorting means, and selected by the input processing means based on the identifier cut out by the output processing means. 1. A sorting processing device characterized by being configured to perform a merging operation of sorting k data into one data string in ascending order or descending order by determining . (2) The sorting means includes two memory circuits, a comparator that compares the magnitude relationship between the two data stored in the memory circuit, and a comparator that compares the magnitude relationship between the two data stored in the memory circuit, and a L units (L≧k/2: integer) are one-dimensionally connected, each having at least a data input/output circuit for selecting one of the memory circuits and transferring the stored data;
In synchronization with data input and output operations that are sequentially performed from one end of the one-dimensionally connected units, each unit performs a comparison using a comparator and transfers data to an adjacent unit using an input/output circuit in parallel. 2. The sort processing device according to claim 1, wherein the minimum or maximum data is extracted in one output operation from among the k pieces of data stored in the input operation.