JPH0666050B2 - Sort processing method - Google Patents

Description

The present invention relates to a sort processing method, and more particularly to a sort processing method capable of rearranging a large amount of data in ascending order or descending order in a short time.

[Prior art]

Sorting is a process of rearranging a given set of data in a predetermined order. The sort process in an electronic computer means that the data given as a numerical value or a character string is represented by a binary code of "0" or "1" inside the computer, so the numerical meaning of the binary code has First, compare the given data with each other and rearrange the data in ascending order (smallest to largest) or descending order (largest to smallest) depending on the size relation of each data. Conventionally, when such sort processing is executed by a memory device and a general-purpose computer having a central processing unit (CPU) as a core, data transfer and comparison between the memory device and the central processing unit are performed. When the number of data to be sorted is large, it is necessary for the processing because of the sequential processing and the fact that only two data can be compared at a time. But there is a problem that becomes extremely long.

As a conventional apparatus that solves the problem related to the sort processing time, there is a method of using a dedicated sort processing apparatus to determine the magnitude relationship by comparison and transfer data in parallel to increase the speed. FIG. 2 shows a configuration example of a sort circuit used in the sort processing apparatus. This circuit includes a first memory 1 and a second memory 2 for holding data to be compared, a comparator 3, a flag register 4 for holding the determination result obtained by the comparator 3, and It has a configuration in which a plurality of units 6 each comprising an input / output circuit 5 are one-dimensionally connected. In this circuit, data can be compared with each other and transferred simultaneously by a plurality of units, so that the sorting process can be performed in a time proportional to the number of data according to the operation principle described below.

FIG. 3 is an operation principle diagram of the sorting circuit shown in FIG. 2, and as an example, out of the one-digit numerical data up to 0 to 9,
It shows an operation in the case of sorting six pieces of data of 6,5,2,4,1 in descending order. In FIG. 3, the first memory 1 and the second memory 2 and the flag register 4 in FIG.
However, other circuits are omitted.

When performing the sorting process, first, the contents of the first memory 1 and the second memory 2 of all units are initialized. At this time, when sorting in descending order, 0 is set as the minimum value of data, and when sorting in ascending order,
Set 9 as the maximum value of the data. FIG. 3 shows a case of sorting in descending order, and 0 is set in the first and second memories 1 and 2. In this circuit, sort processing is performed by an input operation of sequentially inputting data and an output operation of sequentially outputting data. In each unit, data is transferred to the right and two pieces of data are transferred in each unit. Compare with each other. In this case, the data to be transferred is the smaller of the two data held in the first and second memories 1,2. At this time, one piece of data is input to the sort circuit in synchronization with the data transfer, and one of the first memory 1 and the second memory 2 of the leftmost unit which has become empty due to the transfer. Hold in memory. (T1 to T6) When this input operation is repeated and all six pieces of data have been input, the output operation sequentially transfers the data to the adjacent unit on the left side. At this time, the data to be transferred is the larger of the two data in the unit, and 0 is input to the rightmost unit. (T7 to T12) As described above, the data is sequentially input by repeating the input operation, and the output operation is executed when the data input is completed, so that the data is sequentially extracted from the maximum value in the descending order. In the example of the sorting process described here, the rearrangement of 6 pieces of data is performed by using 3 units.
Since it can be done with 6 input operations and 6 output operations,
Generally, in the sorting circuit of FIG. 2, if one input operation and one output operation are regarded as one cycle, ascending or descending sort processing can be performed with the number of input cycles and the number of output cycles equal to the number of data.

When this sort circuit is used as a peripheral device (sort processing device) of an electronic computer, the data to be sorted, which is held in advance in the memory of the electronic computer, is sent to the sort processing device via the data transfer path of the electronic computer. The sequentially input data and the sorted data are sequentially stored in the original memory or the like via the data transfer path. In this case, the sorting process can be performed almost in the data transfer time by superimposing the data transfer time and the comparison to determine the size, and the time required for the sorting process can be significantly reduced.

In the sorting circuit of FIG. 2 explained above, in order to take in two data per unit, when L units are connected in one dimension, a maximum of 2L data can be sorted at one time. However, when such a sort circuit is provided as a peripheral device of an electronic computer, it is necessary to preliminarily assume an upper limit of the number of target data in the sort process and provide a sufficiently large number of units corresponding to this. There is a problem that the size of the sort processing device becomes large and uneconomical. Further, once the number of units is determined and the sort processing device is configured, there is a problem that the sort processing device cannot perform sorting exceeding the allowable number of data. Therefore, in the past, when it was necessary to sort an extremely large amount of data, after dividing the entire data into a size that can be sorted by the sort processing device, each was sorted by the sort processing device and the entire data was sorted on a general-purpose computer. A sorting method called the merge sheet method has been adopted in which the CPU device of the above is used to merge by software means.

Generally, a data string in which some data are arranged according to a certain rule is called a string. In the merge sort method, two or more strings are merged as one string. At this time, the number of strings that can be merged at one time is called the number of merge ways. Now there are 16 strings
If the number of merge ways is 2, the number of strings decreases from 16 to 8, 4, 2, 1 and the sorting process ends. In one merge operation, the same number of pieces of data as the number of merge ways are compared with each other, and all the pieces of data are moved to be rearranged based on the result of the comparison. In the above example, this merge operation is performed four times, and the number of merge operations required is given by logkm from the relationship between the number of strings m and the number of merge ways k. Therefore, in order to merge N pieces of data presorted into m pieces of strings, N × logkm
It is necessary to move the data once.

Generally, in a general-purpose computer, the number of merge ways k is 2 because one CPU device performs comparison. For this reason, even when a dedicated sort processing device is added to a general-purpose computer, when a large amount of data and a large number of strings m are sorted, a plurality of merge operations are required. Therefore, there has been a problem that a huge amount of processing time is required. Therefore, the number of pieces of data targeted for sort processing tends to increase more and more with the progress of information processing technology for databases today. There is a demand for a sort processing device having a high processing capacity that can deal flexibly.

[Object of the Invention]

An object of the present invention is to eliminate the above-mentioned problems of the prior art and to provide a sort processing method suitable for sort processing on an extremely large amount of data such as a database.

[Structure and Action of Invention]

The sort processing apparatus of the present invention includes a memory means for storing a plurality of data strings sorted in ascending order or a descending order, and a minimum or maximum data from each of the plurality of data strings in the initial operation, and the plurality of data strings in the normal operation. One of the data strings is selected, the minimum or maximum data in the data string is taken out, an identifier for identifying the data string to which the data belongs is added to the taken out data, and the data is sorted. Input processing means for inputting, a plurality of data with identifiers input from the input processing means, a sorting means for storing the minimum or maximum data from the stored data, adding an identifier and outputting An identifier is cut out from the data with an identifier outputted from the sorting means, and the cut out identifier or its related information is It is characterized in that an output processing means for providing to said input processing means to determine a data sequence to be selected. An embodiment of the present invention will be described in detail below.

FIG. 1 is a block diagram of a sort processing apparatus according to an embodiment of the present invention. In the figure, 7 is a sort circuit, 8 is a control circuit, 9 is an input register, 10 is an output register, 11 is a bank address generation circuit, 12 is a sort input / output switching circuit,
13 is a read address generation circuit, 14 is a write address generation circuit, 15 is a buffer memory, 16 is an address switching circuit, 17 is a data switching circuit, 18 is a switching control line (ST), 19 is a bank address line (BA), 20 Is the I-phase signal line (I), 21 is the II-phase signal line (II), 22 is the line control line (IN
T), 23 is an input control line (PUSH), 24 is an output control line (POSH)
P), 25 are input / output control lines (PUP), and 26 is a data input / output line (DIO).

In the above configuration, the sorting circuit 7 constitutes a sorting means for extracting the minimum value or the maximum value, and the input register 9, the sorting input / output switching circuit 12 and the read address generating circuit 13 constitute an input processing means, Output register 10
The bank address generating circuit 11 and the write address generating circuit 14 constitute an output processing means.

In this embodiment, as the sorting circuit 7, a circuit having the same configuration as the sorting circuit shown in FIG. 2 is applied. In this circuit, when the number of units is L, L ≧ k / 2 (L, k: integer)
The k pieces of data having the relationship of can be sorted. However, in the present invention, this sorting circuit is k
Not only is it used as a means for rearranging the k non-aligned data in ascending or descending order by repeating the input operation once, and then repeating the output operation k times. The difference is that it is used as a means for sequentially extracting the minimum or maximum data from a set of data. That is, in the sorting circuit of FIG. 2, as described in FIG. 3, when k times of input operation is performed on k pieces of data in the procedure of performing the sorting process in ascending order or descending order, the data is input. The minimum or maximum data is stored in the unit closest to the I / O terminal. Therefore, the minimum or maximum data can be extracted by performing one output operation thereafter.
The principle of extracting the minimum or maximum data of the stored data by one output operation is based on the number of input operations already performed, the number of output operations, and the combination of input operation and output operation. Is not dependent and is guaranteed as long as the data exists in the sort circuit. Therefore, in order to use this sort circuit as a means for extracting the minimum or maximum data as described above, after performing k input operations on k data in advance, output operations and input operations are alternately repeated. It can be done by It should be noted that whether to extract the minimum data or the maximum data is set in advance depending on whether the direction for performing the sorting process is ascending order or descending order.

Next, the operation of the sorting method of the embodiment of the present invention shown in FIG. 1 will be described with reference to FIG. The sort process of this sort processing apparatus includes an initial sort stage and a merge stage. This switching is performed by the switching control line (ST) 18, and when ST18 is "1" in the logical level, it is the initial sort stage, and when it is "0", it is the merge stage.

First, the initial sort stage (ST = “1”) will be described. In the initial sorting stage, the sorting circuit 7 partially sorts non-sorted data to be sorted from outside to form a string and stores the string in the buffer memory 15. At this time, the unaligned data is sequentially applied from the outside via the data input / output line (DIO) 26. This data is sequentially input to the sorting circuit 7 via the input register 9 and the sorting input / output switching circuit 12. In the sorting circuit 7,
As shown in FIG. 3, a sorted data string, that is, a string is output by repeating a plurality of input operations and a plurality of output operations. This string is stored in the buffer memory 15 via the sort input / output switching circuit 12 and the output register 10. At this time, the write address (ADW) of the buffer memory 15 is the write address generation circuit 1
Generated by 4.

As described above, in the initial sort stage, the same sort of operation as in the sort process of the prior art shown in FIG. 3 is performed by this sort processing apparatus to obtain a plurality of strings in the buffer memory 15. be able to. The triangles in the buffer memory 15 of FIG. 4 show the individual strings obtained in this initial sorting stage, which is the case where k strings have been obtained.

Next, the merge stage (ST = “0”) will be described. In the merging step, the k strings stored in the buffer memory 15 are merged by using the sort circuit 7 by performing the initial operation and the normal operation described below, and the data input / output line (DIO) 26 Performs processing to output as sorted data. Introduction In the initial operation, the buffer memory 15
The minimum or maximum data is extracted from each of the k strings given to, and the extracted k data is input to the sorting circuit 7 via the input register 9 by k times of input operation. Whether to extract the smallest data or the largest data is determined by sorting in ascending order or descending order. In the next normal operation, one minimum or maximum data is output as a merge result from the k pieces of data input to the sorting circuit 7 by one output operation. At this time, the output data is sorted in ascending order or descending order in the same manner as described above, and it is determined whether the minimum data or the maximum data is output, and the sort input / output switching circuit 12 and the output register 10 are set. The data is output to the outside from the data input / output line (DIO) 26 as sorted data. Next, the next minimum or maximum data is extracted from the string that contained the data output as the merge result and is input to the sorting circuit 7 and combined with the (k-1) data remaining in the sorting circuit 7. Then, the second minimum or maximum data is extracted from the k pieces of data. The margin operation is completed by repeating the above operation until all the data in the k strings are output while sequentially outputting the merge result.

When the above normal operation is repeatedly performed, an identifier for identifying from which string the data is extracted is previously added to the data input to the sorting circuit 7 by the input processing means, and the sorting circuit By referring to the identifier of the minimum or maximum data output from 7 by the output processing means,
It can be determined from which string the data to be entered next should be retrieved. This identifier only needs to be able to discriminate which one of at least k strings, and when it is expressed in binary, log ₂
It becomes k bits. This binary representation of the identifier is called a bank address.

Next, a method of assigning a bank address will be described. In the initial operation, the bank address is initialized from 0 to (k
-1) up to k addresses for bank address generation circuit
The data generated at 11 and added to the sort target data by the input register 9 and k data to which the bank address is added by the input operation are input to the sort circuit 7 via the sort input / output switching circuit 12. At the time of output, the data to which the bank address is assigned from the sort circuit 7 is stored in the output register 10 via the sort input / output switching circuit 12. Bank address (ie identifier) from this data
Is cut out and supplied to the read address generation circuit 13, so that the read address generation circuit 13 determines the address of the data to be read next in the buffer memory 15. At this time, the data other than the identifier obtained in the output register 10 (the data originally intended to be sorted) is transferred via the data switching circuit 17 to the data input / output line (DIO) 2
Output from 6. At this time, the output data is sorted in ascending order or descending order.

Next, the operation of each part of this sort processing apparatus in the merge stage will be described in detail. This sort processing device is entirely composed of a synchronizing circuit based on I-phase and II-phase signals.
One data is rearranged in one cycle consisting of phases. Reference numerals 20 and 21 in FIG. 1 denote I-phase and II-phase clock lines, respectively. Reference numeral 22 is a state signal line, and the state signal line 22 sets an initial operation state and a normal operation state. Status signal line
When 22 is set to “1” at the logical level, it is in the initial operation state, and in the initial operation of the initial sort stage and the merge stage,
Either the operation of continuously storing data in the sorting circuit 7 or the operation of continuously extracting data in ascending or descending order can be performed. When the state signal line 22 is "0" at the logic level, it is a normal operation state in which data input operation and output operation are alternately performed and merged.

FIG. 5 is a time chart showing the operation of the initial operation of successively storing data in the sorting circuit 7. When data is stored consecutively, the bank address can be uniquely determined from the immediately preceding bank address by processing such as incrementing. Therefore, as shown in the figure, calculation of bank address → calculation of read address → data Data can be stored in the sorting circuit 7 twice in one cycle according to the reading procedure. As a result, the storage of the k pieces of data in the sorting circuit 7 performed in the initial operation for performing the k-way merge sort is completed in k / 2 cycles.

FIG. 6 is a time chart of a normal operation in which the sorting circuit 7 alternately performs data input processing and data output processing. By the output processing, the bank address is cut out from the data extracted from the sorting circuit 7 and is set as the bank address of the next input data. A read address is determined based on this bank address, data is read from the buffer memory 15 and input to the sort circuit 7.

Next, a detailed circuit configuration of each section of the present sorting apparatus will be shown.

FIG. 7 is a detailed diagram of the control circuit 8 shown in FIG.
In the figure, 27 is a reset signal line (RST), 28 is an OR gate, 2
9 is an AND gate, 30 is an inverter, 31 is an up / down counter, and 32 is a flip-flop circuit. The up / down counter 31 indicates the number of data currently stored in the sorting circuit 7, and the counter value increases or decreases depending on the number of input operations and the number of output operations to the sorting circuit 7. As a result, it is detected that the number of data currently stored in the sort circuit 7 is 0 or k, and the flip-flop circuit 32 is set or reset. PUP which is the output of the flip-flop circuit 32
The sort input / output switching circuit 12 is controlled by the signal 25,
Determine the data input / output direction.

FIG. 8 is a detailed diagram of the sort input / output switching circuit 12 shown in FIG. Only one bit is shown in the dotted frame in the figure, and 33 is a tri-state buffer gate.
When the PUP signal 25 has a logical level of "1", it is during an input operation, and the data of the input register 9 is used as the input of the sort circuit 7. On the other hand, when the logical level of the PUP signal 25 is "0", it is during the output operation, and the data flow is switched to the direction in which the output data of the sort circuit 7 is stored in the output register 10.

FIG. 9 is a detailed diagram of the bank address generating circuit 11 shown in FIG. Reference numeral 34 in the figure is a counter, which generates continuous bank addresses in the initial operation. Output register
Switching between the bank address cut out from 10 and the address generated by the counter 34 is performed by the status signal line 22.

10 and 11 are detailed diagrams of the address switching circuit 16 and the data switching circuit 17 of FIG. 1, respectively.
In both of these circuits, the switching control line (ST) 18 switches between address and data.

FIG. 12 is a detailed diagram of the read address generation circuit 13 of FIG. This circuit is composed of two counters 35 and 36, a multi-bit shift circuit 37, and a multi-bit adder circuit 38. The counter 35 is a counter for setting an address of which number of data is to be extracted next for each of the k strings, and this address is called an in-bank address. The counter 36 is a counter for generating an address of a bit higher than the bank address in the data read address. The multi-bit shift circuit 37 shifts the output of the counter 36 and the bank address (BA) to an arbitrary position, and the output of this shift circuit 37 is added to the in-bank address by the multi-bit adder circuit 38 to obtain the read address. (ADR in the figure). This allows
The number of pieces of data forming a string can be made variable in units of powers of two. In the processing sort stage described above, the multi-bit shift circuit 37 moves the bank address to the least significant bit side of the read address to access the continuous memory area using the initial bank address.

FIG. 13 is a detailed diagram of the write address generation circuit 14 of FIG. This circuit is composed of a counter 39, and in the initial sort stage, a write address for storing the data as a merged result obtained in synchronization with the POP signal sequentially and continuously in the buffer memory 15 is generated.

The sort processing device of the present embodiment described above is composed of a counter, a switching circuit, simple AND gates, OR gates, etc., so that it can be constructed using conventionally known circuit means such as bipolar transistors and MOS transistors.

In the embodiment of the present invention described above, the same sort means is used to perform the sorting process of the entire data in the initial sort stage and the merge stage. However, the sort unit and the merge stage that perform the initial sort stage are performed. It is also possible to adopt a configuration that includes both sort means, or to perform only the merge step.

Further, in the present embodiment, a case has been shown in which k strings are converted into one string by one merge operation.
By providing the buffer memory 15 and the memory device having a capacity sufficient to store the data to be sorted, even if there are K or more strings by repeating the merge operation a plurality of times using this sort processing device. It can be configured to be easily sorted. Furthermore, by connecting a plurality of the present sort processing devices in multiple stages, the sort processing can be performed in a shorter time than the case where the merge operation is repeatedly performed by one sort processing device. In this case, the merge results obtained by a plurality of sort processing devices at the preceding stage, that is, the strings stored in the buffer memory are directly merged by a plurality of sort processing devices connected so as to be directly input to the sort processing device at the next stage. By performing the operation, the merge operation can be executed in parallel, so that the total sort processing time can be shortened.

In the present embodiment, the case where the sorting circuit according to the prior art shown in FIG. 2 is applied as a means for extracting the maximum value or the minimum value from k pieces of data in a short time is shown.
An associative memory or the like can be applied as a means for extracting the maximum value or the minimum value.

Further, in the present embodiment, the case where a randomly accessible memory is used as the buffer memory 15 is shown, but in addition to this, a string is held, and sequential access capable of sequentially reading or writing data from the minimum value or the maximum value is possible. It is also possible to apply various data holding means. When the sort processing device of this embodiment is connected as an auxiliary device of a computer, the buffer memory 15
It is also possible to use the computer together with the main memory of the computer.

Further, in the present embodiment, the operation of assigning the identifier to the data input to the sort circuit 7 is illustrated after the data is extracted from the buffer memory 15.
It is also possible to easily implement a configuration that is given in advance when storing it in 15 as a string.

〔The invention's effect〕

As described above, in the sorting method of the present invention, the memory means for storing a plurality of sorted data strings in ascending or descending order, and the initial operation to extract the minimum or maximum data from the plurality of data strings, respectively, In a normal operation, one data string of the plurality of data strings is selected, the minimum or maximum data in the data string is extracted, and the extracted data is assigned an identifier for identifying the data string to which the data belongs. Input processing means for adding and inputting to the sorting means, and a plurality of data with identifiers input from the input processing means can be stored, the minimum or maximum data is extracted from the stored data, and an identifier is added. And outputting the sorted identifier, the identifier is cut out from the identifier-added data output from the sorting means, and the cut-out identifier Alternatively, since the related information is composed of the output processing means to be given to the input processing means for determining the data string to be selected next, the merge operation with the extremely large number of merge ways, which cannot be done by the conventional technique, can be performed. It can be carried out in a time proportional to the number of data. At the same time, the same sort means can be used together with the initial sort by the conventional sort method, so that even if the number of data to be sorted is large, the entire data can be sorted with a small number of merge operations.
It has the advantage that a large amount of data can be sorted in a short time. Also, the data itself has an identifier (bank address)
In order to handle an extremely large amount of data that cannot be handled by a conventional sort processing device, it is possible to sort the number of data making up one string. .

[Brief description of drawings]

FIG. 1 is a block diagram of a sort processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional sort processing circuit used as a peripheral device of a general-purpose computer, and FIG. 3 is shown in FIG. FIG. 4 is an operation principle diagram of the sort processing circuit, FIG. 4 is an operation principle diagram of the sort processing device shown in FIG. 1, and FIGS.
FIG. 7 is a detailed diagram of the control circuit of FIG. 1, FIG. 8 is a detailed diagram of the sort input / output switching circuit of FIG. 1, and FIG. FIG. 10 is a detailed diagram of the bank address generating circuit, FIG. 10 is a detailed diagram of the address switching circuit of FIG. 1, FIG. 11 is a detailed diagram of the data switching circuit of FIG. 1, and FIG. 12 is a read address of FIG. FIG. 13 is a detailed diagram of the generating circuit, and FIG. 13 is a detailed diagram of the write address generating circuit in FIG. 7 ... Sort circuit, 8 ... Control circuit, 9 ... Input register, 10 ... Output register, 11 ... Bank address generation circuit, 12 ... Sort input / output switching circuit, 13 ... Read address generation circuit, 14 ...... Write address generation circuit,
15 …… buffer memory, 16 …… address switching circuit,
17 ... Data switching circuit,

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadamichi Kawada 3-9-11 Midoricho, Musashino-shi, Tokyo Inside Nippon Telegraph and Telephone Public Corporation Musashino Electro-Communications Research Laboratory (56) Reference JP-A-58-87630 (JP, A) Actual Development Sho 59-58852 (JP, U)

Claims (1)

[Claims] 1. A minimum or maximum data is extracted from k (k> 1) data strings pre-sorted in ascending or descending order given as input, and the data string to which the data belongs is identified from the extracted data. Input means for inputting data with an identifier to which a data string identifier is added to a sort means described later, two storage circuits for storing the input data with the identifier, and two identifiers stored in the storage circuit. A comparator that determines the magnitude relation of data and one of the two storage circuits is selected based on the determination result of the comparator, and the data with an identifier stored in the selected storage circuit is transferred. Data input / output circuit for at least L units (L ≧ k / 2: integer) are connected in a one-dimensional manner, and the units are connected in order from one end of the one-dimensionally connected unit. In synchronization with the input operation and the output operation of the data to be performed, the comparison by the comparator and the transfer to the adjacent unit by the data input / output circuit are performed in parallel in each of the units, so that the k stored data are stored. Sorting means for selecting and outputting the minimum or maximum data from the data with an identifier in one output operation, and the data with an identifier output from the sorting means is separated into an identifier and a data part, and the separated identifier And an output processing means for outputting the separated data part as an output to the input means, and in an initial operation, the input means is used to output 1 from each of the k data strings. The maximum or minimum data is extracted one by one, and the data with an identifier provided with an identifier is input to the sorting means. The minimum or maximum identifier-added data is selected and output using a step, and the output unit cuts out the identifier from the output identifier-added data, and the input unit indicates the cut-out identifier. A sorting method, characterized in that the process of extracting the data to be inputted to the sorting means next from the data string is repeated.