JPS6140652A - Method and circuit for write protection of memory - Google Patents

Abstract

PURPOSE:To protect a memory from data write by programming a write instruction twice repeatedly and adding a circuit consisting of a comparator and DFF to the memory and performing comparison by the comparator. CONSTITUTION:Data on a data bus 1 is stored in a DFF8 so that the DFF gets the rise of a write signal 4 from a CPU to write this data in a memory 9. At this time, the signal 4 is inputted as a signal 10 to a comparator 7, and the signal 10 is outputted as a write signal 6 to the memory 9 only when it coincides with data inputted to the P terminal and the Q terminal of the comparator 7. Next, the CPU outputs the write signal 4 again, and the DFF8 outputs the preceding stored contents to a bus 11 by this signal 4. Data inputted to the P terminal and the Q terminal of the comparator 7 coincide with each other at this time, and the signal 6 is outputted to the memory 9, and data on the bus 1 is written in the memory 9. Thus, the memory is protected from data write.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory writing method and circuit provided for a CPU system, and in particular to a method that can prevent memory contents from being destroyed due to CPU abnormality. and circuits.

[Prior art] In order to maintain the reliability of a CPU system, it is necessary to prevent the destruction of data stored in memory due to CPU runaway, that is, to prevent abnormal writing. .

Therefore, in order to prevent the write signal from being input to the memory, conventionally known methods include providing a switch to cut off the write signal line and providing a write check subroutine in the CPU program.

In this field, there are proposals such as JP-A-55-98594, JP-A-57-86195, and JP-A-58-23898.

[Problem that the invention seeks to solve]

However, the above-mentioned means for providing a switch has the problem that a switch is required, and it also requires time and effort to switch the switch when necessary.

The method of providing subroutines has the problem that the program becomes complicated and the processing time increases.

[Failure to solve the problem]

In order to solve the above-mentioned problems, the present invention makes it possible to repeat a write command with the same content twice when the CPU writes to memory, and to temporarily hold the data to be written by the first command. Install flip-flops,
Furthermore, a comparator is provided to compare the data to be written by the 2JJt-th instruction with the contents of the D flip-flop, and the data is written to the memory only when the comparison result by this comparator shows that they are the same.

[Example] A specific example of the present invention will be described below with reference to FIG.

In Figure 1, ■ is a data bus, 2 is an address bus,
3 is the memory select (chip enable) signal f (CB
), 4 and 6it write=Ml (WR), 5 is a read signal (lower ■), 7 is a comparator, 8 is a D flip-flop, and 9 is a memory IJ (RAM).

Now, when the CPU (not shown) issues write signal 4, D
Flip-flop 8 captures the rising edge of the signal and stores the data on data bus 1 to be written into memory 9.

At this time, the write signal 4 is input as a signal 10 to the gate G of the comparator 7, and only when the data input to the P terminal of the comparator 7 and the data input to the Q terminal of the comparator 7 match, The write signal 6 is not output to the memory 9 as the write signal 6.

At this point, data has been input to the P terminal of the comparator 7, but no data has yet been input to the Q terminal of the comparator 7.

Next, the CPU issues write signal 4 again.

Specifically, the program is programmed in advance by repeating the write command twice, such as LD MEMORY, A LD MEMORY, A.

As a result, when the second write signal 4 is issued, the D flip-flop 8 receives it and outputs the previously stored contents to the bus 11.

At this time, the data input to the P terminal of the comparator 7 and the data input to the Q terminal of the comparator 7 match for the first time, a write signal 6 is issued to the memory 9, and the data on the data bus 1 is transferred to the memory 9. written to.

This situation is shown in FIG. 2 as a time chart.

In Figure 2, X and A are data values, and the previous data The figure shows how a write signal 96 is issued only when the write and current data are the same (in this case, both are A) (see (b)).

In other words, unless the CPU repeatedly issues the write signal in this way, data will not be written to the memory, so if the CPU malfunctions and the second write signal is not issued, no writing will be performed and the data will not be written to the memory as before. The memory contents of are protected.

[Other Embodiment J] In the comparison with the above example, if you are concerned about memory protection, use an inverting output type element 9 for the D flip-flop 8, and run the program by 'CMA' (the contents of the achievator). Reversing) LD MEMORY, AMA LD MEMORY, A will further improve reliability.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of making it possible to write protect the memory by simply adding an extremely simple and inexpensive circuit consisting of a comparator and a D flip-flop to the write-instruction memory.

[Brief explanation of the drawing]

FIG. 1 is a specific embodiment of the present invention, and FIG. 2 is a time chart of the present invention. 7: Comparator 8: D flip-flop 9: Memory Figure 1 Data on data bus 1 [II3m==a==] Data at P terminal of combo barre 97 FJ=[1713m8=
] Comparator Y6"A71' to register 5 -9 "ku=1=N"
=71. Engineering 73. .

Claims (2)

[Claims] (1) When the CPU writes data to memory, the same write command is programmed twice in a row in advance in the program executed by the CPU, and the data to be written by the first command is externally written. The feature is that the data is once held in the circuit, and the second instruction compares the once held data with the data to be written in the external circuit, and only when they match, the data is written to the memory. How to write protect memory. (2) When the CPU inputs the write signal to be issued to the memory and the D flip-flop temporarily holds the data to be written, and when the output of this D flip-flop and the data to be written are compared and match. A write protection circuit for a memory, comprising: a comparator that issues a write signal to the memory.