JPS613544A - Synchronizing clock reproducing device - Google Patents

Abstract

PURPOSE:To obtain a data extraction pulse not affected by various elements of a transmission system by obtaining synchronizing information from transmission data itself. CONSTITUTION:A clock pulse CLK having a transmission speed four times that of data is applied to a quad counter 8 from a clock generating circuit 3. A decoder 9 outputs pulses D2, D2, D3 respectively when the value of the counter 8 is 0, 2, 3. When an edge detection pulse ED is obtained from a gate 5 with a count value of 0, a pulse is generated, then the counter 8 is cleared and the count is paused once. When the detection pulse ED is obtained with a count value of 2, a pulse is obtained from the gate 6, the counter 8 is cleared and the count value is advanced by 1. Thus, in applying the pulse D3 to a data extraction circuit 11 as a data extraction pulse, the original data is extracted correctly.

Description

[Detailed Description of the Invention] Industrial Application Field This invention is applicable to serial transfer of digital data.
The present invention relates to a synchronous clock reproducing device for obtaining a synchronous clock used when extracting the digital data on a receiving side.

Background technology and its problems For example, in a computer, data processing is performed by one word (
However, data communication between computers or between terminals is usually performed by serial data transfer. In this case, on the receiving side, the data is inversely converted into data in units of one word, but since it is serial data, it is necessary to synchronize each word.

As this synchronization method, for example, a start-stop synchronization method is generally used. MODE is a typical example of this asynchronous transmission.
R5-2 used between M and computer terminals
There is a 32C (f!IA standard) interface, which provides a 1-bit start bit before 1 byte (8 bits) of data, and determines the timing of capturing subsequent data based on this.

By the way, in this method, there is no problem if there is no change in the data following the start bit such as phase shift, but
Due to the characteristics of the data transmission line and signal circuit system, or due to the influence of various characteristics such as electromagnetic conversion and rotational unevenness when data is passed through a magnetic recording and reproducing system, phase fluctuations occur in the data, so it is determined by the start bit. The data capture timing may not necessarily be appropriate for each bit of all subsequent data, and the original data cannot be reproduced correctly, resulting in a transmission error. This is particularly noticeable in systems where the data length (number of bits) for one word is long. For this reason, conventionally, it has been necessary to strictly match the characteristics of the signal transmission system.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a synchronous clock reproducing device that can reliably reproduce original data on the receiving side even when phase distortion occurs in a serial data transmission system.

Summary of the Invention This invention provides N (N is 3) for 1 bit of original data.
A clock generation circuit that generates a reference clock signal with a frequency including clock pulses (an integer greater than or equal to and when the number of the clock pulses included between the edges of the transmission data is less than an integer multiple of N, the count value of the counter is advanced by an extra amount, and when it is more than an integer multiple of N, is a synchronous clock regeneration device that pauses the count value by a predetermined count value and obtains a pulse for extracting transmitted data when the count value is a specific value, and improves the reliability of the data transmission system. This technique reduces the number of man-hours required to precisely match or adjust various elements of a transmission system.

Embodiment FIG. 1 shows a system diagram of an embodiment of the apparatus of this invention.

In this example, the transmitted serial data TR
DA (FIG. 2C) is supplied to the noise cancellation circuit (2) through the input terminal fi+. In this case, serial data TR
For example, D^ is data that has passed through a magnetic recording and reproducing system,
The original data 0RDA (B in the same figure) has been subjected to phase fluctuations.

The noise removal circuit (2) also has a data transmission speed of 4
Clock pulse CLK with a frequency that is twice as high, that is, 4 clock pulses are included for 1 bit of the original data.
(FIG. 2A) is supplied from the clock generation circuit (3). In this noise removal circuit (2), the data T
When the pulse width of RDA is less than three clock pulses CLK, this is removed as noise. This is because the clock pulse CLK is four times faster than the data transmission speed, and since there is no case where there are less than 3 pulses in the data pulse width, it can be considered noise, and because the edge information of the data TRDA is used in the subsequent stage. This is to prevent malfunctions caused by this noise.

Figure 3 shows an example of this noise removal circuit, which uses three 07971
It consists of a 7071 circuit (21) (22) (23), two AND gates (24) (25), and a JK flip-flop circuit (26).

Clock pulse CLK (
Figure 4A) shows three 079717071 circuits (21)
(22) is supplied to the clock terminal of (23).

Further, transmission data TRDA (FIG. 4B) which is not synchronized with this clock pulse CLK is supplied to the D terminal of the 079717071 circuit (21). Therefore, this circuit (
21), a delayed signal of the data TRD^ synchronized with the rising edge of the clock pulse CLK is obtained as an output Qr (C in the figure). This output Q1 is supplied to the D terminal of the 079717071 circuit (22), so it is roughly 1
A signal delayed by one clock is obtained as the output Q2 (D in the same figure), and this output Q2 is further supplied to the D terminal of the D Frisopfromp circuit (23), and a signal delayed by one clock is obtained as the output Q3 (E in the same figure). ) is obtained as And these 079717071 circuits (21), (
22).

The outputs Ql, Q2, and Q3 of (23) are each inverted in polarity and supplied to the AND gate (24), from which the output As has a falling edge at the rising edge (excluding noise) of the output Q1 (FIG. F). is obtained.

Also, the output Q1+Q2. Q3 are each supplied to the AND gate (25) as they are, and from this, an output A2 (G in the same figure) having a falling edge at the falling edge of the output Q1 (excluding noise) is obtained.

The outputs A1 and A2 of these AND gates (24) and (25) are respectively supplied to the J terminal and the terminal of the JK flip-flop circuit (26), and the clock pulse CLK is supplied to this JK flip-flop circuit (26). The noise component is removed from the serial data TRDA and the data TR
Output 5Y with DA synchronized to clock pulse CLK
DA (FIG. 4 H1, FIG. 2 D) is obtained.

This output is supplied to the 5YDA & edge detection circuit (4).

Also, the clock pulse CLK is applied to this edge detection circuit (4).
), from which a detection pulse ED (FIG. 2E) that rises at the rising and falling edges of the output 5YDA is obtained.

Edge detection pulse ED is AND gate (5) and (6)
Furthermore, it is supplied to the clear terminal of the quaternary counter (8) through the OR gate (7).

On the other hand, a clock pulse CLK from a clock generation circuit (3) is supplied to a clock terminal of this quaternary counter (8), and the count value information is supplied to a decoder (9). In this decoder (9), the counter (8)
The pulse D o + D 2 becomes "1" when the count values at are l-0J, 'r2J, and r3J, respectively.

D3 (having a pulse width of one clock) is obtained. Then, the pulse Do is supplied to the AND gate (5), and the pulse D2 is supplied to the AND gate (6). Therefore, from the AND gate (5), the count value is "0".
”, if the edge detection pulse ED is obtained, “1
An output of "0" is obtained, which clears the counter (8), and the count value remains at "0" even when the next pulse CLK is supplied. In other words, the counter (8) stops counting the pulses C and LK once. Additionally, the AND gate (6) outputs an output that becomes "L" when an edge detection pulse is obtained when the count value is "2", which clears the counter (8) and generates the next pulse. At CLK, the count value is set to "0". In other words, the count value of the counter (8) can be advanced by "1".

Further, the pulse D3 is supplied to the data extraction circuit (11) as a data extraction pulse via an OR gate.

Assuming that the data TRDA is equal to the original data without any phase deviation, and assuming that the counter (8) is cleared at the first edge of the data, the pulse D3 is the edge detection pulse ED.
is equal to Therefore, if this pulse D3 is used as a data extraction pulse and the data TRDA is sampled in the data extraction circuit (11) at its falling edge, the original data can be extracted correctly.

However, the data TRDA has a phase deviation, and the edge detection pulse ED is not necessarily obtained when the count value is "3". For this reason, a correction commensurate with the phase deviation is made by AND gates (5) and (6) by the above-mentioned clearing operation.

In other words, the fact that the edge detection pulse ED is obtained when the count value is "0" means that the width of 1 bit of data has shifted in the direction longer than 4 clocks, so it is necessary to pause the count once. If this is done, the time will be extended by one clock, and it will correspond to the data TRDA.

On the other hand, when the count value is "2", the edge detection pulse ED
Obtaining means that the width of 1 bit of data is biased in the direction of being shorter than 4 clocks, so if you advance the count value by 1 clock, the time will be shortened. Thus, it corresponds to the data TRD^.

Note that if the counter (8) is cleared when the edge detection pulse ED is obtained when the count value is "12", the counter (8) will not become the count value "3" for the pulse D3 as the data extraction pulse. Therefore, it does not occur. Therefore, the output of the AND gate (6) is
1) is supplied to the data extraction circuit (11) as a data extraction pulse.

FIG. 2F shows changes in the count value of the counter 48) controlled as described above, and FIG. 2G shows the data sampling pulse PD obtained from the OR gate α0).

As mentioned above, the data TRDA is extracted by sampling at the falling edge of the pulse PD in the circuit (11), and as shown in FIG. 2G, the extracted data is the original data ORD^. It is in accordance with.

Note that in the above example, a clock that is four times as fast as the data transmission rate is used, so a four-way counter is used as the counter. Since it is a 74-ary counter, control to follow the phase deviation of data can be performed simply by clearing the counter.

However, the present invention is not limited to the use of a clock that is four times the data transmission speed and a quaternary counter as described above.In short, the present invention is not limited to the use of a clock that is four times the data transmission speed and a four-way counter. Depending on the relationship between the value and the data edge, the counter may be stopped or allowed to advance. It will be clear that the count value to be paused or advanced is not limited to "1".

Note that the example in Figure 1 corresponds to a steady deviation of 415 or more and 4/3 or less when converted to transmission speed fluctuations, and 2 for short-term fluctuations.
It is possible to reproduce a clock suitable for the timing of extracting data from a serial signal with a deviation of more than /3 and less than 2/1.

Effects of the Invention In this invention, synchronization information is also obtained from the transmission data itself, which reduces the number of elements in the transmission system compared to the case of the conventional astop synchronization method, in which the data extraction timing is determined only from the start bit. It is possible to obtain data sampling pulses with fewer data errors due to the influence of. This improves the reliability of the transmission system.

In addition, since the configuration for this can be realized by a circuit that detects data edges, a counter, and a means for controlling the count value of this counter, no adjustment is required compared to when a PLL circuit is used for increasing the synchronous clock. It also has the advantage of being easy to digitize and suitable for IC.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of an example of the device of this invention, Fig. 2 is a time chart for explaining the same, Fig. 3 is a block diagram of a specific example of a part of the circuit, and Fig. 4 is the same as Fig. 3. FIG. 3 is a diagram for explaining a circuit. (3) is a clock generation circuit, (4) is an edge detection circuit,
1B) is a counter. Figure 1

Claims (1)

[Claims] N for 1 bit of original data (N is an integer of 3 or more)
It has a clock generation circuit that generates a reference clock signal with a frequency that includes clock pulses, an N-ary counter, and a circuit that detects edges of transmission data obtained by the original data via a transmission system. However, when the number of clock pulses included between the edges is less than an integral multiple of N, the count value of the counter is advanced by an extra amount, and when it is more than an integral multiple of N, the count value is increased. A synchronous clock reproducing device that pauses for a predetermined count value and obtains a pulse for extracting the transmission data when the count value is a specific value.