JP2002368728A - Device and method for synchronizing received data sent in parallel through plurality of channels - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and method that synchronizes a plurality of data channels sent in parallel by using a single clock signal and eliminates skew between the data channels so as to enhance the transmission capability. SOLUTION: Controlling delay in a clock signal derived from received data generates a clock signal (50) whose phase is adjusted and using the clock signal synchronizes each data signal received from a plurality of channels respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface or an apparatus for receiving a data string transmitted in parallel.

[0002]

2. Description of the Related Art In general, there are two ways of successfully recognizing that data has been transmitted. In serial data transmission, data is transmitted sequentially over a single transmission channel. In parallel transmission, a plurality of related channels are provided, and data is simultaneously transmitted via the plurality of channels.

[0003] In a data transmission system, data is generally transmitted in a fixed relation to a clock signal. That is, the clock signal defines a fixed time slot and transmits one data bit in each time slot. Upon receiving the transmitted signal, the relationship of the received signal to the data time slot is established so that the transmitted data can be reproduced. Due to fluctuations introduced by the transmission medium, it is not possible to simply run a clock with the appropriate frequency at the receiver without guaranteeing that it is correctly synchronized with the incoming signal.

In a serial transmission system, a receiving device can generate an appropriately synchronized clock from the received data itself, or a data sequence can be used to synchronize a locally generated clock to enable data recovery. You can also. Using such devices and using serial data technology, high data transmission rates have been achieved.

[0005] Parallel data transmission introduces another problem in terms of data reproduction. In particular, the transmission characteristics of each of the plurality of parallel channels are not always the same. Some variation can be introduced by the physical structure of the transmission line (eg, cable length), but proper design can minimize these. Other factors include interference in the transmission path, and such environmental factors affect some channels differently than others. Due to the influence of such different characteristics in various channels, the transmission time from transmission to reception may not be the same in all channels. Therefore, in the receiving apparatus, there may be some deviation from proper synchronization between channels, which is caused by skew (A
skew ＠).

[0006] Typically, a clock signal may be transmitted using one channel in a parallel system, which clock signal can be used to recover data at the receiver, and the skew is also reduced by the clock signal. Affects the timing relationship between the channel and the data channel.

By providing steps to limit the transmission distance and data rate in each channel, data
It is possible to avoid errors caused by skew in parallel transmission systems between channels and clock channels. This has the effect that the magnitude of the introduced skew is small compared to the data clock interval and does not interfere with data reproduction.

[0008]

However, the increased bandwidth requirements in data transmission systems have come close to those previously used for serial transmission, and the need for the ability to transmit parallel data at the data rate in each channel. There is. At such data rates, problems caused by skew in parallel transmission channels have a significant effect on the ability to recover the received data.

[0009] One solution would be to regenerate a separate data recovery clock for each of the parallel channels. However, this is impractical due to the large number of parallel data channels and does not address the lack of synchronization between the channels.

[0010]

SUMMARY OF THE INVENTION The present invention comprises means for generating a clock signal based on received data, and associated with each of the channels, synchronizing data received from the associated channel with the generated clock. Means.

In this configuration, a single clock signal is generated, which is used for all data channels. this is,
This means that the device can be easily scaled to receive data from multiple parallel channels.

Furthermore, the apparatus eliminates skew between data channels when synchronizing all data channels with a single clock. Thus, the device can simply provide the received and reconditioned data signal for subsequent processing. Alternatively, the apparatus can perform data recovery while simultaneously realigning the channels.

[0013] The clock signal may be generated based on a single receive channel. This channel may be a channel designed for transmitting a clock signal from a transmitter. Alternatively, this channel may be one of the data channels where a significant number of data transitions are expected.

Further, it is possible to generate a clock signal based on a plurality of parallel channels.

Synchronizing each data channel with this clock may preferably be done by applying a variable delay to each data channel. Further, the generated clock signal is preferably delayed by one half of the maximum delay applicable to each data channel so that the data channels can be effectively advanced or delayed relative to the clock. .

These problems are overcome by the present invention, and other features and advantages are more fully described in the following description of a preferred embodiment, which provides non-limiting examples, with reference to the accompanying drawings.

[0017]

FIG. 1 shows a timing diagram of data signals in a typical data transmission system. In particular,
FIG. 1 shows a clock signal 10 known as a half rate clock. This is indicated by a representative data stream 12 and sequential data slots 14. In the preferred embodiment, it is assumed that the half rate clock is transmitted by one of the parallel channels. Usually, when reproducing data, it is to generate a full-rate clock having a frequency twice that of the half-rate clock, so that the half-rate clock is placed at the center of each data slot 14. , And at both boundaries.

FIG. 2 is a waveform diagram similar to FIG. 1 except that it shows the effect of skew on the transmission channel. Compared to half-rate clock 10, the boundaries between data slots in data stream 22 may drift out of synchronization with clock transitions as a result of varying transition times in the carry channel.

More precisely, skew is specified by a single time value representing the maximum alignment error between any two signals in a parallel transmission signal. This is defined as Ts, so any data bit can be advanced or delayed up to Ts worst relative to the clock.
The receiver needs to be designed to handle such misalignments.

FIG. 3 shows an overview of a preferred parallel interface receiver system. It comprises a clock recovery circuit 30, a set of data de-skew circuits 40 (one circuit for each bit in the parallel bus). The basic principle of this system is to generate a recovered clock from a clock input and distribute it to each data de-skew circuit 40. In the data de-skew circuit 40, each incoming data signal is The clock is shifted so as to be aligned with the clock using the variable delay line.

Hereinafter, the operation of the data de-skew circuit 40 will be described in more detail. Each of the circuits includes a variable delay configured to apply a variable delay between O and Td to received data. Note that a line 42 is provided. The variable delay line 42 is controlled by a delay line control means 44. The delay line control means 44
It operates based on a comparison with a clock signal generated by the phase detector 46.

Further, the delay line 32 is connected to the clock recovery circuit 3.
Even 0 is used and is set to be exactly at the center of the range. That is, the delay line in the clock recovery circuit 30
Set to 2Td. This allows the data de-skew circuit 40 to shift data by "2Td" with respect to the clock.

The illustrated clock recovery system is based on a phase interpolation technique, and generates a phase of an output clock from a pair of orthogonal reference clocks 35 by adding different weights in a phase interpolator 34 and adding them. In FIG. 3, the reference clock (and thus the aligned data clock) is typically at the full data rate. However, it is also possible to adapt the system to operate with a half rate clock.
The control of the phase interpolator 34 is performed using the phase detector 38 and is an alignment of the recovered clock 50 and a comparison with the delayed half-rate clock.
Thus, it generates a control signal which is used to adjust the weight of the phase interpolator. Phase interpolator control 36 may use the analog method described in Patent Application No. 0004298.6, but is typically implemented using digital techniques.

The reproduction clock 50 is distributed to each data channel. Note that in practice this clock distribution is guaranteed to have no skew itself. Thus, the data de-skew circuit 40 uses a phase detector 46 (which may be the same as the phase detector of the clock recovery circuit 30) so as to shift the data to alignment with the recovered clock 50.
The variable delay line 42 is controlled.

Therefore, in order to guarantee that the skew can be canceled at each input, the variable delay line 42 must shift the data position by 2Td with respect to the clock and guarantee 2Td> Ts. No.

The precise implementation of the phase detectors 38, 46 is not part of the present invention. However, this
Generally, when data is advanced or delayed, respectively, the delay is increased (via control signal AUp #) or reduced (control signal ADDown #).
It simply represents a thing. FIG. 4A shows an example of a possible phase detector 46. This circuit simply latches the received data on the positive and negative edges of the clock.
2. Sampling input to 403. The exclusive OR gate function 404 detects a change in the data value. That is, when a change occurs between a positive clock edge and a subsequent negative edge, a pulse AUp # is generated from latch 405 as advancing, while a change occurs between the negative clock edge and the subsequent When the signal is generated between the positive edge and the positive edge, it is regarded as a delay and the pulse ADown is output from the latch 405.
n}. In this way, the data edge is aligned with the negative clock edge, thus placing the positive clock edge of the full rate clock at the center of the data eye to optimize the data bit value. Sample. FIG. 4B shows this timing.

The operation of this phase detector can be explained by the characteristics shown in FIG. It should be noted that this property exhibits a periodicity limited by ∀2Td.
Here, the UI is a unit interval (Amit interval ＠) equal to the period of a single data bit.
This is a required characteristic of the data phase detector.

In the data de-skew circuit 40, the phase detector 46 is used to control the data input delay line to adjust the phase with respect to the aligned reproduced clock 50. FIG. 6 shows the adjustment range (∀2Td) of the data signal for an ideal aligned input superimposed on the phase detector characteristics. FIG. 7 shows a similar view for misaligned data. That is, in this case, the data is late and the phase detector will indicate that the delay needs to be reduced. This figure shows the state described above, 2Td> Ts, to relocate the data around the center.

FIG. 8 is similar to FIG. 7, except for a high skew value and a correspondingly increased data delay adjustment range. In such a state, the data phase can be adjusted so that the data phase overlaps the adjacent bit period. If the system enters this state, the phase detector 46 indicates the wrong direction to center the data (eg, in FIG. 8, the phase detector attempts to increase the delay rather than decrease the delay). ), The potential locks up at the end stop in the range of the delay line. The condition under which this occurs is T
It is clear that s + 2Td> 2UI.

Accordingly, the range for Td satisfying these requirements is as follows.

[0031]

## EQU1 ## Ts <2Td <(2UI-Ts)

These constraints are that Td is subject to variation due to manufacturing tolerances, while any reduction in Ts
Both its minimum and maximum values result in a reduced tolerance range for Td. For example, when Ts = 3UI,
Td is a margin 0 for an error.

To alleviate these constraints, it is desirable to avoid potential lock-up conditions. In practice, this can be achieved by making the delay line control for Around around 包含 from its maximum to its minimum and vice versa. When this is done, there is no potential lock-up as long as the queue and data delay are sufficient to lock to the center of the adjacent data bit as shown in FIG. This occurs when Ts + 2Td> 2UI. Therefore,
Here, the restrictions on Td are as follows.

[0034]

## EQU2 ## Ts <2Td <(UI-Ts)

This gives a much larger margin than in the previous case.

It should be noted that the requirement to include data delay lines probably requires a digital solution to control them.

Although there are various standard methods for implementing the variable delay line, one preferred embodiment is shown in FIG.
02 is used. The phase interpolator 104 mixes the specific delay signal D0 with the maximum delay signal D1 according to a variable ratio and outputs a variable delay signal. This is achieved by applying and mixing the differential type D0 and D1 to one set of transistor pairs 106 and 107 with a variable ratio according to the values of the current sources I0 and I1, as shown. It can be implemented. In this configuration, the bias currents I0 and I1 are changed in the reverse direction so that the total current becomes constant.

The design of FIG. 10 provides good performance as long as Td is relatively small compared to the data bit period. When Td is a high value, the circuit of FIG. 11 having more delay stages 112 may be used than a single low-speed stage (which tends to attenuate high-speed data signal components). These may then be used in connection with a multi-stage interpolator similar to that shown in FIG. If necessary, the delay line may be further extended by multiple stages. This both tends to improve the linearity of the data phase interpolator and allow for large delay variations.

With respect to the above description, the following items are further disclosed.

(1) Means (30) for generating a clock signal (50) based on received data in an apparatus for receiving data transmitted in parallel via a plurality of channels.
And means (40) associated with each of the plurality of channels for synchronizing data received from the channel associated with the generated clock signal (50).

(2) The clock signal generating means (30) includes a clock signal delay means (32) for delaying the clock signal (50) by a predetermined amount with respect to a clock input derived from the received data. The device of claim 1 comprising:

3. The apparatus of claim 2, wherein said predetermined amount is one half of the maximum delay (Td) available for each data channel.

(4) The apparatus according to the above item (1), (2) or (3), wherein the synchronization means (40) includes variable delay means (42) for applying a variable delay to each channel.

(5) Each variable delay means (42) is increased in the applicable delay range (0-Td) and, if said maximum delay (Td) is not sufficient to establish synchronization, its maximum 5. The apparatus according to claim 4, wherein the apparatus is controlled to return to the delay or to its maximum delay (Td) if the maximum delay is insufficient to establish the synchronization.

(6) The variable delay means (42) includes a means (104) for mixing a non-delayed signal with a signal delayed maximally by a variable ratio to output a variable delay signal (104). Item.

(7) The mixing means includes a plurality of delay stages (1
7. The device according to claim 6, comprising item 12).

(8) In a method for synchronizing a plurality of data signals received through a plurality of channels, a step of generating a clock signal (50) based on the received data; Synchronizing with the generated clock signal (50).

9. The method of claim 8, wherein said clock signal is delayed by a predetermined amount with respect to a clock signal derived from said received data.

(10) The method according to (9), wherein the predetermined amount is a 1/2 maximum delay (Td) applicable to each data channel.

(11) The variable delay in each of the channels is increased in the applicable delay range (0-Td) and, if the maximum delay is insufficient to establish synchronization, its minimum delay and 11. The method according to claim 8, 9 or 10, wherein the method is controlled to return to the reverse.

(12) Parallel transmission data in a plurality of channels are synchronized by generating a clock based on received data and synchronizing data received from each channel with the generated clock signal (50).

[Brief description of the drawings]

FIG. 1 is a waveform diagram showing a phase clock and a data signal.

FIG. 2 is a waveform diagram showing a clock signal and a data signal having a skew;

FIG. 3 is a block diagram showing an outline of a high-speed parallel interface.

FIG. 4A is a circuit diagram of a phase detector. B is an idealized signal waveform diagram of the phase detector.

FIG. 5 is a waveform chart showing characteristics of the phase detector.

FIG. 6 is a waveform diagram showing a phase detector characteristic together with a data delay adjustment range for ideal alignment data.

FIG. 7 is a waveform chart showing a phase detector characteristic together with a data delay adjustment range for misaligned data.

FIG. 8 is a waveform diagram having characteristics of a phase detector with high skew and delay Td.

FIG. 9 is a waveform diagram of characteristics of a phase detector having a high skew and a large Td having a delay Around around ＠.

FIG. 10 is a circuit diagram of an interpolator, a block diagram of a variable data delay line based on the interpolator, and a diagram showing its characteristics.

FIG. 11 is a circuit diagram of a data phase interpolator having improved linearity and range, a diagram showing an extended data phase interpolator delay line based on the data phase interpolator, and characteristics thereof.

[Explanation of symbols]

 Reference Signs List 30 clock recovery circuit 32, 42 variable delay line 34 phase interpolator 36, 44 phase interpolator control 38, 46 phase detector 40 data de-skew circuit 42 variable delay line

Claims (2)

[Claims] 1. An apparatus for receiving data transmitted in parallel via a plurality of channels, means (30) for generating a clock signal (50) based on the received data, and means associated with each of the plurality of channels. Means (40) for synchronizing data received from a channel associated with said generated clock signal (50). 2. A method for synchronizing a plurality of data signals received over a plurality of channels, comprising: generating a clock signal (50) based on the received data; and generating the data received from each channel. Synchronizing with the generated clock signal (50).