JPS6133060A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a data transmission circuit which transmits data repetitively by delivering the desired transmission data out of a memory in accordance with a counting action and transmitting them repetitively. CONSTITUTION:A switch 5 is closed to start counting the clock pulses sent from an oscillator 1. This count output is supplied to a memory in the form of an address signal, and the different addresses are designated every counting action. Thus a transmission state signal SS emerges at an output terminal U1 of the memory 3. Then a light emitting diodes 6 is turned on, and the serial transmission data added with a parity bit is delivered from an output terminal U2. When a counter 2 counts up a fixed number of clock pulses and a series of transmission data are delivered, a count control signal SC emerges at an output terminal U3. Then the counter 2 is reset and the transmission data are transmitted repetitively through a data transmission line 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transmitting circuit that is used, for example, in an identification data transmitting device and repeatedly transmits fixed or semi-fixed data.

<Prior art and its problems> Generally, when transmitting serial data, errors during data transmission are detected using a parity addition method, reverse transport method, etc., but it is difficult to implement such a method using hardware. In this case, a circuit such as a parity addition circuit is required, making the overall circuit configuration complicated, and if it is attempted to be implemented using software, a new CPU is required for this purpose, which has the disadvantage of increasing costs in both cases.

This drawback also applies to circuits that repeatedly transmit fixed or semi-fixed data such as identification data. Or a transmission circuit for semi-fixed data could not be obtained.

<Object of the Invention> The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a transmitting circuit that can repeatedly transmit fixed or semi-fixed data with a simple circuit configuration. shall be.

<Configuration and Effects of the Invention> In order to achieve the above object, the present invention provides a data transmission circuit that repeatedly transmits fixed or semi-fixed data, which includes an oscillator that outputs clock pulses and a counter that counts the clock pulses. , R for storing at least the data to be repeatedly transmitted and the counter control signal.
The ROM is configured to be addressed by the count output of the counter and output transmission data and a counter control signal from different output terminals, respectively.

Since the present invention has the above-mentioned characteristics in terms of structure,
The required transmission data is output from the ROM in accordance with the counting operation of the counter, and fixed or semi-fixed data can be repeatedly transmitted. Moreover, the data transmission is controlled by a new dedicated circuit for error detection. or CPU
Even without providing a circuit, accurate operation can be performed with a simple circuit configuration.

That is, when implementing a parity check method to detect errors in data transmission, the data to be sent with a parity bit added must be stored in ROM in advance, and when implementing an inversion transmission method, If data that has been added or modified as appropriate for error detection is stored in R and OM in advance, such as by storing inverted data and inverted data in ROM in advance, this data can be sent as is. Therefore, on the receiving side, it is possible to reliably detect errors during transmission from the data that has been added or modified, and therefore, data transmission can be performed accurately, and errors during transmission can be detected from the data that has been added or modified. No detection circuit or CPU is required.

Moreover, by simply changing the storage contents of the ROM, it is possible to deal with changes in the contents of transmission data, differences in transmission methods, and changes in repeated transmission time, so it can be used for various purposes and has a wide range of applications.

<Description of Examples> Hereinafter, the present invention will be described in detail based on examples shown in the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which serial data in a 4-pitch F configuration is repeatedly transmitted. In the figure, numeral 1 is an oscillator that outputs clock pulses, 2 is a counter that counts the clock pulses of the oscillator 1, and 3 is RO'M that stores at least data to be repeatedly transmitted and a counter control signal. In the embodiment, a parity bit is added to the transmission data, and a signal indicating the transmission state is separately stored. 4 is a counter control section, and 5 is a switch.

Therefore, the count output of the counter 2 becomes the address signal of the ROM 3, and the count output of the counter 2 becomes the address signal of the ROM 3.
In this embodiment, four output terminals CO, C1, C2, C
3 are the same number of address input terminals A O of ROM3, respectively.
, A 1 , A 2 , and A 3 . R.O.
The first output terminal U1 of M3 is a terminal for outputting a signal indicating the transmission state, and a light emitting diode 6 is connected to this, and a constant positive voltage Vd is applied to the light emitting diode 6.

The second output terminal U2 of the ROM 3 is a terminal for outputting transmission data to which a parity bit has been added, and is connected to the data transmission line 7. The third output terminal U3 of the ROM 3 is a terminal that outputs a counter control signal, and the output is sent to the counter control section 4.
The signal is inputted to one input terminal of a negative logic NAND gate 8 constituting the circuit. The switch 5 and a resistor 9 are commonly connected to the other input terminal of the NAND gate 8, and a constant positive voltage g is applied through the resistor 9.

Next, the operation of the above configuration will be explained based on the time chart in FIG. 2 and the address-output correspondence diagram of the ROM 3 in FIG. 3. Now, when switch 5 is closed, the switch output becomes H.
(high) level, which causes counter 2 to start counting clock pulses from oscillator 1;
A count output appears at each output terminal Co-C5 of the counter 2, respectively. This count output is supplied as an address signal to the address input terminals AO to A3 of the ROM 3, and a different address is designated for each counting operation.

As a result, an L (low) level transmission state signal Ss appears at the first output terminal U1 of the ROM 3, and the light emitting diode 6 lights up. At the same time, from the second output terminal U2 of the ROM3, serial transmission data with a parity bit added, that is, a start bit ST, data bits D1 to D4,
Transmission data consisting of parity bit P, stop bit SP) is output. Counter 2 counts a fixed number of clock pulses (9 clock pulses in this example);
When one set of transmission data has been output, an L-level counter control signal Sc appears at the third output terminal U3, and the counter 2 is reset by this counter control signal Sc. Therefore, the counter 2 returns to its initial state and starts counting clock pulses anew, and the above-described operation is repeated according to the count output, and the transmission data is repeatedly transmitted from the data transmission line 7.

When employing a parity check method to detect errors in data transmission, transmit data with parity bits added as described above is stored in ROM3 in advance; however, when employing other error detection methods, Transmission data that has been added and modified according to the method is stored in the ROM 3 in advance.

In the above embodiment, a single data transmission line is used to transmit serial data, but a plurality of data transmission lines may be used to transmit parallel data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment, and FIG. 3 is a correspondence diagram showing the relationship between addresses and outputs in a ROM. 1... Oscillator, 2... Counter, 3... ROM,
4... Counter control section, 7... Data signal line.

Claims (1)

[Claims] (1) In a data transmission circuit that repeatedly transmits fixed or semi-fixed data, an oscillator that outputs clock pulses, a counter that counts the clock pulses,
A ROM that stores at least data to be repeatedly transmitted and a counter control signal, and the ROM is addressed by the count output of the counter and outputs the transmission data and the counter control signal from different output terminals, respectively. data transmission circuit.