SU1472903A1 - Digital network address modifier - Google Patents

Abstract

Use: in electrical engineering. The essence of the invention: the device contains a pulse distributor, two elements AND, an address register and three groups of elements AND, the first output of the pulse distributor is connected to the first input of the first element AND whose output is connected to the first inputs of the AND element of the first group, the second output of the pulse distributor is connected to the first inputs of elements AND the second group.

Description

the outputs of the m-th bit of the address register are connected respectively to the second inputs 2 (ml) -ro and 2-th elements AND of the third group (m + n + 1, where t is the full address of the logical address register address), the outputs of the elements AND the second Groups are connected to the corresponding bits of the physical output.

the addresses of the node of the relay of the device's network messages, the outputs of elements AND of the third group are connected to the corresponding bits of the output of the physical address of the subscriber of the network of the device, the input of the logical address of the device is connected to the information input of the address register.

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The invention relates to computing and can be used in the interface of subscribers in a digital communication network to convert a logical subscriber into the physical addresses of network nodes and communication lines by the subscriber.

The aim of the invention is to simplify the device.

Figure 1 shows the functional scheme of the device; figure 2 -. example of a digital communication network.

The device contains the address register 1, the pulse distributor 2, the OF element, the trigger 4, the AND 5 element, the trigger b, the AND 7 element, the delay element 8, the groups 9,10,11 elements AND the OR element 12, the inputs 13 and 14 of the logical address of the device and starting the device, the outputs 15 of the physical address of the node receiving messages of the network 16 sign of issuing the physical address of the node receiving the network messages, 17 sign of issuing the physical address of the network subscriber, 18 of the physical address of the node of the network message repeater, 19 of the physical network subscriber, 20 signs of completion modifications addr ca device.

The device works as follows.

When a subscriber interacts with a digital network, a multi-line interface is used. This means that in order to increase the reliability of communication, the subscriber has the ability to connect to the network (network nodes) using several subscriber lines - access lines. In this case, if any access line or network node to which the subscriber is connected fails, the latter can use another access line that is connected to another node of the digital network (see, Fig. 2). For identification of subscribers, logical addressing is used. representing a permanently assigned logical address of the subscriber pointing to one or more physical addresses. Receiving a logically addressed message from subscriber H (Figure 2), node 000 of the network converts logical address D specified in the address field of the message header into physical addresses 011 and 111 of output nodes of the network and physical addresses 0111 and 1110 of subscriber access lines D с the purpose of determining the route of transmission of a message to a specific physical address. The address here is the address of the network node (port) to which the subscriber is connected using a physically addressable access line. This means that one logical address can correspond to several physical addresses, which corresponds to a multi-line subscriber-network interface.

The system of logical addressing of subscribers of a digital communication network is such that the output node of the network with a physical address a ,, a,,., And a has a subscriber with a logical address b1b7 ".. bt, if bit,., Ah, the physical address of the node networks are identically equal to the corresponding bits b1b ,,. bh.1 logical address of the subscriber.

For example, if for n = 3 the output node has the address 011, then for n 4 this node may have four subscribers with addresses 1100; 1101; 1110; 1111. In turn, these same subscribers can be connected to another output node of the network with the address 111. Otherwise, n is the last bit of the address of the output

network node identically equal to the first address of the subscriber.

6, the recipient of the message can be either a network node or a network subscriber. In order to distinguish between messages that are intended for network nodes and network subscribers, the sender identifies the message being transmitted. For messages intended for network nodes, the identifier takes the value 1, for subscriber messages O. Therefore, the logical address of the message has a prefix,

device (signaling the completion of the logical address analysis). In addition, at the second input of the splitter 2, a shutdown is performed and the device shuts down.

Thus, if a network node acts as a recipient, then the operation of the device is completed within one cycle of operation.

In the event that in the zero p p de reg register of the address 1 is written O (low potential at a unit of discharge), the first clock imp

containing a specific value indentation 15 Does not pass to the output of a logical

typifier. In that case, if the logical address of the message whose destination is a network node is analyzed, the analysis immediately stops after the identifier is identified, since it is not necessary to reveal the physical addresses — points of connection to the multiline subscriber network. Instead, the physical

20

element 3 and device operation n must continue in the next cycle.

The second clock pulse from the second output of the distributor 2 prepares element 5 for operation, setting trigger 4 to one. There is a reading of the contents from the 1st to the (n-1) -th digit of the register of the 1 address with simultaneous polling

the address of the network node, which is on-25 trigger 6, while the output

the radiator. Control is then transferred to the routing procedure. Otherwise, the logical address analysis continues until all the physical addresses defining the subscriber’s multi-line interface are fully detected, after which control is transferred to the procedure for processing the physical address table.

Before the start of the analysis procedure, the logical address of the recipient is recorded at the device input 13, Triggers 4 and 6 are set to the zero state. The pulse distributor 2 is triggered from the control signal on the device input 14.

The first clock pulse from the first output of the distributor 2 polls the zero bit of the register 1 address. If zero is written in the zero bit 1 (high potential at the unit output of the bit), then the first

a clock pulse appears at the output of the logic element AND 3. As a result, through the group 9 of the logic elements I, the contents of the 1st to nth bits of the 1 register of the address are read, and the output of the device 15 is formed by n-bits the physical address of the recipient - digital communication network node. At the same time, at the output 16 of the device, a control signal is generated that is external to the considered signal.

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device (signaling the completion of the analysis of the logical address). In addition, a shutdown is performed at the second input of the distributor 2 and the device shuts down.

Thus, if a network node acts as a recipient, the operation of the device is completed within one cycle of operation.

In the event that in the zero bit of the de reg register of the address 0 is written (low potential at the single output of the bit), the first clock pulse

element 3 and the device continues in the next cycle.

The second clock pulse from the second output of the distributor 2 prepares element 5 for operation, setting trigger 4 to one state. There is a reading of the contents from the 1st to the (n-1) -th digit of the register of the 1 address with simultaneous interrogation of the state of the trigger 6, while the output

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five

18 devices through a group of 10 logical elements And the formation of an n-paired single physical address of the first output node of the digital network, to which the subscriber is connected via the corresponding access line. (t + 1) -block address of the corresponding access line is formed at the output 19 of the device through a group of 11 AND gates by reading the contents of the 1st to pz-th bits of the register 1 address in a given clock cycle and polling the trigger status 6. Besides Moreover, in the considered clock, at the output 17 of the device, a control signal is formed that is external in relation to the device in question (signaling the completion of the next stage of the analyzer operation),

The third clock pulse from the first output of the distributor 2 through the And 5 element, prepared for operation in the Pre-1 preceding cycle, sets the trigger 6 into one state, as a result of which the And 7 element is prepared for operation.

The fourth clock pulse from the second output of the distributor 2 performs functions similar to those of the second clock pulse, except that the single state of the trigger 4 does not change. In this case, the n-bit physical address of the second

output node of the digital network to which the subscriber is connected via the corresponding access line; (tp + 1) - the bit address from the corresponding access line is formed at the output 19 of the device. In addition, in this cycle, the external control signal is formed at the output 17 of the device (signaling the completion of the next stage of the analyzer operation).

Fifth clock pulse from the first output of the distributor 2 through the element And 5 affects the trigger 6, without changing its single state, and

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1472903

after passing through the logic element AND 7 and the delay in the element 8 of the back, hold, sets the triggers 4 and 6 to the zero state and stops the distributor 2. Simultaneously, the output of the device 20 is generated by an external control signal (signaling the end of the analysis procedure

logical address of the recipient, received at the input device 13).

Delay element 8 is necessary to prevent simultaneous effects of a clock pulse on different

5 trigger inputs 6 (to eliminate the automaton effect).

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Claims (1)

A device for modifying an address in a digital network containing a pulse distributor, two AND elements, an address register and three groups of AND elements, the first output of the pulse distributor connected to the first input of the first AND element, the output of which is connected to the first inputs of the AND elements of the first group, the second output pulse distributor is connected to the first inputs of the elements And the second group, which is distinguished by the fact that, for the sake of simplicity, it contains two triggers, a delay element, an AND element, and an OR element, and the trigger input of the device is connected to the trigger input of the pulse distributor, the first output of which is connected to the first the inputs of the second and third elements And, the second output of the pulse distributor is connected to the installation input in the unit of the first trigger, the output of the sign of the issuance of the physical address of the subscriber network of the device and to the first inputs of the elements And the third group, the output of the first trigger is connected to the second th input of the second AND gate, whose output is connected to the set input in units ^f zu second flip-flop, a direct output of which is connected to the second input of the third AND gate, whose output via a delay element connected to the output modification terminator device address, setting to zero inputs of the first and the second flip-flops and to the first input of the OR element, the second input and output of which are connected respectively to the output of the first element AND and to the blocking input of the distributor. pulses, the output of the sign of the modification mode of the address of the address register is connected to the second input of the first element And, the direct and inverse outputs of the K-th category of the address register are connected respectively to the second inputs of the 2 (kl) -ro and 2 of the k-th elements of the first, second and third groups (k = 1, η-1, where η is the width of the physical address field of the network node of the address register network) the outputs of the 2 (k-1) th and 2 th elements And the first hochppm are connected respectively to 2 (k-1) th and to the 2nd category of the output of the physical address of the receiver node of the device network messages, the output of the first element And sub Access to the exit of the sign. issuing the physical address' of the receiver node of the device network messages, the prism and inverse outputs of the ηth bit of the address register are connected respectively to the second inputs 2 (nl) -ro and 2 of the ηth. elements And of the first group, the outputs of which are connected respectively to the 2 (n-1) th and 2 ηth digits of the output of the physical address of the receiver node of the device network messages, the second, inputs of the 2 (η-1) th and 2 ηth elements And the second and third groups are connected respectively to the direct and inverse outputs of the second trigger, direct and inverse SU 1472903 A1 '' tn-ro outputs of the address register category are connected, respectively, to the second inputs of 2 (m-l) -ro and 2-th elements of the third group (w^β η + 1, where m is the bit depth of the logical address field of the address register)., the outputs of the AND elements of the second group are connected to the corresponding bits of the output of the physical address of the device relay node of the device network messages, the outputs of the AND elements of the third group are connected to the corresponding ·. the corresponding bits of the output of the physical address of the subscriber of the device network, the input of the logical address of the device connected to the information input of the address register.