JPS61292418A - Phase locked oscillation circuit - Google Patents

Abstract

PURPOSE:To decrease the synchronous pull-in time than that of a conventional circuit by providing an oscillator having the same frequency as a reference input signal and outputting individually a comparison reference phase to each phase locked oscillation circuit. CONSTITUTION:The oscillator 11 is an oscillator having an oscillation frequency equal to a reference input signal. A selector 16 outputs normally the reference input signal f0 and outputs the output of the oscillator 11 when a high level selection signal is impressed to an input terminal 17 because of a fault of the reference input signal f0 or at the independent synchronous mode. A frequency divider 4 frequency-divides the output of the selector 16 and outputs the comparison reference phase to phase synchronizing circuits A, B. Thus, the high level selection signal is inputted to the input terminal 17 at a fault of the reference input signal f0 or at the independent synchronous mode so as to output the output of the oscillator 11 thereby synchronizing synchronous output signals f1, f2 at the input fault or the independent synchronous mode and the comparison reference phase is outputted individually from the frequency divider 4 to the circuits A, B.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked oscillator circuit in a digital slave synchronization network, and in particular to a phase-locked oscillator circuit that receives a reference input signal and synchronized with the reference input signal and has a plurality of different frequencies. This invention relates to a phase-locked oscillator circuit that obtains an output signal.

[Conventional technology]

Conventionally, this type of phase-locked oscillation circuit uses a frequency divider l that divides a reference input signal of one frequency fo, as shown in FIG.
, a phase synchronization circuit that includes a phase comparator 13, a voltage controlled oscillator 8, and a frequency divider 3 and outputs a synchronous output signal of frequency f2, a phase comparator 12, a voltage controlled oscillator 7, and a frequency divider 2. The frequency divider 2 obtains a synchronized output signal of frequency f1 by sub-synchronizing with reference input signal f0, and converts the reference phase for the phase synchronization circuit of the synchronized output signal of frequency f2 to frequency divider 2.
It consists of a phase synchronization circuit that outputs an output.

As a result, the synchronization output signal f2 is slave-synchronized to the synchronization output signal f1, and the synchronization output 'l +f2 as a whole is slave-synchronized to the reference input signal f0. This occurs when the reference input signal fo becomes an obstacle or when the reference input signal f. This is to synchronize the synchronous output signals r, +'2 when performing independent synchronous operation without the synchronous output signal r, +'2.

[Problem that the invention seeks to solve]

The conventional phase synchronized oscillation circuit described above has a synchronized output signal f2
Since the output phase synchronized oscillator circuit uses the synchronized output signal f1 as the reference phase of the phase comparator 13, it has the disadvantage that the synchronization pull-in time is long at the start of operation or when recovering from a failure in the reference input signal fo. Was.

[Means for solving problems]

The phase synchronized oscillation circuit of the present invention includes a phase comparator, a voltage controlled oscillator, and a frequency divider, and includes a plurality of phase synchronized circuits that output the synchronized output signals, an oscillator having an oscillation frequency equal to the reference input signal, and an oscillator having an oscillation frequency equal to the reference input signal. A selector that normally outputs the reference input signal and outputs the oscillator when the reference input signal fails or in independent synchronization mode, and a selector that inputs the output of the selector and compares each of the phase synchronization circuits. and a frequency divider that outputs a reference phase.

Therefore, multiple synchronization output signals are synchronized when the reference input signal fails or in independent synchronization mode, and the comparison reference phase of each phase synchronization circuit is individually supplied from the frequency divider. shorter than the circuit.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the phase-locked oscillation circuit of the present invention.

This embodiment is a circuit that obtains two-frequency synchronous output signals of frequencies F, , and f2 dependent on a reference input signal of frequency fo.0 phase synchronization circuit A includes a phase comparator 14, a voltage controlled oscillator 9, and a frequency divider. 5, and a synchronous output signal f! output 0
Phase synchronization circuit B includes phase comparator 15 and voltage controlled oscillator 1
Consists of 0 and frequency divider 6.

The 9 oscillator 11 that outputs the synchronized output signal f2 is an oscillator with an oscillation frequency equal to that of the reference input signal fO. Input terminal 17
The 0 frequency divider 4, which outputs the output of the oscillator 11 by applying a high-level selection signal to the selector 18, divides the output of the selector 18 and outputs a comparison reference phase to each phase synchronization circuit A, H. .

Therefore, when the reference input signal fo fails or when operating in the independent synchronization mode, a high level selection signal is applied to the input terminal 1.
7, the output of the oscillator 11 is output, and the synchronous output signal f, , in the case of an input failure or independent synchronous mode is output.
fz can be synchronized, and since the comparison reference phase is individually output from the frequency divider 4 to each phase synchronization north circuit 28A, B, the synchronization pull-in time is shorter than in the conventional circuit.

〔Effect of the invention〕

As explained above, the present invention is equipped with an oscillator having the same frequency as the reference input signal, and outputs the comparison reference phase to each phase synchronized oscillation circuit individually. This has the effect of synchronizing the output and avoiding an increase in synchronization pull-in time due to the cascade connection of phase synchronization circuits, which is a drawback of conventional circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a phase-locked oscillation circuit according to the present invention, and FIG. 2 is a block diagram of a conventional example. 4.5.6... Frequency divider 9.10... Voltage controlled oscillator 11... Oscillator 14.15... Phase comparator 16... Selector 17... Input terminal.

Claims (1)

[Claims] A phase-locked oscillator circuit that takes a reference input signal as an input and obtains synchronous output signals having a plurality of different frequencies synchronized with the reference input signal, the circuit comprising: a phase comparator, a voltage-controlled oscillator, and a frequency divider. a plurality of phase synchronization circuits that output the synchronized output signals; an oscillator having an oscillation frequency equal to the reference input signal; A phase synchronized oscillation circuit comprising: a selector that outputs the output of the oscillator in a synchronization mode; and a frequency divider that inputs the output of the selector and outputs a comparison reference phase of each of the phase synchronization circuits.