JPH03101311A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE:To stabilize an output frequency by resetting a frequency divider and compulsorily adjusting the phase of the input of a phase comparator at the time of resetting. CONSTITUTION:When there is abnormality in the fluctuation of a cycle in a reference clock 1, the frequency divider 5 is reset by a reset signal from an abnormality detection circuit 6 and a selector 7 is switched by a selector control signal 9. Two inputs inputted to the phase comparator 2 come to signal waveforms without phase deviation, namely, the reference clock, and a circuit subsequent to the phase comparator 2 stably operates in the same way as a case before abnormality occurs. Thus, a VCO output signal 10 becomes stable even if the reference clock is abnormal, and the operation of the other circuit using the output signal can be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase synchronized oscillation circuit used to generate a signal phase synchronized with a video signal in a VTR or the like.

BACKGROUND OF THE INVENTION Recent advances in IC technology have made it possible for anyone to easily design a high-speed phase-locked oscillation circuit, and the range of applications has expanded. The operation of a conventional general phase-locked oscillation circuit will be explained below.

In Fig. 3, the output of the phase comparator 2 is transmitted to the low-pass filter 3.
The output of the low-pass filter 3 is input to the voltage controlled oscillator 4 (hereinafter referred to as vCO), the vCO output signal 6 is input to the frequency divider 5, and the output of the frequency divider 5 is input to the phase comparator 2. and the reference clock is input.

In the above configuration, when the output of the frequency divider 5 is delayed in phase from the reference clock 1, the voltage obtained by smoothing the output of the phase comparator 2 with the low-pass filter 3 changes in the direction of increasing the frequency of the vCO output signal 6. As a result, the phase of the output signal of the frequency divider 5 is advanced as shown in FIG. Conversely, if the phase of the output of frequency divider 5 is ahead of reference clock 1, then vC
The frequency of the O output signal 6 is lowered, and the phase of the output of the frequency divider 5 is delayed.

Therefore, when the phase of the reference clock is stable, the two input signals of the phase comparator 2 are synchronized in phase and have the same frequency. Here, if the frequency division ratio of the frequency divider 5 is N, then
A signal with a frequency N times that of the reference clock whose phase is synchronized with the reference clock can be extracted from the VCO 4.

Problems to be Solved by the Invention However, in such a phase-locked oscillator circuit, when the period of the reference clock 1 deviates due to a certain factor, V
The output signal frequency of CO4 fluctuates, and the amount of the fluctuation is N times the amount of frequency fluctuation of the reference clock 1, assuming that the frequency division ratio of the frequency divider 5 is N.

In other words, the larger the frequency division ratio of the frequency divider, the more difficult it generally becomes to obtain an output from the VCO 4 whose frequency is stable and whose phase is synchronized with the reference clock 1.

Furthermore, if the deviation in synchronization of the reference clock 1 exceeds the expected control range of the VCO 4 due to some reason, the subsequent operation of the phase-locked oscillator circuit may be difficult to predict. When phase-synchronizing the output signal of the VCO 4, it is difficult to stably follow the phase fluctuation of the reference clock when switching the playback screen.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a phase-locked oscillation circuit with a stable output frequency.

Means for Solving the Problems In order to achieve the above object, the present invention makes it possible to reset the frequency divider, arranges a selector between the phase comparator and the frequency divider,
The output of the frequency divider and the reference clock are input to the input of the selector, the output of the selector is input to the phase comparator, and an abnormality detection circuit that generates the reset signal of the frequency divider and the control signal of the selector is arranged in the front stage. This is what happens.

According to the above-described configuration, the present invention detects an abnormality in the reference clock using the abnormality detection circuit, resets the frequency divider, switches the selector to set both inputs of the phase comparator to the reference clock, and detects the result of the phase comparison. This is something that can be done to prevent large fluctuations.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.

In FIG. 1, a reference clock 1 is input to a phase comparator 2, an abnormality detection circuit 6, and a selector 7, and the output of the phase comparator 2 is input to a low-pass filter 3.
The output of the VCO 4 is input to the frequency divider 5, and the output of the frequency divider 5 is input to the selector 7. A reset signal 8 of the output signal of the abnormality detection circuit 6 is input to the frequency divider 5, and a selector control signal 9 is input to the selector 7.

To explain the operation in the above configuration, when there is an abnormality in the fluctuation of the period of the reference clock 1, the frequency divider 5 is reset by the reset signal 8 from the abnormality detection circuit 6, (d) in FIG. 2, and the selector control The selector 7 is switched by the signal 9, and the two inputs to the phase comparator 2 become the signal waveforms of (a) and (C1) in FIG. 2 with no phase shift, that is, the reference clock. The circuits after 2 operate stably in the same way as before the abnormality occurred.

In this way, in this embodiment, even when the reference clock is abnormal, ■C
Since the O output signal 10 is stable, the operation of other circuits that use the output signal can also be stabilized.

Effects of the Invention As described above, according to the present invention, by making the frequency divider resettable and forcibly matching the phase of the phase comparator input at the time of reset, even large phase deviations can be absorbed. It becomes possible. At this time, the phase synchronized oscillation circuit operates as if no phase shift had occurred. Therefore, the voltage range for controlling vCO can be reduced, and a more stable and highly accurate phase-locked oscillation circuit can be provided.

[Brief explanation of drawings]

FIG. 1 shows a phase synchronized oscillation circuit 1 according to an embodiment of the present invention.
... Reference clock, 2 ... Phase comparator, 3.
...Low pass filter 4 ...VCO
(voltage IJ Ill oscillator), 5... frequency divider,
6... Abnormality detection circuit, 7... Selector, 8... Reset signal, 9... Selector control signal, 10... vCO output signal.

Claims (1)

[Claims] a voltage controlled oscillator, a resettable frequency divider that divides the frequency of its output signal, a selector that selects the output of the frequency divider and a reference clock, an abnormality detection circuit that detects an abnormality in the reference clock; It has a phase comparator that compares the phase of the selector output and the reference clock and converts the phase difference into a voltage, and a low-pass filter, and controls the oscillation frequency of the voltage-controlled oscillator with the output voltage of the low-pass filter. Phase synchronized oscillator circuit.