JPH06276089A - Pll circuit - Google Patents

Abstract

PURPOSE:To detect a phase difference and to delay a feedback signal by a corresponding time. CONSTITUTION:The PLL circuit consists of a phase comparator 1 which detects the phase difference between an input signal 10 and the feedback signal 12 and outputs a signal corresponding to the phase difference, a low-pass filter 2 which inputs and converts the signal corresponding to the phase difference into a DC voltage and outputs it, a voltage-controlled oscillator 3 which is cascaded to the low-pass filter 2 and controlled with the DC voltage supplied from the low-pass filter 2 to generate a specific output (clock) signal 11, a frequency divider 4 which divides the frequency of the output signal of the voltage-controlled oscillator 3, a delay part 5 which generates a feedback signal 12 delayed by the specific time under the control of a delay control part 6 and outputs the feedback signal 12 to the phase comparison part 1, and the delay control part 6 which generates a delay quantity control signal on the basis of the signal, outputted by the phase comparison part 1, corresponding to the phase difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit for feeding back a feedback signal delayed by a predetermined time to a phase comparator.

[0002]

2. Description of the Related Art In a clear vision (EDTV) or the like, for example, a PLL circuit (block diagram) shown in FIG. 3 is used in order to obtain a clock signal which is phase-synchronized with a horizontal synchronizing signal of a broadcast color television signal. Reference numeral 31 is a horizontal synchronizing signal 4 of a broadcast color television signal input as a reference signal.
0 and the feedback signal (horizontal synchronizing signal) 42 obtained by dividing the clock signal 41 oscillated and output by the VCO 34 by the counter 37, and generating a signal according to the phase difference between the two signals. Is. 32 is the phase comparator 3
A low-pass filter (LPF) that receives a signal corresponding to the phase difference from 1 and generates a DC voltage based on the signal. Three
A voltage controlled oscillator (VCO) circuit 4 controls the oscillation frequency and phase based on the DC voltage to generate and output a desired clock signal 41. 37 is the clock signal 4
It is a counter (frequency divider) that divides 1 by a predetermined ratio to generate a feedback signal 42. However, the conventional PLL described above
In the circuit, there may be a large phase difference between the feedback signal 42 and the reference signal 40 depending on the power-on timing and the like, and the VCO that is cascade-connected with the LPF 32 is generally used.
Due to the slow convergence speed determined by the overall characteristics of 34, it was not possible to generate a stable clock signal 41 phase-locked with the horizontal sync signal 40 within a predetermined convergence time.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems. When an input (reference) signal is supplied, a clock signal phase-synchronized with the input signal is output within a predetermined time. It is an object of the present invention to provide a PLL circuit that can be used.

[0004]

In order to achieve the above object, a phase comparator for detecting a phase difference between input signals and outputting a signal corresponding to the phase difference, and a signal output by the phase comparator. A low-pass filter for inputting and converting to a direct-current voltage, a voltage-controlled oscillating unit that is connected in cascade to the low-pass filter and that generates a signal of a predetermined oscillation frequency controlled by the direct-current voltage and outputs the signal, and the voltage In a PLL circuit including a frequency divider that divides an output signal of a control oscillating unit and is feedback-connected to the phase comparing unit, a delay amount control signal is generated based on a signal according to a phase difference output from the phase comparing unit. And a delay unit for delaying the output signal of the frequency divider by a predetermined time under the control of the delay control unit and feedback-connecting it to the phase comparison unit.

[0005]

With the above-described structure, for example, within a period of a half cycle of the output signal before dividing the phase difference of the feedback signal based on the signal corresponding to the phase difference input to the delay control unit. As described above, the signal is delayed by the delay unit and fed back to the phase comparison unit. Next, a low-pass filter, a voltage controlled oscillator, a frequency divider, a delay unit that holds the delay time, and a comparison unit for phase differences within a half cycle period while holding the delay time. The feedback circuit performs the convergence operation.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a PLL according to the present invention.
It is an example block diagram of a circuit. Reference numeral 1 is a phase comparator which detects a phase difference between the input signal 10 and the feedback signal 12 and outputs a signal corresponding to the phase difference. Reference numeral 2 is a low-pass filter that inputs a signal corresponding to the phase difference, converts the signal into a DC voltage, and outputs the DC voltage. Reference numeral 3 is a voltage-controlled oscillator that is connected in cascade to the low-pass filter 2 and is controlled by the DC voltage supplied by the low-pass filter 2 to generate a predetermined output (clock) signal 11. Reference numeral 4 is a frequency divider for dividing the output signal of the voltage controlled oscillator 3. Reference numeral 5 is a delay unit that generates a feedback signal 12 by delaying the output signal of the frequency divider 4 by a predetermined time under the control of the delay control unit 6 and outputs the feedback signal 12 to the phase comparison unit 1. Reference numeral 6 is a delay control unit that generates a delay amount control signal based on the signal corresponding to the phase difference output from the phase comparison unit 1.

The operation of the PLL circuit according to the present invention will be described. FIG. 2 is a diagram showing the delay time based on the phase difference of the comparison (feedback) signal with respect to the input (reference) signal in the PLL circuit according to the present invention. Reference numeral 20 is an input (reference) signal, and 21 is a feedback (comparison) signal having a phase difference (delay) 23 and having a repeating period 22. 27 is an output (clock) signal of the voltage controlled oscillator 3. Delay control unit 6
Detects the phase difference (delay) 23, and the delay unit 5 delays the feedback signal 21 by a time 24 which is substantially the difference between the repeating period 22 and the phase difference (delay) 23. As a result, for example, the delayed feedback signal has a phase difference 25 within one half of the cycle of the output (clock) signal 27.

[0008]

As described above, according to the present invention, when an input (reference) signal is supplied, a PLL circuit capable of outputting a stable clock signal phase-synchronized with the input signal within a predetermined time. provide. Therefore, in clear vision or the like, it is possible to supply a stable clock signal that is phase-synchronized with the input horizontal synchronizing signal within a predetermined time such as channel switching and power-on. Further, since a large phase difference can be removed by delaying the feedback signal, the convergence time is shortened, and accordingly, the time constant of the low pass filter can be increased and the frequency stability of the output signal can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing a delay time based on a phase difference between a comparison (feedback) signal and an input (reference) signal in a PLL circuit according to the present invention.

FIG. 3 is a block diagram of an embodiment of a conventional PLL circuit.

[Explanation of symbols]

 1 phase comparator 2 low-pass filter 3 voltage controlled oscillator 4 frequency divider 5 delay unit 6 delay control unit 10 input signal 11 output (clock) signal 12 feedback signal 20 input (reference) signal 21 feedback (comparison) signal 22 feedback ( Comparison) Signal repetition period 23 Phase difference (delay) 25 Phase difference within 1/2 27 Output (clock) signal 31 Phase comparator 32 Low pass filter (LPF) 34 Voltage controlled oscillator 37 Counter 40 Input signal 41 Clock signal 42 Feedback signal

Claims (1)

[Claims] 1. A phase comparison unit that detects a phase difference between input signals and outputs a signal corresponding to the phase difference, and a low-pass filter that inputs the signal output by the phase comparison unit and converts it into a DC voltage. A voltage-controlled oscillation unit that is connected in series to the low-pass filter and that generates a signal of a predetermined frequency controlled by the DC voltage and outputs the signal; and a frequency-divided phase of the output signal of the voltage-controlled oscillation unit. In a PLL circuit including a frequency divider that is feedback-connected to a comparison unit, a delay control unit that generates a delay amount control signal based on a signal corresponding to the phase difference output by the phase comparison unit, and an output signal of the frequency divider. Is delayed by a predetermined time under the control of the delay control unit and is feedback-connected to the phase comparison unit, and generates a delay amount control signal based on the phase difference signal input by the delay control unit. Control Based on the signal,
A PLL circuit characterized in that the output of the frequency divider is delayed by a corresponding time and is feedback-connected to the phase comparison unit to synchronize the phase of the feedback signal with the reference signal.