JPS61289768A - Freeze control start discrimination system for frame synchronizer - Google Patents

Abstract

PURPOSE:To correct completely a chroma phase at the memory readout side by comparing the polarity of a frame pulse and an ODD/EVEN field pulse obtained by a storage means with the polarity of two pulses of the same kind at the read side. CONSTITUTION:A polarity holding circuit 5-4 fetches the polarity of a frame pulse (i) and a field pulse (j) at the start point of time of a write inhibition pulse (k) and outputs a frame pulse (l) and a field pulse (m) while keeping the polarity respectively. Further, a synchronizing signal of a synchronization separating circuit 11 at the read side is given to a frame pulse generator 5-5 and an ODD/EVEN field pulse generator 5-6 in the same way as the write side and a read side frame pulse (n) and a read side field pulse (p) are obtained. A polarity comparison circuit 5-7 outputs a polarity inversion command (q) and a chroma inversion command (d) of the read field pulse according to the logic under the condition that a write inhibition pulse (k) is set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a freeze control start determination method for a frame synchronizer provided as television studio equipment.

[Conventional technology]

Conventionally, in this type of frame synchronizer, internal control operations are often performed at a frequency four times that of the subcarrier. According to this, the memory write address and continuation address are.

Each address is divided into H address and ■ address.

Furthermore, by always setting the H address at a point at the same phase with respect to the horizontal synchronizing signal as the starting point of the address, various processing becomes easier. but.

On the other hand, one function of the frame synchronizer is that when the input video signal is switched to a video signal with a different phase and frequency from the previously input signal (different synchronization signal), it detects this and then starts the new input signal. Writing of video data to memory 1 is temporarily suspended until a vertical synchronization signal (V synchronization) is input. Then, until a stable new signal is obtained as the output of the frame synchronizer, the signal before switching, that is, the frame synchronizer sends out the signal one frame before, to eliminate disturbances when switching input signals. Since the color phase (chroma phase) of the signal one frame before is inverted, a 1 nichroma inversion circuit is added to correct this.

However, in such a conventional frame synchronizer, the timing at which the chroma inversion circuit is effectively stored is limited to the start point (address 0 of the frame period) of the successive address that controls memory successive access. Therefore, if the input is switched in the middle of the video signal and the write protection circuit is activated (; means that the chroma signal cannot be corrected for the period of the first screen, and the color phase shifts by 180 degrees. is obtained on the output side as .

To eliminate this inconvenience, :: sets the start of the H address to the same A as the subcarrier phase (burst phase) of the input signal.
I had no choice but to do 1.

[Problem that the invention seeks to solve]

The object of the present invention is to apply a frame synchronizer whose addresses are configured such that the start of the address always has the same phase relationship with the input horizontal synchronization signal, even if write protection is activated at any time.

Two complete chroma phase corrections are performed on the memory read side.
Another object of the present invention is to provide a freeze control start determination method that does not cause any disturbance on the output screen.

[Means for solving problems]

The control start determination method according to the present invention includes a frame memory for writing digital input video information, a means for prohibiting writing of data to the frame memory, and a means for inhibiting writing of data read from the frame memory. A frame synchronizer includes freezing means for comparing the polarities of the read side frame pulse and the read side frame pulse, receives the write side frame pulse and the ODD/EVEN field pulse, and outputs the write inhibit frame pulse and the ODD/I1iVIN. A means for storing the polarity of each field pulse, and comparing the two polarities of the frame pulse and ODD/EVEN field pulse obtained by the storing means with the polarity of two pulses of the same type on the readout side, and predetermining the polarity of each field pulse. polarity comparison means for controlling the polarity of the ODD/FiVEN field pulse on the writing side and the chroma phase of the freezing means, respectively, based on the logical conditions (Y), and a polarity comparison means for controlling the inhibit output of the write inhibiting means on the reading side. The present invention is characterized in that it has a write inhibit timing conversion means that captures data at a field start phase of , and sends it as a freeze pulse to the freeze means.

[Embodiments of the invention]

Next, a freeze control start determination method according to the present invention will be described with reference to an embodiment and one drawing.

Figure 1 shows the invention! FIG. In this example: Input video signal a is applied to input terminal 1, converted into digital data at a frequency four times that of the subcarrier at A/D converter 21, and then written to frame memory 3. On the other hand, the video data read from the frame memory 3 is added to the freeze circuit 4:2, where the polarity is compared with the write-side frame pulse b and the read-side frame pulse n superimposed on the video data. . If the two do not match, the built-in chroma inversion circuit is operated to invert the macro phase only when the freeze pulse e is on. However, from the freeze control start determination circuit 5, the freeze pulse e
If the chroma inversion command d is not obtained, the chroma inversion command d sent from the freeze control start determination circuit 5 gives priority to the chroma inversion circuit. The output video data of the freeze circuit 4 is converted into an analog signal by the D/A converter 6 and then output from the output terminal 7.

The synchronization component of the input video signal a is extracted by the synchronization separation circuit 8, and a write address is generated by the write address generator 9 using it as a reference. Similarly, input terminal 10
The reference synchronization signal given to is applied to the successive address generator 12 via the synchronization separation port WIt11, where the successive address is generated. Memory control candy 13 is
In response to the write inhibit pulse from the freeze control start determination circuit 5, the write side field pulse j and the read side field pulse hl, control signals necessary for writing and reading from the frame memory 3 are generated. Note that ODD field information is determined by the polarity of the memory field pulse h on the read side.

Alternatively, the information in the EVEN field can be freely obtained as a memory output.

FIG. 2 is a block diagram showing a specific example of the configuration of the freeze control start determination circuit in the embodiment of FIG. 1. Please refer to this diagram.

The synchronization component extracted from the input video signal a by the synchronization separation circuit 8 (=) is sent to the frame pulse generator 5-1 and O
DD/KVK and N field pulse generator 5-2, where the write side frame pulse (polarity inverted every frame) 1 and the write side field pulse (O
The polarities of the DD field and the EVEN field are reversed. The above-mentioned synchronization component is also applied to the write inhibit pulse generator 5-3, which detects any disturbance in the input synchronization signal and generates a write inhibit pulse k. In the polarity holding circuit 5-4, the frame pulse 1 at the start point of the write inhibit pulse is
and field pulse j, and output them as frame pulse t and field pulse m, respectively, while maintaining the polarities. Also, the reading side as well as the writing side,
The synchronization signal of the synchronization separation circuit 11 is generated by the frame bus/L/bus generator 5-5 and the ODD/EVEN74-rudo bus generator 5.
-6, and here a readout side frame pulse n, readout side f, and yield pulse p are obtained, respectively.

In the polarity comparison circuit 5-7, the above pulses L, m
, n and p, and under the condition that the write inhibit pulse k is set, the polarity reversal command q and the chroma reversal command d of the read-side field pulse are executed according to the logic shown in FIG.
Outputs . The field pulse polarity inversion circuit 5-8 inverts the polarity of the read-side field pulse p according to the polarity inversion command pulse q, and sends it to the memory control circuit 13 as a read-side field pulse h for memory. The write-inhibit pulse timing conversion circuit 5-9 receives the write-inhibit pulse k, converts the start timing according to the read-side field start < Output to 4.

FIG. 4 is a time chart for explaining the operation obtained by the above embodiment. If we look at the phase correspondence between the write side and the read side in this chart, we can see that during the write inhibit period A, the read side field pulse is inverted during the B period on the read side, and the previous field pulse is inverted during the B period. and the operation of reading out the information.

Since the freeze pulse is set during the C period, the determination circuit in the freeze circuit receives the color information contained in the memory and the read-out frame pulse, and performs an operation to invert the chroma phase.

Period D indicates a normal output period. According to this,
Not only will the chroma phase shift be eliminated, but even if the image is distorted even before the write-protect operation is activated, the effect can be suppressed by replacing the distorted image with the picture information of the previous field before reading it out. Can be removed. 1. For comparison with the present invention, referring to the time chart of FIG. 5 for the conventional method, when writing is prohibited at the start point of the write-inhibited period of A, the reading side.

That is, since the information of the previous frame is output in period B on the output screen, the chroma phase is shifted by 180 degrees.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the frame synchronizer has an address structure such that the start of the address always has the same phase relationship with the input horizontal synchronizing signal.

Even if write protection is activated at any point in time, the chroma phase is completely corrected on the memory read side, and there is no disturbance on the output screen.

The effect obtained is profound.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention;
FIG. 2 is a block diagram showing a specific example of the structure of the freeze control start determination circuit in the embodiment shown in FIG. 1, and FIG. 5 shows the logic for sending out the field pulse inversion command and the chroma inversion command in the polarity comparison circuit. 4 are time charts for explaining the operation obtained by the embodiment of the present invention, and FIG. 5 is a time chart for explaining the operation obtained by the conventional method. In the figure, 2 is an A/D converter, 5 is a frame memory,
4 is a freeze circuit, 5 is a freeze control start determination circuit, 6
1 is a D/A converter, 8.11 is a synchronization separation circuit, 9 is a write address generator, 12 is a continuous address generator, 13 is a memory control circuit, and 5-1.5-5 is a frame pulse generator. 5-2.5-6 is ODD/KVKN7 pulse generator, 5-3 is write inhibit pulse generator, 5-4 is polarity holding circuit, 5-7 is polarity comparison circuit, 5-8 is A field pulse polarity inversion circuit and 5-9 are a write inhibit pulse timing conversion circuit.

Claims (1)

[Claims] 1. A frame memory into which digitized input video information is written, a means for inhibiting writing of data to the frame memory, and a frame pulse on the writing side and a frame on the reading side upon receiving the data read from the frame memory. In a frame synchronizer including a freezing means for comparing the polarity with the write side frame pulse and the O
means for receiving the DD/EVEN field pulse and storing the polarities of the frame pulse and the ODD/EVEN field pulse, respectively, at the time when writing of video information to the frame memory is stopped due to an inhibit output of the write inhibiting means; The two polarities of the frame pulse and ODD/EVEN field pulse obtained by the storage means are compared with the polarities of two pulses of the same type on the reading side, and the polarity on the writing side is determined based on predetermined logic conditions. polarity comparison means for respectively controlling the polarity of the ODD/EVEN field pulse and the chroma phase of the freezing means; and a polarity comparison means that captures the inhibit output of the write inhibiting means at the field start phase on the reading side and sends it to the freezing means as a freeze pulse. 1. A freeze control start determination method for a frame synchronizer, comprising a write inhibit timing converting means for transmitting a write.