KR900001644B1 - Buffer memory reducing method for digital television - Google Patents

Abstract

The method comprises a first step for detecting the initial writing time utilizing an AND gate, a second step for converting analog picture signal to digital signal, a third step for recording the picture data on a buffer memory (6) when the buffer memory is in writing mode and a field memory is in decoding mode, and for recording the picture data when the field memory is not in writing mode, a fourth step for decoding the picture data when the buffer memory is not in writing mode and the field memory is in decoding mode, and for transmitting data from the buffer memory to the field memory when the field memory is not in decoding mode and then the picture signal returns to the second step.

Description

Buffer Memory Capacity Reduction Method for Multiple Image Circuits for Multiple Image Digital TV Receivers

FIG. 1A shows a screen of a multi-image digital TV receiver, and FIG. 1B shows a circuit diagram of a multi-image digital TV receiver.

2 is a flow chart for explaining the present invention method.

3A and 3B are waveform diagrams for explaining the present invention, and FIG. 3C is a circuit diagram of a multiple image processing circuit in which the present invention method is implemented.

4 is a circuit diagram for detecting a starting point for storing in a buffer memory in the present invention method.

5A and 5B are detailed circuit diagrams and operational waveform diagrams of the memory controller 8 of the present invention.

6 is a circuit diagram of a conventional multi-image processing circuit.

7A-7C are waveform diagrams of a conventional multiple image processing circuit.

The present invention relates to a multiple image circuit for a multiple image digital TV receiver, and more particularly, to a signal processing method for reducing a buffer memory capacity in a multiple image circuit.

In general, a multi-image digital TV refers to a sub-screen 31 that is as small as 1/9 or 1/4 of the full screen size in the TV main screen 30 as shown in FIG. 1A. The sub-screen 31 can watch different broadcasts at the same time.

As shown in FIG. 1B, a typical multi-image digital TV is configured to receive a TV signal from the antenna 32, tune it in the tuner 33, amplify the signal tuned as the intermediate amplifier 35, and VTR (34). To the same level as the output. The multiplexer 36 selects which of the polarized signals and the output of the VTR 34 are the main screens and which are the sub-screens, so that the signals for the main screens are connected to the digital TV circuits through the analog-to-digital converter 37. 38), and the sub picture signal is applied to the multiple image processing circuit 39 through the analog-digital converter 37 '.

The multiple image processing circuit 39 has a function of reducing the size of the screen by the input signal and displaying it on a part of the main screen 30 as the sub screen 31.

In the conventional multi-image processing circuit 39, as shown in FIG. 6, the composite image signal from the multiplexer 36 is input to the image signal processing IC 390, so that the luminance signal Y and the color difference signal RY, BY. ) Is passed through the low pass filter (391).

The signals (Y, RY, BY) passing through the low pass filter (391) pass through the multiplexer (392) and are respectively converted into digital signals by the analog-to-digital converter (393) and the buffer memory by the memory controller (396). The data recorded in 394 is then decoded by the multiplexer 40 in the filter memory 395 and sent to the digital-to-analog converter 41 (see also FIG. 1B).

For example, if the sub screen 31 is made to be 1/9 of the main screen 30, it is reduced to 1/3 vertically and 1/3 horizontally. In this case, one scan line is sampled in the field memory 395 vertically every three scan lines, and one dot is sampled every three dots horizontally, thus eliminating the operation for 1/9 reduction. 7a and b, the horizontal synchronization signal is shown in FIG. 7a, the write period of the field memory 395 is shown in FIG. 7b, and the field memory 395 is decoded in FIG. 7c. The period is shown. That is, in the case of the time t ₁ in FIG. 7C, since the data must be simultaneously written and read into the field memory 395, the memory call time should be fast. To solve this problem, the data is stored in the buffer memory 394 at the data write time t ₂ by using the buffer memory 394 to separately write and decode the field memory 395. The data is transferred from the buffer memory 394 to the field memory 395 during the idle time t ₃ and t ₄ .

In the data decryption period t ₁ , data is decrypted in the field memory 395. Therefore, since the data writing period is one horizontal scanning line period (1H), the capacity of the buffer memory 394 must be able to accommodate data corresponding to one horizontal scanning line period of the signals (Y, RY, BY), where the memory decoding The period t ₁ is one third of the memory write period t ₂ . However, in such a conventional device, since data is stored in the buffer memory and then transferred to the field memory, the size of the buffer memory is large enough to store signals (Y, BY, BY) corresponding to one horizontal scan line. As the size of the buffer memory increases, the installation area increases, and the time to transfer data from the buffer memory to the field memory increases.

The present invention records the corresponding data in the buffer memory during the 1/3 horizontal scanning period in which the digital signal from the A / D converter is simultaneously decoded and written to alleviate this disadvantage. During the period, the data is distributed to the field memory for recording, thereby reducing the buffer memory capacity to 1/3 compared with the conventional case, and at the same time, reducing the time required to transfer data from the buffer memory to the field memory by 1/3. It is an object of the present invention to provide a method for reducing the capacity of a buffer memory of a multi-image circuit for a TV receiver. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, there is shown a flow chart for implementing the present invention. Referring to the present invention, the present invention is described in the case where the write time of the field memory 7 and the readout time of the buffer memory 6 overlap at the same time. Determined as the AND gate 1, the memory controller 8 detects the start point of the write operation of the buffer memory 6, converts the video signal to analog digital conversion as the converter 5, and then enters the field if the buffer memory 6 is in the write state. The decryption state of the memory 7 is determined so that if the field memory 7 is in the decrypted state, the data is written to the buffer memory 6, and if the field memory 7 is not in the decrypted state, the data is stored in the field memory 7. If the buffer memory 6 is not in the write state, the decryption state of the field memory 7 is determined. If the field memory 7 is in the decrypted state, the data of the field memory 7 is decrypted and the field memory 7 is read. Detoxification status If not, the data is transferred from the buffer memory 6 to the field memory 7 and then returned to the analog / digital conversion of the video signal as the converter 5.

The detailed circuit of the memory controller 8 is configured as shown in FIG. 5A, and its operation relationship is explained with reference to FIG. 5B. As shown in FIG. 5A, the horizontal synchronization signal is equal to the clock terminal CLK of the counter. When inputted to the monostable multivibrator, the counter counts and sends a signal to the comparator so that one comparator compares the 0th signal of (a) and the other comparator compares the 2nd signal, and (b) and (e) respectively. The same signal is output, and the signal (g) (buffer memory readout signal) is obtained through the OR gate of the signal (c) and the signal (f) which invert the signal (b) through the inverter, and the signal (e) and the field memory. The (f) signal, which is the readout signal, is obtained through the AND gate, and the (h) signal (buffer memory write signal) is obtained. The (f) and (e) signals inverted the (f) and (e) signals and the (g) signal described above are obtained. Obtains (i) signals, which are field memory write signals, respectively through the OR gate .

The buffer memory readout signal g and the buffer memory write signal h obtained in this way are applied to the buffer memory 6, and the field memory readout signal f and the field memory write signal i are stored in the field memory 7; To be added.

Next, the present invention will be described in more detail with reference to Figs. 3a-b. As shown in Fig. 3c, the composite video signal is converted into a signal (Y, RY, BY) by the image signal processing IC 2, and then low pass. It is applied in parallel to the multiplexer 4 through each of the filters 3. In the multiplexer 4, the signals Y, R-Y, and B-Y input in parallel are sequentially output and applied to the analog digital converter 5 to convert them into digital signals.

The converted digital signal is simultaneously applied to the buffer memory 6 and the field memory 7, but the driving of the buffer memory 6 and the peak memory 7 is controlled as the memory controller 8. In FIG. The waveform diagram of the memory 6 write drive signal (that is, the signal (h) in FIG. 5B) is displayed, and the pulse width t of this drive signal has a period of 1/3 horizontal scan line.

Further, in FIG. 3B, the waveform diagram of the read drive signal of the field memory 7 (i.e., the signal (f) in FIG. 5B) is shown.

Here, the field memory 7 drive signal pulses also have a period t of 1/3 horizontal scan lines and there are three pulse memory drive pulses in the buffer memory drive signal section in which one buffer memory drive pulse exists. I can see.

In particular, the reason for using the buffer memory is to decipher and decode the memory. Therefore, as in the case of FIGS. 3A and 3B, only data corresponding to one-third horizontal syringe stem (t) in which recording and decoding are simultaneously performed is performed. It is written to the buffer memory and directly to the field memory between the remaining 2/3 horizontal syringes.

By doing so, the capacity of the buffer memory is reduced by 2/3 compared with the conventional case.

In addition, the starting point for writing data to the buffer memory 6 is to input the buffer memory write drive signal (Fig. 3a) and the field memory read / write signal (Fig. 3b) to the AND gate 1 so that it is only available at time t. The output is generated to be the rising edge of the output pulse.

As described above, according to the present invention, since the buffer memory has a size corresponding to 1/3 horizontal scanning line, the buffer memory installation area is reduced, and the overall size is not only reduced, but the amount of transition data is reduced to 1/3 so that the buffer memory Data transfer time from field to field memory can be shortened, so there is room for digital TV operation, which can prevent malfunction and reduce product cost.

Claims (1)

When the recording time of the field memory 7 and the decoding time of the buffer memory 6 overlap at the same time as the AND gate 1, the memory controller 8 detects the start point of the recording operation of the buffer memory 6, The signal is converted into an analog-to-digital signal by the A / D converter 5, and then the decoding state of the field memory 7 is determined when the buffer memory 6 is in the recording state, and data is read out when the field memory 7 is in the decoding state. To write to the buffer memory 6, to write data to the field memory 7 if the field memory 7 is not in the read state, and to read the field memory 7 if the buffer memory 6 is not to the write state. When the field memory 7 is in the decrypted state, the data in the field memory 7 is decrypted so that the data is transferred from the buffer memory 6 to the field memory 7 when the field memory 7 is not in the decrypted state. Next, the video signal is again converted into analog / D as an A / D converter (5). Buffer memory capacity of the multi-image circuit for multi-image digital TV receivers returned to the step of converting the multi-image signal to the analog / digital signal with the A / D converter 5 by returning to the step of converting to the digital signal Way.

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