JPS6128218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device having a small construction area and excellent input clamping characteristics.

What is most desired in designing a semiconductor integrated circuit is how to design one with a small area and good characteristics.

In other words, in an attempt to make the chip smaller, it may not be possible to satisfy the electrical characteristics required for the integrated circuit, or conversely, in order to improve the electrical characteristics, a large number of elements and a large number of wiring lines are used. It is undesirable for this to lead to an increase in the chip area.

Based on the above, designers of semiconductor integrated circuits reduce the overall chip area by reducing the number of elements used as much as possible, reducing the area of each element within a range that does not adversely affect characteristics, and conducting wiring effectively. We must try to do so.

When designing a multi-functional integrated circuit, the wiring becomes complicated, and in some cases it is better to take common wiring within the circuit, such as power supply Vcc and ground GND wiring, and route it to the outside of the electrode (pad) to improve the topology of the wiring. It is often easier.

However, wiring outside the pad in this manner has a large adverse effect due to the bonding wire touch, and also makes it impossible to design an integrated circuit with a beam lead structure. Furthermore, this structure increases the difference in chip area between the spacing required between the pad and the external wiring and the spacing required between the internal wiring. Although routing the wiring outside the pad in this manner makes the wiring somewhat easier topologically, it has many drawbacks as described above.

One way to counter this problem is to use multilayer wiring technology, which creates multiple layers of wiring by sandwiching insulators, but this increases the number of steps and, in addition, makes it difficult to make electrical connections (through holes) between wiring layers, resulting in lower yields. There are negative effects such as a decrease in

On the other hand, a commonly used method is to use a highly doped N-type layer (N ⁺ layer) as a wiring, and this is usually called a tunnel wiring structure.

According to this method, although some resistance is introduced into the wiring, it can be formed by emitter diffusion (N ⁺ diffusion) and there is no need to increase the number of special steps. In other words, it can be seen that the N ⁺ tunnel wiring method is a very effective method for wiring design of complex circuits.

On the other hand, TTL (transistor
When a logic circuit network is constructed using DTL (diode transistor logic) or DTL (diode transistor logic),
Reflections that occur between the transmitting side and the receiving side when the signal changes may cause the input voltage of the receiving side circuit to swing to a large negative value. If this negative voltage is too deep, the swing from the GND (ground) level, which returns by multiplying the reflection coefficient, to the positive side will also become large, and if this swing on the positive side is greater than the threshold voltage of the circuit, this The receiver input will not eventually go to a low level unless the side deflection is reduced below the threshold voltage. In other words, the time from when the output on the transmitting side shifts from one logic level to the other until the output on the receiving side finally settles to the corresponding logic level is the negative potential on the receiving side due to the above reflection. It depends largely on the magnitude of the swing.

In other words, when designing TTL and DTL, it is necessary to provide some kind of input clamp circuit to prevent the input point from becoming more negative than the GND level. An input clamp circuit is constructed by inserting diodes 202 and 203 between which the anode is connected to GND and the cathode is connected to the input.

A plan view of a conventional example in which this input clamp diode is constructed using the tunnel wiring structure described above is shown in the second figure.
In addition, the sectional view in the A-A' direction of Figure 2 is shown in Figure 3.
As shown in the figure.

An N-type buried layer 2 is provided in a P-type semiconductor substrate 1, an N-type layer is epitaxially grown thereon, and a P-type insulating isolation layer 4 is diffused to form an island 3 of the N-type layer. Thereafter, a high concentration N layer 6 is formed on the island 3 by selective diffusion, and an insulating film 7 is formed. After that, portions 81, 82, and 83 are opened, and Al wiring layers 91, . . . , 96 are provided.

In addition, 100 is the pad of the input terminal, 94, 9
5 and 96 indicate general wiring including Vcc, and 93
shows the GND wiring at a distance from the wiring tunnel, and the insulating region is connected to the lowest potential at 83.

FIG. 4 shows an equivalent circuit diagram of FIGS. 2 and 3. 101 indicates a PN junction diode formed between region 4 and regions 3 and 6 in FIG. 3, and 4' indicates 9.
3 to the above-mentioned PN junction, and 6' shows the resistance due to region 6 from 82 to 81.
In FIGS. 2 to 4, the wiring 92 (which is connected to the emitter of the input gate transistor 5 in FIG. 1) is omitted from illustration. ).

As shown in the above diagram, there is no GND wiring near the tunnel area of the input wiring, and the insulation area is located far away through many islands that form other elements in the circuit.
When connected to GND, the resistor 4' in Figure 4 (hereinafter referred to as Γ _B ) becomes very large, which in turn increases the drop to negative voltage at the input point due to a certain input draw current. Put it away.

That is, in FIG. 4, the input draw current I
The relationship between _I and the input voltage V _I can be approximated as V _I = V _D + I _I · Γ _B (1), where the forward voltage of the PN diode is V _{D , and as Γ B increases} , It can be seen that V _I also becomes large. Note that in equation (1), the symbols indicate absolute values.

Here, in order to reduce Γ _B , it is better to bring the contact 83 closer to the island 3, but there are other
If GND wiring is not required, place it near area 3.
Routing GND wiring around the circuit is inefficient and inevitably increases the chip area.

In the conventional structure in which the PN diode formed between the tunnel island and the insulating region is used as the input clamp diode, when there is no GND wiring nearby, the series resistance of the P region of the PN diode becomes large, and the input The drawback was that the input could not be sufficiently clamped when the draw current was large.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device having extremely excellent input clamping characteristics without increasing the number of elements.

In the present invention, after separating the tunnel island that forms part of the input wiring, a part of the N-type epitaxial region is left, the base is diffused so as to overlap with the insulating region, and the insulating layer is separated to form the wiring above the tunnel. By making contact between the Vcc line that is connected to the base, or the wiring that provides a high potential with low impedance, and the base-diffused epitaxial region, an NPN transistor with Vcc as the collector, GND as the base, and the input as the emitter can be formed. It is characterized by the formation of

That is, according to the present invention, a first conductive type semiconductor substrate, a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate, and a plurality of second conductive type first semiconductor layers formed on the second conductive type semiconductor layer are provided. The first region is separated by a PN junction.
In a semiconductor integrated circuit device in which a second conductivity type region and a highly concentrated second conductivity type third region provided in the second conductivity type first region serve as an input wiring layer, the first conductivity type semiconductor second region and a fourth region of the first conductivity type formed at least partially overlapping the first region of the semiconductor of the second conductivity type; and the third region of the high concentration second conductivity type is provided in the fourth region of the first conductivity type. , there is obtained a semiconductor integrated circuit device characterized in that a ground electrode is provided in the second region or the fourth region of the first conductivity type.

Next, embodiments of the present invention will be described using the drawings.

FIG. 5 is a top view showing one embodiment of the present invention, and FIG.
The figure is a sectional view taken along line AA' in FIG. 5, FIG. 7 is a sectional view taken along line BB' in FIG. 5, and FIG. 8 is an equivalent circuit diagram thereof.

I is a P-type semiconductor substrate, 2 is an N-type buried layer, and 3 is a P-type semiconductor substrate.
In the N type epitaxial layer formed on the type semiconductor substrate 1, an island-shaped first region is formed by the P type insulating separation layer 4 (second region). This island-like first
In the region 3, a P-type impurity is diffused leaving the region 31 to form a P-type fourth region 5, and a third region 61 is formed thereon by diffusing a high concentration N-type impurity. . At this time, a high concentration of N-type impurity is diffused also in the region 31 to form a region 62. Furthermore, openings 81, 82, 8 are formed in the insulating film 7 formed thereon.
3 and 84 are provided, and aluminum wiring layers 91 to 96 are provided to cover these openings.
Note that 100 is the pad of the input terminal, and 93 is the part separated from the wiring tunnel (third area 61).
GND wiring, 94 is Vcc wiring, and 95 and 96 are general wiring.

Note that the wiring 92 is connected to, for example, the emitter of the input gate transistor of the TTL gate circuit, but is not shown because it is cumbersome.

As is clear from this embodiment, the equivalent circuit of the main part of the present invention is shown in FIG. Resistor 4' is a resistance caused by the insulating region 4, and resistance 61' is a resistance caused by the heavily doped N-type region 61.

Next, the functions and effects of the present invention will be explained.

Input 91 changes from GND potential to negative potential, and PN
Voltage for one stage of diode forward voltage (approximately 0.7V)
When the value becomes more negative, the emitter junction of transistor 102 in FIG. 8 becomes forward biased, and transistor 102 begins to operate. i.e. Vcc
A collector current of the transistor 102 flows from the wiring 94, and the sum of this current and the base current flowing from the GND wiring 93 flows out as an input current. At this time, most of the input current comes from the collector current of the transistor. Therefore, even when a large input current is drawn, according to the present invention, the voltage drop caused by the resistor 4' is small, and the input clamping characteristics of the semiconductor integrated circuit are significantly improved.

Next, to explain this in detail, if the current amplification factor of the transistor 102 is h _FE , the base-emitter forward voltage is V _BE , and the resistance value of the resistor 4' is Γ _B , then the input voltage V _I is V _I = V _BE +R _B・I _I /h _FE ...(2). Comparing the equation showing V _I in the conventional case [Equation (1)] and the equation [Equation (2)] in the case of the present invention, it is found that Equation (1)
I _I in the formula becomes I _I /h _FE in formula (2). That is, for the same I _I , the voltage drop due to the resistance Γ _B in the present invention [Equation (2)] is 1/h _FE compared to the conventional [Equation (1)], and the parasitic effect is significantly It can be seen that the negative influence of the resistance Γ _B has diminished.

Next, another embodiment of the present invention will be described.

FIG. 9 is a plan view showing another embodiment of the present invention, and FIGS. 10 and 11 are A--A in FIG. 9, respectively.
They are an A' cross-sectional view and a B-B' cross-sectional view.

In this embodiment, an area is provided in the island 3 in which the circuit-required resistor 103 in the logic circuit is formed as a P-type diffusion layer 52 to have the same effect as the fourth area 5 shown in FIG. 51 is provided, and a high concentration of N-type impurity is diffused into the region 51 to form a region 61, and this portion is used as a tunnel wiring. It is clear that even in this case, an NPN transistor is formed between the wiring tunnel region 61 made of high concentration N-type impurity, the region 51 or 4, and the region 62, and the equivalent circuit is shown in FIG.

Note that the aluminum wiring 96 and the heavily doped N-type region 62 are necessary for the resistor 103 (P-type diffusion layer 52).

In these embodiments, the drop in the negative voltage at the input point due to the input draw current is improved, for example, from -13V to -0.9V under predetermined conditions and arrangement relationships.

As explained in detail above, according to the present invention, there is no need for base electrode wiring, and the layout of Vcc wiring only needs to be slightly modified, so that extremely excellent input clamping characteristics can be achieved without increasing the occupied area. A semiconductor integrated circuit device can be obtained.

[Brief explanation of the drawing]

Figure 1 shows a typical semiconductor integrated circuit device with an input clamp diode, which is an example of a conventional semiconductor integrated circuit device.
A circuit connection diagram showing an example of a TTL circuit, FIG. 2 is a plan view illustrating a conventional semiconductor integrated circuit device in which an input clamp diode is constructed using a tunnel wiring structure, and FIG. 3 is A-A of FIG. 2. 'Cross-sectional view,
FIG. 4 is an equivalent circuit diagram of the conventional example shown in FIGS. 2 to 4, and FIG. 5 is a plan view showing an embodiment of the present invention.
Figure 6 is a sectional view taken along line A-A' in Figure 5, and Figure 7 is a cross-sectional view of Figure 5.
8 is an equivalent circuit diagram of one embodiment of the structure of the present invention, FIG. 9 is a plan view showing another embodiment of the present invention, and FIG. 10 is A of FIG. 9. -A' sectional view, and FIG. 11 is a BB' sectional view in FIG. 201...Input terminal, 202, 203, 21
0,101...Diode, 204,206,2
08,211,103...Resistance, 205,20
7,209,212,102...Transistor, 2
14...Vcc terminal, 213...Output terminal, 1,
4, 5, 51, 52...P-type semiconductor, 2, 3,
6, 61, 62...N-type semiconductor, 7...Insulator,
91-96... Aluminum wiring, 100... Bonding pad.

Claims (1)

[Claims] 1 a first conductive type semiconductor substrate, a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate, and a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate;
A conductive type semiconductor layer is formed into a plurality of second conductive type first regions.
In a semiconductor integrated circuit device in which an input wiring layer is a second region of a first conductivity type separated by a PN junction and a third region of a high concentration second conductivity type provided in the first region of the second conductivity type, the first a fourth region of the first conductivity type formed in the first region of the second conductivity type semiconductor so as to at least partially overlap the second region of the semiconductor of the second conductivity type;
A semiconductor integrated circuit characterized in that the third region of the high concentration second conductivity type is provided in the fourth region of the conductivity type, and a ground electrode is provided in the second region or the fourth region of the first conductivity type.