JPS61273790A - Memory circuit - Google Patents

Abstract

PURPOSE:To obtain a memory circuit which has both FIFO and LIFO functions by instructing the 2nd RAM to be read when the 1st RAM is instructed to be written, and to be written when the 1st RAM is instructed to be read. CONSTITUTION:A count mode control part 6 inputs an FIFO/LIFO specifying signal 10 and outputs a count mode specifying signal 14 which specifies a count-up or count-down mode. The output of the counter 1 is use as a RAM address 16 to read or write the address of a RAM 3 or 4; and the RAMs 3 and 4 are controlled by a switching part 2 so that when one RAM is in write mode, the other is in write mode. Thus, PCM data 11 inputted to the RAMs 3 and 4 are written in the RAMs 3 and 4 temporarily, then readout again, and outputted as PCM data 20. Consequently, both FIFO and LIFO functions are provided and easily switched.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a memory circuit used in a microcomputer, etc., and in particular, the present invention relates to a memory circuit used in a microcomputer, etc. F I F O (First-InFirst-O
ut Memory ) and L I F O (La5t(
It relates to a type of buffer storage circuit that can also be a nFirst-Out Memory.

(Prior Art) Conventional memory circuits of this type include FIFO-only circuits and LIFO-only circuits, and these circuits have already been used in circuits around microcomputer computers. is often used when reading data from an external device. Also, LIFO
is used in the stack memory of microcomputers.

(Problem to be solved by the invention) However, since these circuits only have a single function, if you want to switch between the FIFO and LIFO functions in a time-sharing manner, it is necessary to have both memories and It is necessary to provide a circuit for this switching. Furthermore, FIFOs and LIFOs currently available on the market have a rather small capacity, so increasing the capacity requires a considerable amount of space, making it difficult to miniaturize the entire circuit.

Therefore, an object of the present invention is to provide a memory circuit having both FIFO and LIFO functions.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the storage circuit provided by the present invention has a count mode in which it receives a FIFO-LIFO designation signal and outputs a count mode designation signal in synchronization with a word clock. a control unit, a counter that counts bit clocks and outputs the counted value as a RAM address, a circuit that instructs this counter to load an initial value, and first and second circuits that write to or read from the RAM address. 2 RAM, and a RAM operation mode switching unit that instructs writing or reading to the first and second RAMs, and the count mode designation signal is
When the FO/LIFO designation signal specifies FIFO, the counter/knob mode is entered, and the FIFO-LIFO
When the specified signal specifies LIFO, the word clock
The counter alternates between a count-up mode and a count-down mode in synchronization with the count-up mode, and the load instruction circuit instructs to load the initial value when receiving the word clock while in the count-up mode, and the counter
When in the count-up mode, the count value is increased for each bit clock, and when in the count-down mode, the count value is decreased for each bit clock, and the RAM operation mode switching section writes data to the first RAM. The second RAM is instructed to read, and when the first RAM is instructed to read, the second RAM is instructed to write.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a counter, 2 is a RAM operation mode switching section, and 3 and 4 are R
AM, 5 is an AND circuit, and 6 is a count mode control section.

To operate this, the count mode control unit 6 inputs a 1-bit FIFO/LIFO that specifies the usage mode of this circuit.
It inputs a designation signal 10 for the counter 1 and outputs a count mode designation signal 14 that designates the count-up/countdown mode of the counter 1. In addition, a bit clock 12, a load (LOAD) pulse 15, and a counter initial value 9 are input to the counter 1. The counter 1 inputs the counter initial value 9 when the load pulse 15 is input. This load pulse 15 is generated by ANDing the count mode designation signal 14 and the word clock 13. The output of the counter 1 becomes the RAM address 16, which becomes the write and read address of the RAM 3 or 4. RAM3
and 4 are controlled by the switching unit 2 to which the word clock 13 is input so that when one is in the write mode, the other is in the read mode. Switching unit 2 is RAM
Control signals 17 and 18 are output to control RAMs 3 and 4, respectively, and set them in write mode or read mode. Due to these operations, RAM3
．． The PCM data 11 inputted to 4 is once written to these RAMs and then read out again to become PCM output data 2.
It will be output as 0.

The above operation will now be explained in more detail with reference to the timing diagram of FIG. FIG. 2 is an example of a timing diagram of the first embodiment, and this timing diagram includes (1) input signal section, (
The diagram is divided into 2) FIFO mode timing section and (3) LIFO mode timing section. The input signal section (1) includes PCM input data 11, a pit clock 12 and a word clock 13 synchronized therewith.

In the FIFO mode timing section (2), the FIFO-
The state is shown when LIFO specifier number 10 specifies FIFO, the mode of counter 1 is always set to up mode, and RAM address 16 is the same in write mode and read mode. I know that there is. On the other hand, in the LIFO mode timing section (3), a state is expressed when the FIFO-LIFO designation signal 10 designates LIFO, and the mode of the counter 1 is switched to the down mode after the up mode. Furthermore, the last RAM address in write mode is
In read mode, it will be the first RAM address, so
The PCM output data 20 is inverted word by word.

Due to the control operation of the counter 1 as described above, this embodiment has the feature that it can be used as either FIFO or LIFO.

(Effects of the Invention) As explained above, according to the present invention, FIFO and LI
It is possible to provide a memory circuit that has both the functions of FO and can easily switch between these functions. Moreover, since the RAM can be set to any location, a large capacity FIFO/L
An IFO storage circuit can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram showing the operation of the illustrated embodiment. 1...Counter, 2.-RAM operation mode switching section,
3.4...RAM, 5...AND circuit, 6...Count mode control unit. Representative Patent Attorney Shinsuke Honjo δr）

Claims (1)

[Claims] A count mode control section that receives FIFO/LIFO designation signals and outputs a count mode designation signal in synchronization with the word clock, and a count mode control section that counts bit clocks and outputs count values from RA.
a counter that outputs an M address; a circuit that instructs this counter to load an initial value; first and second RAM that writes to or reads from the RAM address; a RAM operation mode switching unit that instructs writing or reading, and the count mode designation signal is
- When the LIFO designation signal designates FIFO, the mode is set to count up, and when the FIFO/LIFO designation signal designates LIFO, the mode is alternately switched to count up mode and countdown mode in synchronization with the word clock, and the load The instruction circuit instructs to load the initial value when the instruction circuit is in the count-up mode and receives the word clock, and the counter increments the count value every bit clock when in the count-up mode, and When in countdown mode, the count value is subtracted every bit clock, and the RAM is
The operation mode switching unit instructs the second RAM to read when the first RAM is instructed to write, and instructs the second RAM to write when the first RAM is instructed to read. A memory circuit characterized by: