SU1339653A1 - Memory - Google Patents

Abstract

The invention relates to computing and can be used in image processing systems for solving the problem of distributing image elements across luminance ranges, as well as in various information and logic systems. The purpose of the invention is to increase the speed of the device. The memory device contains the first counter 1, the 2.address switch, the first memory block 3, the register 4 numbers, the second counter 5, the third counter 6, the second memory block 7, the shift register 8. The increase in the device performance is achieved due to the fact that the data processing results are stored in the memory block 3, and in the memory block 7, the original dacha data are stored. 1 ill., 1 tab. from € (L 00 00 with ot joint venture with

Description

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The invention relates to computing and can be used in image processing systems for solving the problem of distributing image elements across luminance ranges, as well as in various information and logic systems.

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of a storage device.

The device contains the first counter 1, the address switch 2, the first memory block 3, the register 4 numbers, the second counter 5, the third counter 6, the second memory block 7 and the shift register 8.

The operation of the device in the mode of counting numbers is based on a simple analytical dependent number and the cell number corresponding to a given range of values of the number. In block 7, a processing array of numbers is stored, the maximum of which can have the value, 25 where k l, 2j .., f p (block size 7). At the same time processing (counting of values) can be carried out on 2 ranges, where, 1,2,.,. 5 k. When

cell block 7 with the given address. The counted number, in turn, is fed to the input of register 8, at the output of which a code is generated that represents the value of the number shifted by k-t bits (the shift is made towards the lower bits). This code is the address of the cell of the corresponding range in block 3 and through the switch 2 arrives at its input. A reading is made in register 4 of the code representing the current value of the number of analyzed numbers falling within this range. The code from register 4 is fed to counter 5. where it is incremented by one, and the magnified code is written back to 70 but to block 3 at the same address, the contents of counter 6 are incremented, and the next number is processed from the original array stored Now in the block 7. This sequence of actions is repeated for each initial number, and thus the number of numbers of the initial array is counted by the ranges of their values, 30 The device can operate in the mode of ordinary memory (memory). For this, commentator 2 switches to the transfer mode to the first input of block 3 of information from the output of counter 1. The device

m k calculates the number of numbers equal to each of 2 -1

 values, t, e, the range is reduced to a single specific starting number, and the number of ranges to the number of all possible values of the array of numbers to be processed.

Before operation of the device, the parameter t, should be set. determining the number and length of the ranges, the array being processed must be in block 7, and block 3 must be

prepared for counting. For this, counters 1 and 5 are set to zero. The contents of counter 5 are recorded in the cell of block 3, whose address is determined by the contents of counter 1. Then the contents of counter 1 are incremented by one and the next entries are made in block 3. This sequence of actions is repeated for all addresses of block 3. Thus, the cells of block 3 are brought to zero values, after which the device is ready for processing an array of numbers, stored in the block 7,

The input of block 7 receives the value of the address from counter 6 and reads the number stored in

This is stored in block 7. This sequence of actions is repeated for each source number, and thus the number of numbers in the source array is counted by the ranges of their values. The device can also work in the mode of a conventional memory device. For this, commentator 2 switches to the transfer mode to the first input of block 3 of information from the output of counter 1. The device

one

consists of two separate memory devices, information from which is read into registers 8 and 4, respectively. In addition, the device can also operate in the memory mode with an indirect addressing table at the output. In this case, block 7 is the main memory of information storage, which, when read through the register

8 and the switch 2 is fed to the input of the block 3, which is supplied with auxiliary memory, which performs the functions of the stored indirect addressing table, and the address from which from block 3 to

register 4 reads the result. Thus, the device performs storage and tabular transformation of information.

Managing this device in

in the described order, it can implement both an automaton with rigid logic) and a universal computer according to a given program. The control signals come from an external control unit which

in-seven memory blocks. The result or output data can be read according to the processing algorithm from block 3 using the same external control unit.

The list of control signals arriving at the device blocks and the functions performed under their action are given in the table,

Claims (1)

Invention Formula A storage device containing the first counter, switch dre; 20 Ca, the first memory block, the device number register, which is, in order to increase the speed of the device, a third counter and a second memory block, the outputs of which are connected, are entered into it the inputs of the bits of the shift register, the address inputs of the second block are connected to the outputs of the bits of the third counter, the bits of which are the second address input of the device, the information input of the second memory block is the information input of the device, the records of the third counter and the second memory block are with Respectively, the sixth and seventh inputs of the device write permission, the read input of the second memory block is the second read enable input of the device, the setup input to O, and the counting input of the third counter are respectively the third installation and fourth control inputs of the device. The second counter and the shift register, the first and second information inputs of the address switch are connected respectively to the bits of the shift register and the first counter, the bits of which are the first address input of the device. - the output of the address switch is connected to the address input of the first memory block, whose information inputs are connected to the outputs of the second counter, the information outputs of the first memory block are connected to the information inputs of the number register, the outputs of which are connected to the input bits of the second counter and are - with the information output of the device, the recording inputs of the first and second counters of the shift register, the number register and the first memory block are respectively the first to the fifth inputs of the recording resolution of the device j thirty 35 Have Signal write address in the counter 6 Add one to the contents of counter 6 The signal to write data to the cell unit 7 Data reading signal from cell block 7 The signal write to the register 8 data from the output of block 7 Shifting the contents of register 8 towards the lower bits Signal write address in the counter h The signal for setting counter 1 to zero 653 ten 4 o The installation inputs to the first and second counters are the first and second installation inputs of the device, the read input of the first memory block is the first read enable input of the device, the control input of the address switch is the first control input of the device, the shift input of the shift register is The synchronization input of the device, the counting inputs of the first and second counters, are respectively the second and third control inputs. Add one to the contents of counter 1 Signal data recording in the cell unit 3 Data reading signal from cell block 3 The signal to write to the register 4 data from the output of block 3 The signal to write data to the counter 5 The signal for setting counter 5 to zero Add to the contents of the counter 5 The signal for setting counter 6 to zero Switch control signal 2 addresses Table continuation