JPS6126211A - Crystal growth of semiconductor - Google Patents

Crystal growth of semiconductor

Info

Publication number
JPS6126211A
JPS6126211A JP14601184A JP14601184A JPS6126211A JP S6126211 A JPS6126211 A JP S6126211A JP 14601184 A JP14601184 A JP 14601184A JP 14601184 A JP14601184 A JP 14601184A JP S6126211 A JPS6126211 A JP S6126211A
Authority
JP
Japan
Prior art keywords
layer
aln
film
single crystal
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14601184A
Other languages
Japanese (ja)
Inventor
Toshio Nonaka
野中　敏夫
Nagayasu Yamagishi
山岸　長保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP14601184A priority Critical patent/JPS6126211A/en
Publication of JPS6126211A publication Critical patent/JPS6126211A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Abstract

PURPOSE:To effect a thermally stable recrystallization and to facilitate removal of a protective film of a recrystallized layer by using AlN in a zone melting method. CONSTITUTION:The first layer IC2 having a high-melting point metal electrode in a semi-insulating GaAs substrate 1 and it is covered with an SiO2 film 3. Ge is vapor-deposited to about 1mum to form a polycrystalline layer 4a and a single crystal layer 4b. An AlN film 5 is deposited to about 5,000Angstrom by spattering and a substrate temperature is kept at 800 deg.C by using AlN as a protective film with a temperature of zone heater of about 1,700 deg.C and the polycrystalline layer 4a is recrystallized. Nextly AlN is removed selectively by phosphoric acid and a GaAs single crystal layer 6 is laminated on the single crystal Ge layer 4b by an MOCVD method to form the second layer IC7 in the layer 6. AlN has a thermal expansion coefficiency which is extremely approximate to that of Si and Ge and cracks and peeling are hardly occur. A melting point is higher than that of Si, GaAs, Ge, SiO2 and etc. and the formation and removal are easy. By this constitution, a stable recrystallization becomes possible.

Description

【発明の詳細な説明】 （産業上の利用分野） この発明は半導体結晶成長方法に関し、特に絶縁性層上
に形成された多結晶層あるいは非晶質層の単結晶化の方
法に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for growing semiconductor crystals, and particularly to a method for single crystallizing a polycrystalline layer or an amorphous layer formed on an insulating layer. .

（従来の技術） 従来このような技術分野は、絶縁性層上に半導体層を形
成するＳＯＩ技術（Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ　０ｎ
Ｉｎｓｕｌａｔｏｒ　Ｔｅｃｈｎｏｌｏｇｙ　）に属し
ておシ、積層化されたいわゆる３次元デバイスの実現に
は必須の技術分野である。この様なＳＯＩ技術において
は、絶縁性層上に形成した多結晶層あるいは非晶質層を
単結晶化するための工程、いわゆる再結晶化法が必要と
なる。再結晶化技術の一つとして、ストリップヒータを
用いて、絶縁性層上に形成された多結晶あるいは非晶質
半導体層を溶融させ再結晶化させる過程によシ単結晶層
とする帯溶融法がある。(Prior Art) Conventionally, this technical field has been based on SOI technology (Sem1conductor ON), which forms a semiconductor layer on an insulating layer.
It belongs to the field of Insulator Technology) and is an essential technical field for realizing so-called three-dimensional stacked devices. Such SOI technology requires a so-called recrystallization method, which is a process for single-crystallizing a polycrystalline layer or an amorphous layer formed on an insulating layer. One of the recrystallization techniques is the strip melting method, in which a polycrystalline or amorphous semiconductor layer formed on an insulating layer is melted and recrystallized into a single crystal layer using a strip heater. There is.

文献Ｊｏｕｒｎａｌ　ｏｆ　ｔｈｅ　Ｅｌｅｃｔｒｏｃ
ｈｅｍｉｃａｌ　５ｏｃｉｅｔｙさらに上層の保護膜と
して１．０μｍ〜２．０μｍのＣＶＤ法によｋ）　Ｓｉ
Ｏ□膜を形成した後に、前記多結晶Ｓ【の帯溶融法によ
る再結晶化を行うものである。LiteratureJournal of the Electroc
Chemical 5ociety Furthermore, as an upper layer protective film, a thickness of 1.0 μm to 2.0 μm is formed by CVD method.
After forming the O□ film, the polycrystalline S□ is recrystallized by a band melting method.

また、文献、Ｊａｐａｎｅｓｅ　Ｊｏｕｒｎａｌ　ｏｆ
　ＡｐｐｌｉｅｄＰｈｙｓｉｃｓ　Ｖｏｌ、　２２　、
４７　、　Ｊｕｌｙ　、　１９８３　ＰＰ、Ｌ４５０−
Ｌ４５１には、ゲルマニウム（以下Ｇｅという）の。Also, literature, Japanese Journal of
Applied Physics Vol. 22,
47, July, 1983 PP, L450-
L451 contains germanium (hereinafter referred to as Ge).

単結晶化技術として高融点金属のタングステン（以下Ｗ
という）による保護膜を形成し、帯溶融法によＹ）　Ｇ
ｅ層を単結晶化する方法が報告されている。Tungsten (hereinafter referred to as W), a high melting point metal, is used as a single crystallization technology.
Y) G by band melting method
A method of forming the e-layer into a single crystal has been reported.

（発明が解決しようとする問題点） 帯溶融法による再結晶化には、一般に保護膜としてＳｉ
Ｏ２膜が用いられているが、このＳ　１０２膜の熱膨張
係数は０．３５　Ｘ　１０−６／　ｄｅｇであシ、絶縁
性層上に形成するＳｔやＧｅの熱膨張係数はそれぞれ４
、２　Ｘ　１０＝　／　ｄｅｇおよび５．５　Ｘ　１０
−６／　ｄｅｇと１０倍の差があるため、Ｓ　ｉＯ２膜
を１．０μｍ以上の厚さに形成しなければ帯溶融法の熱
によ’）　５１０２膜のヒビ割れ、剥離等が生じ、単結
晶化が困難となる欠点があった。(Problem to be solved by the invention) In general, Si is used as a protective film for recrystallization by the zone melting method.
Although an O2 film is used, the thermal expansion coefficient of this S102 film is 0.35 x 10-6/deg, and the thermal expansion coefficients of St and Ge formed on the insulating layer are each 4.
, 2 x 10 = /deg and 5.5 x 10
Since there is a difference of 10 times from -6/deg, if the SiO2 film is not formed to a thickness of 1.0 μm or more, the heat of the zone melting process will cause the 5102 film to crack, peel, etc. There was a drawback that crystallization was difficult.

□　したがって、この発明は容易に形成でき且つ除去で
きる熱的に安定な保護膜を提供するものである１°（問
題点を解決するための手段） この発明は、絶縁性層上に形成した多結晶あるいは非晶
質半導体層を溶融させ再結晶化させる過程によ゛シ単結
晶層とする帯溶融法において、この多結晶あるいは非晶
質半導体層の保護膜として窒化アルミニウム（以下Ａｔ
Ｎという）膜を用いたものである。□ Accordingly, the present invention provides a thermally stable protective film that is easily formed and removed. In the band melting method in which a crystalline or amorphous semiconductor layer is melted and recrystallized to form a single crystal layer, aluminum nitride (hereinafter referred to as At) is used as a protective film for this polycrystalline or amorphous semiconductor layer.
It uses a membrane (referred to as N).

（作用） 本発明によれば、以上のように帯溶融法において再結晶
化層の保護膜としてｋｔＮを爪いているので熱的に安定
した再結晶化ができ、またとのＡｔＮ膜の形成および除
去が容易にできる利点がある。(Function) According to the present invention, since ktN is used as a protective film for the recrystallized layer in the band melting method as described above, thermally stable recrystallization can be performed, and the formation of AtN film and It has the advantage of being easy to remove.

（実施例） 第１図および第２図は本発明の実施例を一説明するため
の構造断面図であシ、以下図面に沿って説明する。(Embodiment) FIGS. 1 and 2 are structural cross-sectional views for explaining an embodiment of the present invention, and the explanation will be given below along with the drawings.

まず第１図に示すようにガリウムヒ素（以下ＧａＡｓと
いう）半絶縁性半導体基体１に高融点金−と：なシ、Ｇ
ａＡｓ基体１上のＧｅ層４ｂは単結晶となる。次にＧｅ
層４ａ、４ｂ上にＡｔＮ膜ｊｙ２スノｆツタ法によ＃）
５０００膜程度蒸着し、このＡｔＮ膜５を保護膜として
基体温度８００℃、図示しない帯ヒータ温度１７００℃
程度で帯溶融法によりＧｅ層４ａの再結晶化を行う。First, as shown in FIG.
The Ge layer 4b on the aAs substrate 1 becomes a single crystal. Next, Ge
An AtN film is formed on the layers 4a and 4b by the snow vine method.
Approximately 5,000 films were deposited, and with this AtN film 5 as a protective film, the temperature of the substrate was 800°C, and the temperature of the band heater (not shown) was 1700°C.
The Ge layer 4a is recrystallized by the zone melting method.

次にＡｔＮ膜５をリン酸によシ選択的に除去し、第２図
に示すように、単結晶化したＧｅ層４ｂ上に有機金属化
学気相成長（ＭＯＣＶＤ　）法によｐ　ＧａＡｓ単結晶
層６を積層する。次にこのＧａＡｓ単結晶層６に集積回
路７を形成する。Next, the AtN film 5 is selectively removed using phosphoric acid, and as shown in FIG. Layer 6. Next, an integrated circuit 7 is formed on this GaAs single crystal layer 6.

尚、この実施例では半導体基体としてＧａＡｓ　’ｉｔ
：用いたが、その代シにＳｉｉ用いてもよく、また単結
晶化を行う非晶質層または多結晶層としてＧｅの代シに
多結晶シリコンを用いてもよい。In this example, GaAs'it is used as the semiconductor substrate.
:Although Si may be used instead of Ge, polycrystalline silicon may be used instead of Ge as an amorphous layer or polycrystalline layer for single crystallization.

（発明の効果） 第１表は本発明の詳細な説明するための各種材料の物理
定数である。(Effects of the Invention) Table 1 shows physical constants of various materials for detailed explanation of the present invention.

再結晶化の一方法としての帯溶融法においては、保護膜
、の融点が高い、こと、熱伝導率が大きいこと、本発明
による保護膜（ＡｔＮ膜）は、第１表に示すように、熱
膨張係数が５．’　５４　Ｘ　１０−６／ｄｅｇ　、！
：’ｖｓう値をもちＳｉ　、　Ｇｅなどに非常に近く、
ヒビ割れハクリ等が発生しない利点がある。In the band melting method as one method of recrystallization, the protective film (AtN film) according to the present invention has a high melting point and high thermal conductivity, as shown in Table 1. The coefficient of thermal expansion is 5. '54 X 10-6/deg,!
:'vs value, very close to Si, Ge, etc.
It has the advantage that cracks, peeling, etc. do not occur.

さらに第１表に示すように、熱伝導率はＳｘ０２−ｍシ
約１．３倍大きい値をもち、また、融点は３３００℃で
＠　ｌ）　Ｓｉ　、　ＧａＡｓ　、　Ｇｅ　、　５ｉＯ
２１等の材料よシ高い値をもっているため保護膜として
非常に安定である。Furthermore, as shown in Table 1, the thermal conductivity is approximately 1.3 times larger than that of Sx02-m, and the melting point is 3300°C @l) Si, GaAs, Ge, 5iO
Since it has a higher value than materials such as No. 21, it is very stable as a protective film.

また、このＡｔＮ膜はスパッタ法などによシ容易に蒸着
形成が可能であり、その選択的除去もリン酸によシ可能
であることなどの利点がある。Further, this AtN film has the advantage that it can be easily deposited by sputtering or the like, and that it can be selectively removed by phosphoric acid.

第１図および第２図は本発明の詳細な説明するための構
造断面図である。1 and 2 are structural sectional views for explaining the present invention in detail.

１・・・ＧａＡｓ基体、２・・・第１層集積回路、３・
・・ＳｉＯ２膜、４ａ・・・多結晶Ｇｅ層、４ｂ・・・
単結晶Ｇｅ層、５・・・ＡｔＮ保護膜、６・・・ＧａＡ
ｓ単結晶層、７・・・第２層集積回路。DESCRIPTION OF SYMBOLS 1... GaAs substrate, 2... 1st layer integrated circuit, 3...
...SiO2 film, 4a...polycrystalline Ge layer, 4b...
Single crystal Ge layer, 5...AtN protective film, 6...GaA
s single crystal layer, 7... second layer integrated circuit.

特許出願人　工業技術院長用田裕部 第１図 ２茎１看ｔ＃に回路 第２図Patent applicant Hirobe Yoda, Director of the Agency of Industrial Science and Technology Figure 1 2 stalks 1 # circuit Figure 2

Claims (1)

【特許請求の範囲】[Claims] 　絶縁性基体上に積層された非晶質層または多結晶層の
単結晶化を行う帯溶融方法を用いた半導体トライド（窒
化アルミニウム）を積層して帯溶融を行うことを特徴と
する半導体結晶成長方法。Semiconductor crystal growth characterized by laminating semiconductor toride (aluminum nitride) and performing band melting using a band melting method for single crystallizing an amorphous layer or a polycrystalline layer stacked on an insulating substrate. Method.
JP14601184A 1984-07-16 1984-07-16 Crystal growth of semiconductor Pending JPS6126211A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14601184A JPS6126211A (en) 1984-07-16 1984-07-16 Crystal growth of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14601184A JPS6126211A (en) 1984-07-16 1984-07-16 Crystal growth of semiconductor

Publications (1)

Publication Number Publication Date
JPS6126211A true JPS6126211A (en) 1986-02-05

Family

ID=15398071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14601184A Pending JPS6126211A (en) 1984-07-16 1984-07-16 Crystal growth of semiconductor

Country Status (1)

Country Link
JP (1) JPS6126211A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258254A (en) * 1988-08-23 1990-02-27 Nobuo Mikoshiba Semiconductor element
US5011550A (en) * 1987-05-13 1991-04-30 Sharp Kabushiki Kaisha Laminated structure of compound semiconductors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247673A (en) * 1975-10-15 1977-04-15 Hitachi Ltd Process for production of silicon crystal film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5247673A (en) * 1975-10-15 1977-04-15 Hitachi Ltd Process for production of silicon crystal film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5011550A (en) * 1987-05-13 1991-04-30 Sharp Kabushiki Kaisha Laminated structure of compound semiconductors
JPH0258254A (en) * 1988-08-23 1990-02-27 Nobuo Mikoshiba Semiconductor element

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