JPS6219046B2 - - Google Patents
Info
- Publication number
- JPS6219046B2 JPS6219046B2 JP56086670A JP8667081A JPS6219046B2 JP S6219046 B2 JPS6219046 B2 JP S6219046B2 JP 56086670 A JP56086670 A JP 56086670A JP 8667081 A JP8667081 A JP 8667081A JP S6219046 B2 JPS6219046 B2 JP S6219046B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- layer
- insulating film
- silicon
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 2
- 238000010894 electron beam technology Methods 0.000 claims 1
- 238000000407 epitaxy Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 27
- 239000013078 crystal Substances 0.000 description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 241000201976 Polycarpon Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Description
【発明の詳細な説明】
この発明は絶縁膜上に単結晶シリコン層を形成
する半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a single crystal silicon layer is formed on an insulating film.
通常、集積回路を製造するにあたつてはその中
に含まれる構成素子、例えばトランジスタ、ダイ
オード、抵抗などを何らかの手段で電気的に絶縁
分離する必要がある。そして、一般的に、シリコ
ン半導体素子製造に供されるシリコンエピタキシ
ヤル成長技術にはサフアイアなどの絶縁基板上に
適用する場合およびシリコン単結晶基板に適用す
る場合の２つの方法がある。前者の方法は予め絶
縁基板上にシリコン単結晶層を形成するため、単
に、このシリコン単結晶層を島状に物理的に切り
離し、その後、分離した島内に公知の技術で、各
素子を形成するものであるが、サフアイア基板が
高価であるうえ、機械的強度の脆さから破損し易
いため、製造歩留りが低下する。一方、後者の方
法は基板が比較的低廉であり、しかも機械的にも
強靭であるが、構成素子を絶縁分離するには繁雑
な製造方法例えば接合分離などを用いなければな
らない。そこで、従来、前記の２つの方法の長所
だけを取り入れ、高性能、低価格な集積回路の製
造を可能にする一手段として、シリコン基板に被
着した絶縁膜上にシリコン単結晶を形成すること
が提案されている。しかし、シリコン基板上に被
着可能な絶縁膜、例えばシリコン酸化膜、あるい
はシリコン窒化膜などは非晶質であり、単に公知
のエピタキシヤル成長技術を駆使しても、絶縁膜
上には全くシリコン層が形成されない。また、た
とえエピタキシヤル成長条件（例えば成長温度、
成長速度）を変化させたとしても、巨大な粒径の
シリコン単結晶粒がピラミツト状に点在付着する
だけで、実用に供するような均一な単結晶層とは
ならない。そこで、最近、レーザアニール法が注
目されている。このレーザアニール法はまず、絶
縁膜上に、比較的低温（例えば600℃前後）で多
結晶シリコン層を形成し、この多結晶シリコン面
にレーザビームを走査しながら、あるいは断続的
に照射することにより、単結晶を得ようとするも
のである。 Normally, when manufacturing an integrated circuit, it is necessary to electrically isolate the constituent elements contained therein, such as transistors, diodes, resistors, etc., by some means. In general, there are two methods for silicon epitaxial growth techniques used in the manufacture of silicon semiconductor devices: one method applied to an insulating substrate such as sapphire, and the other method applied to a silicon single crystal substrate. In the former method, a silicon single crystal layer is formed on an insulating substrate in advance, so this silicon single crystal layer is simply physically separated into islands, and then each element is formed in the separated islands using a known technique. However, since the sapphire substrate is expensive and is easily damaged due to its weak mechanical strength, the manufacturing yield is reduced. On the other hand, in the latter method, the substrate is relatively inexpensive and mechanically strong, but requires the use of complicated manufacturing methods such as bonding and separation in order to insulate and separate the constituent elements. Therefore, as a means of incorporating only the advantages of the above two methods and making it possible to manufacture high-performance, low-cost integrated circuits, a conventional method has been to form silicon single crystals on an insulating film deposited on a silicon substrate. is proposed. However, insulating films that can be deposited on silicon substrates, such as silicon oxide films or silicon nitride films, are amorphous, and even if known epitaxial growth techniques are used, no silicon will be deposited on the insulating film. No layer is formed. Also, even if the epitaxial growth conditions (e.g. growth temperature,
Even if the growth rate (growth rate) is changed, silicon single crystal grains of huge grain size will only be scattered and deposited in a pyramid shape, and a uniform single crystal layer that is suitable for practical use will not be obtained. Therefore, the laser annealing method has recently been attracting attention. This laser annealing method first forms a polycrystalline silicon layer on an insulating film at a relatively low temperature (for example, around 600°C), and then scans or intermittently irradiates the polycrystalline silicon surface with a laser beam. The aim is to obtain a single crystal.
しかしレーザアニールを用いても、絶縁膜上の
多結晶層では結晶成長の核となる種結晶が多す
ぎ、大きな粒径の単結晶領域を得ることは困難で
あつた。この困難さを解決するために“bridged
epi”と称する第１図ａに示すようなシリコン単
結晶領域１１からのはい上がりのエピタキシヤル
成長法が提案されているが、これも単結晶領域１
１を溶融させるようなレーザー１４のパワーでは
第１図ｂに示すように絶縁基板１３上の多結晶層
１２が蒸発してしまうことが多く、マージンの非
常に少ない製造方法と言わざるを得ない。 However, even when laser annealing is used, there are too many seed crystals that serve as nuclei for crystal growth in the polycrystalline layer on the insulating film, making it difficult to obtain single crystal regions with large grain sizes. To solve this difficulty, “bridged”
An epitaxial growth method has been proposed in which the silicon single crystal region 11 as shown in FIG.
With the power of the laser 14 that melts the polycrystalline layer 12, the polycrystalline layer 12 on the insulating substrate 13 often evaporates as shown in FIG. .
そこで本発明はこのような従来の方法の欠点を
除去し、大きく均一な単結晶シリコン層を絶縁膜
上に安定に形成しようとするものであり、その特
徴とするところは、シリコン基板の一主面の一部
に絶縁膜を被着し、上記絶縁膜上に多結晶シリコ
ン層を形成し、多結晶シリコン層及びシリコン露
出部上にシリコンエピタキシヤル成長層を形成
し、然る後シリコンエピタキシヤル成長層をアニ
ールして単結晶シリコン層を得るものである。 Therefore, the present invention aims to eliminate the drawbacks of such conventional methods and stably form a large, uniform single crystal silicon layer on an insulating film. An insulating film is deposited on a part of the surface, a polycrystalline silicon layer is formed on the insulating film, a silicon epitaxial growth layer is formed on the polycrystalline silicon layer and the exposed silicon, and then a silicon epitaxial growth layer is formed. A single crystal silicon layer is obtained by annealing the grown layer.
以下、実施例について詳細に説明する。 Examples will be described in detail below.
まず、シリコン基板２２上の一部をシリコン窒
化膜等の酸素を通さないち密な薄膜でおおい、こ
れを熱酸化すると、この膜におおわれていないシ
リコン基板２２の表面が酸化され、酸化膜２３が
生成される。これをふつ酸の希釈液で適当にエツ
チングした後、シリコン窒化膜を除去すると第２
図ａのようにシリコン基板２２の露出部と酸化膜
２３の表面がほぼ同一平面となるように酸化膜２
３がシリコン基板２２に埋設して形成される。次
に比較的低温、例えば600℃前後で公知の化学的
気相成長法で多結晶シリコン層を成長させこれに
写真製版を行つて、第２図ｂのごとく、酸化膜２
３上の多結晶シリコン層２１のみ残す。この多結
晶シリコン層２１は後記する第２の多結晶シリコ
ン層形成時の下敷となる。さらに、これを既知の
シリコン気相エピタキシヤル成長技術を使い、水
素ふいん気中で高温、例えば950℃−1200℃に加
熱した反応器中に配置し、シリコンソース材料と
して例えばモノシラン（SiH4）、ジクロルシラン
（SiH2Cl2）などを導入すれば、第２図ｃに示すよ
うに前記多結晶シリコン層２１上には非常に大き
な粒径の単結晶を含む多結晶シリコン層が成長
し、基板シリコン２２上にはこれと同一方向の結
晶軸をもつた単結晶シリコン層が成長して第２の
シリコン層２４となる。これを連続発振のレーザ
ーで走査しながら照射し、このとき酸化膜２３上
の第１多結晶層２１、第２多結晶層２４の両方が
完全に溶融するレーザパワーに設定すれば、第(2)
図ｄに示すようにシリコン基板２２上に成長した
単結晶が核となり、第１、第２の多結晶層２１，
２４が単結晶化されて均一な単結晶層２５とな
る。 First, a part of the silicon substrate 22 is covered with a dense thin film that does not allow oxygen to pass through, such as a silicon nitride film, and this is thermally oxidized.The surface of the silicon substrate 22 that is not covered with this film is oxidized, and the oxide film 23 is formed. generated. After appropriately etching this with a dilute solution of hydrochloric acid and removing the silicon nitride film, the second
As shown in Figure a, the oxide film 23 is placed so that the exposed portion of the silicon substrate 22 and the surface of the oxide film 23 are approximately on the same plane.
3 is embedded in the silicon substrate 22. Next, a polycrystalline silicon layer is grown by a known chemical vapor deposition method at a relatively low temperature, for example, around 600°C, and photolithography is performed on this to form an oxide film 2, as shown in FIG. 2b.
Only the polycrystalline silicon layer 21 on top of the polycrystalline silicon layer 21 is left. This polycrystalline silicon layer 21 becomes an underlay when forming a second polycrystalline silicon layer to be described later. Furthermore, using known silicon vapor phase epitaxial growth techniques, this is placed in a reactor heated to a high temperature, e.g. 950°C to 1200°C, in a hydrogen atmosphere, and monosilane (SiH 4 ), for example, is used as the silicon source material. , dichlorosilane (SiH 2 Cl 2 ), etc., a polycrystalline silicon layer containing very large grain size single crystals grows on the polycrystalline silicon layer 21 as shown in FIG. A single crystal silicon layer having a crystal axis in the same direction as the single crystal silicon layer grows on the silicon 22 to become a second silicon layer 24. If this is irradiated with a continuous wave laser while scanning, and the laser power is set to completely melt both the first polycrystalline layer 21 and the second polycrystalline layer 24 on the oxide film 23, the (2 )
As shown in FIG.
24 is single crystallized to form a uniform single crystal layer 25.
以上の実施例では、熱酸化法により絶縁膜を形
成する場合について説明したが、この方法に限定
せず、例えば化学的気相成長法、あるいはプラズ
マ成長法により堆積したシリコン酸化膜またはシ
リコン窒化膜でもよく、その膜質および製造方法
は何れでもよいことはもちろんである。また、膜
厚については必要な絶縁耐圧を確保すればよく、
絶対値を問わないことはもちろんである。 In the above embodiments, the case where the insulating film is formed by a thermal oxidation method has been described, but the method is not limited to this method. For example, a silicon oxide film or a silicon nitride film deposited by a chemical vapor deposition method or a plasma growth method Of course, any film quality and manufacturing method may be used. In addition, as for the film thickness, it is sufficient to ensure the necessary dielectric strength voltage.
Of course, the absolute value does not matter.
以上、詳細に説明したように、この発明に係る
半導体装置の製造方法によればシリコン基板に被
着した絶縁膜上に大きな均一な単結晶シリコン層
を安定に形成することができ、高性能で、低価格
な集積回路を製造することができるなどの効果が
ある。 As explained above in detail, according to the method for manufacturing a semiconductor device according to the present invention, a large uniform single crystal silicon layer can be stably formed on an insulating film deposited on a silicon substrate, and it can achieve high performance. , it is possible to manufacture low-cost integrated circuits.
第１図は従来の絶縁膜上での単結晶成長方法を
示す断面図、第２図は本発明の製造方法の一実施
例を示す断面図である。
図中、２１は第１の多結晶シリコン層、２２は
シリコン基板、２３は絶縁膜、２４は第２の多結
晶シリコン層、２５は単結晶シリコン層を示す。
FIG. 1 is a sectional view showing a conventional method for growing a single crystal on an insulating film, and FIG. 2 is a sectional view showing an embodiment of the manufacturing method of the present invention. In the figure, 21 is a first polycrystalline silicon layer, 22 is a silicon substrate, 23 is an insulating film, 24 is a second polycrystalline silicon layer, and 25 is a single crystal silicon layer.
Claims (1)
し上記一主面の他の部分にシリコン露出部を形成
する工程、比較的低温で上記絶縁膜上のみにエピ
タキシヤル成長時の下敷になる第１の多結晶シリ
コン層を形成する工程、比較的高温で化学的気相
成長法によるエピタキシヤル成長により上記第１
の多結晶シリコン層上に第２の多結晶シリコン層
を、上記露出部上に単結晶シリコン層を形成する
工程、上記第２の多結晶シリコン層及び上記単結
晶シリコン層上にレーザまたは電子線等のエネル
ギー線を照射して上記第２の多結晶シリコン層を
単結晶化する工程を含む半導体装置の製造方法。 ２ 絶縁膜がシリコン酸化膜であることを特徴と
する特許請求の範囲第１項記載の半導体装置の製
造方法。 ３ 絶縁膜がシリコン窒化膜であることを特徴と
する特許請求の範囲第１項記載の半導体装置の製
造方法。 ４ 絶縁膜をシリコン基板に埋設したことを特徴
とする特許請求の範囲第１〜３項の何れかに記載
の半導体装置の製造方法。[Claims] 1. A step of forming an insulating film on a part of one main surface of a silicon substrate and forming an exposed silicon part on another part of the one main surface, epitaxy only on the insulating film at a relatively low temperature. Step of forming a first polycrystalline silicon layer that will serve as an underlay during layer growth, by epitaxial growth using chemical vapor deposition at a relatively high temperature
forming a second polycrystalline silicon layer on the polycrystalline silicon layer and a single-crystalline silicon layer on the exposed portion; forming a laser or electron beam on the second polycrystalline silicon layer and the single-crystalline silicon layer; A method for manufacturing a semiconductor device, comprising the step of monocrystallizing the second polycrystalline silicon layer by irradiating the second polycrystalline silicon layer with energy rays such as 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon nitride film. 4. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that an insulating film is embedded in a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56086670A JPS57201015A (en) | 1981-06-04 | 1981-06-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56086670A JPS57201015A (en) | 1981-06-04 | 1981-06-04 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57201015A JPS57201015A (en) | 1982-12-09 |
| JPS6219046B2 true JPS6219046B2 (en) | 1987-04-25 |
Family
ID=13893462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56086670A Granted JPS57201015A (en) | 1981-06-04 | 1981-06-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57201015A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01115935U (en) * | 1988-01-30 | 1989-08-04 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151820A (en) * | 1984-08-20 | 1986-03-14 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-06-04 JP JP56086670A patent/JPS57201015A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01115935U (en) * | 1988-01-30 | 1989-08-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57201015A (en) | 1982-12-09 |
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