JPS61255172A - Clamp circuit for video signal display device - Google Patents

Abstract

PURPOSE:To accurately clamp even when having no signal and to obtain a wide horizontal position adjustable range by extracting a signal of a level subjected to a peak value clamping of an output of a horizontally synchronizing separator circuit during a horizontal flyback-line pulse period and obtaining a clamp pulse in accordance with a rear edge timing thereof. CONSTITUTION:In a peak value clamp circuit 6, an output of a horizontally synchronizing signal separator circuit 2 is clamped by the peak value of a polarity of a horizontally synchronous signal at the time when having a signal or having no signal. The signal is extracted during a horizontal flyback pulse period by transistors Q3, Q2 and a clamp pulse (f) is obtained by a differentiation circuit 7 and a transistor Q4 in accordance with a rear edge timing thereof. Thereby, even when a relative phase of a horizontally synchronous signal B and a horizontal flyback pulse C is shifted a pulse width of a clamp pulse F is not changed and a position of the clamp pulse F is not changed with respect to the original horizontally synchronous signals A3, A4 and a horizontal position adjustable range becomes a difference between a pulse width t2 of the horizontal flyback pulse and a horizontally synchronous period t3 (t2-t3), which is wider than the conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clamp circuit for a video signal display device, and more particularly to a circuit for clamping a video signal in order to maintain a constant pedestal level of the video signal.
- Conventional technology In order to accurately express the gradation from black to white in display devices for video signals, the pedestal level or black level is used as a reference so that the black level itself does not change even if the video content changes. It transmits □ DC signal. One of the methods of transmitting DC components is a DC regeneration circuit using a clamp. DC regeneration is performed by clamping the pedestal level at a constant level.

As a clamp in this case, it is common to use a clamp pulse that is formed based on the horizontal synchronization signal so that it can always clamp a fixed point. For example, a clamp pulse that is formed based on the horizontal synchronization signal is used. There are also methods that use a waveform obtained by subtracting the horizontal synchronization signal from the integrated waveform of the horizontal synchronization signal.

This method can only obtain a clamp pulse when a horizontal sync signal is present, so in the absence of a signal, the clamp circuit turns into an oven, resulting in a completely black image, and the brightness control must be adjusted. However, the display on the image (for example, channel display, video selection display) becomes invisible, or the image becomes completely white, giving the appearance of a malfunction.

Therefore, there are conventional clamp circuits that do not cause the above disadvantages.
Figure 3 shows the circuit diagram. Under normal conditions, terminal 1
The incoming composite video signal a ((A+) in FIG. 4) is separated from the horizontal synchronizing signal b ((B+) in FIG. 4) by the synchronization separation circuit 2 and is supplied to the transistor Qs. On the other hand, the horizontal retrace pulse C (
(C+)) is supplied to the transistor Q6 to switch it, and a clamp pulse d ((D+) in the figure) is taken out from the collector (output terminal 4) of the transistor Qs.

Meanwhile, no signal! In It ((A2) in the same figure), the horizontal retrace pulse itself is extracted as the clamp pulse d ((02) in the same figure), and the above-mentioned disadvantage can be eliminated. .

Problems to be Solved by the Invention However, in recent video signal display devices, V
It often receives signals other than broadcast signals from broadcast stations such as TR, video disc, personal computer, etc.
This may cause a shift in the horizontal scanning frequency or a difference in blanking period, and it is necessary to adjust the horizontal position of the image. In this case, the horizontal position adjustment is generally performed by controlling the relative phase between the horizontal synchronizing signal and the horizontal retrace pulse.

By the way, when the above horizontal position adjustment is performed, Fig. 4 (D3)
(When the horizontal retrace pulse is delayed with respect to the horizontal synchronization signal)
As shown in FIG. 3 and (D4) (when the horizontal retrace pulse advances relative to the horizontal synchronizing signal), the width and position of the clamp pulse change. Therefore, there is a problem that the brightness changes if there is a noise component etc. on the front porch or the back porch between the end of the video signal and the start of the horizontal synchronization signal. There is a problem in that the DC regeneration rate changes when the clamp pulse width changes even if there is no noise component or the like.

In addition, in order to avoid clamping the image part, for example, as shown in FIG. If the width is t2 (if the horizontal synchronization period is 5 μs and the minimum value of the clamp pulse is 2Ils, then the minimum value of pulse width t2 is 5+2=7us), then the period (t+-t2)
-41js is the horizontal position adjustable range, but there are variations in the horizontal retrace period and horizontal synchronization period, and the horizontal position adjustable range depends on this variation, so the range may become narrow, which is a problem. (Note that the horizontal retrace pulse cannot be made narrower than this, so the horizontal position adjustable range cannot be expanded any further).

The present invention provides a video signal display that can reliably clamp even when there is no signal, and that the position and pulse width of the clamp pulse relative to the video signal do not change even when the horizontal position is adjusted, and that allows a wide range of horizontal position adjustment. The purpose is to provide a clamp circuit for the device.

Means for solving the problem In FIG. 1, the peak value clamp circuit 6 is replaced by the horizontal synchronization separation circuit 2.
Means for clamping the output of the signal to the peak value of the polarity of the horizontal synchronization signal both when there is a signal and when there is no signal, a transistor Qs
e Q 21 Differential circuit 7. The transistor Q4 is an embodiment of a means for extracting a peak-clamped level signal from the output of the horizontal synchronization separation circuit 2 during the period of the horizontal retrace pulse C, and obtaining a clamp pulse in accordance with the timing of its trailing edge.

The peak value clamp circuit 6 clamps the output of the horizontal synchronization separation circuit 2 at the peak value of the polarity of the horizontal synchronization signal both when there is a signal and when there is no signal. A signal at a peak value clamped level during the output is extracted during the horizontal retrace pulse period, and the differential circuit 7. A clamp pulse is obtained by the transistor Q4 according to the timing of the trailing edge.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention. In the figure, the same parts as those in FIG. 3 are given the same numbers and their explanations will be omitted. In a normal state, the horizontal synchronization signal taken out from the synchronization separation circuit 2 is processed by the delay circuit 5 for, for example, 200 ns.
The peak value is clamped to a certain value by the peak value clamp circuit 6. The signal whose peak value is clamped is delayed from the emitter of transistor Q1 as a horizontal synchronizing signal b.
' ((B+) in FIG. 2) and is supplied to the transistor Q3 to switch it.

On the other hand, the horizontal retrace pulse C (('C+) in the figure) is supplied to the transistor Q2, and the signal d' ((D+) in the figure) corresponding to the timing of the delayed horizontal synchronizing signal b' is transmitted from its emitter during the horizontal retrace period. ) is retrieved. The signal d' is differentiated by a differentiating circuit 6 into a signal e ((E+) in the figure), and a clamp pulse ((F+) in the figure) is taken out from the collector (output terminal 4) of the transistor Q4.

On the other hand, in the no-signal state ((A2) in the same figure), since the peak value clamp circuit 6 is provided, the signal b' ((82) in the same figure) is at the peak value level (L level), and the transistor Q2 horizontal retrace pulse C (same figure (C
2)) The same signal d' ((C2) in the same figure) is taken out and converted into a signal e ((F2) in the same figure) in the differentiating circuit 6, and the signal f ((F2) in the same figure) is output from the output terminal 4. taken out.

On the other hand, if the horizontal retrace pulse is delayed with respect to the horizontal synchronization signal due to horizontal position adjustment ((C3) in the same figure), the timing of the clamp pulse f taken out from output terminal 4 will be as shown in the same figure (F3). On the other hand, when the horizontal retrace pulse advances with respect to the square synchronization signal ((C, 4') in the same figure)
, the timing of the clamp pulse □f is as shown in the same figure (F4). In other words, no matter what relative phase deviates between the horizontal synchronization signal and the horizontal retrace pulse, the pulse width of the clamp pulse does not change, and the position of the clamp pulse remains the same as the original horizontal synchronization signal ((A3), (Aa) in the same figure). It remains the same as the normal state. Thereby, stable DC regeneration can be performed at all times. .

In addition, the horizontal position adjustable range is the pulse width t2 (approximately 11.5 IJs) of the horizontal retrace pulse, the horizontal synchronization period, and t3 (5 IJs).
Difference from Jjs> (iz -1-3) = approximately 6.5Ii! i
Therefore, it can be wider than the conventional circuit shown in FIG. In this case, by integrating the waveform of the horizontal retrace pulse and widening the pulse width, the range in which the horizontal position 1111 can be adjusted can be widened by that much, and there is a degree of freedom compared to the conventional circuit.

Note that when obtaining the clamp pulse from the signal d', the clamp pulse may be obtained by subtracting the signal d' from a waveform obtained by integrating the signal d'.

Furthermore, the method for obtaining the clamp pulse f is not limited to the method according to the above embodiment, but may be obtained by, for example, obtaining the clamp pulse from a signal obtained by differentiating the delayed horizontal synchronizing signal b' and a horizontal retrace pulse. You can also do this. According to this method, the clamp pulse is the same as the horizontal retrace pulse in the no-signal state, but in the no-signal state, unlike the signal state, it is stricter and there is often no need to set the ramp level. No problem.

Effects of the Invention According to the circuit of the present invention, it is possible to reliably clamp even when there is no signal, the position and pulse width of the clamp pulse with respect to the video signal do not change even when the horizontal position is adjusted, and; It has many features such as wide adjustable range of horizontal position.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams and signal waveform diagrams of an embodiment of the circuit of the present invention, respectively, and FIGS. 3 and 4 are circuit diagrams and signal waveform diagrams of an example of a conventional circuit, respectively. DESCRIPTION OF SYMBOLS 1...Composite video signal input terminal, 2...Sync separation circuit, 3...Horizontal retrace pulse input terminal, 4...Output terminal, 5...Delay circuit, 6...Peak value Clamp circuit, 7
...Differential circuit, 01-Q4...Transistor.

Claims (2)

[Claims] (1) In a clamp circuit of a video signal display device that clamps a video signal by obtaining a clamp pulse from a horizontal retrace pulse and an output of a horizontal synchronization separation circuit, the output of the horizontal synchronization separation circuit is used both when a signal is present and when there is no signal. A circuit that clamps at the peak value of the polarity of the horizontal synchronization signal, and a signal whose level is clamped at the peak value during the output of the horizontal synchronization separation circuit is sampled during the horizontal retrace pulse period, and the signal is clamped according to the timing of its trailing edge. A clamp circuit for a video signal display device, comprising a circuit for obtaining pulses. (2) In a clamp circuit of a video signal display device that clamps a video signal by obtaining a clamp pulse from the horizontal retrace pulse and the output of the horizontal synchronization separation circuit, the output of the horizontal synchronization separation circuit is used both when a signal is present and when there is no signal. A circuit for clamping at the peak value of the polarity of the horizontal synchronization signal, a circuit for differentiating the output of the horizontal synchronization separation circuit, and a signal corresponding to the timing of the trailing edge of the horizontal synchronization signal from the output of the differentiation circuit. A clamp circuit for a video signal display device, comprising a circuit that extracts the horizontal retrace pulse period to obtain the clamp pulse.