JPS61254984A - Processor for bit mat display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a processing device for a frame buffer of a two-star scan display, and more particularly to a processing device for a bitmap display that performs line-by-scan line display and copying functions. Regarding.

[Conventional technology and problems]

A frame buffer is used to store the digital representation of an image for one display on a two-star scan display. Divide this frame buffer into one or more planes.

Does each plane contain multiple planes? , each word representing a plurality of pixels, f, a 16-bit (pixel) frame buffer word P, 640 pixels x
In a 480-line display, each display consists of 40 words per line, or a total of 1 (L200 words).

It consists of a plurality of horizontal display cycles for a scan line, with a plurality of horizontal blanking cycles during one display horizontal blanking period after each horizontal scan line. Each cycle consists of a refresh part and an update part, in which the word is read from the frame buffer, and in the update part, the word is written to the frame buffer.
Data in this frame buffer can be modified.

To move a portion or block of an image from one position on the display to another, an operation called a bit block transfer (BITBLT) is performed. However, when you try to scroll an image using BitBlit, you may experience tearing, flickering, or inch-warming in one image.
Distortion occurred.

It is therefore an object of the present invention to eliminate such distortions.

To provide a processing device for a pit map display device capable of smoothly scrolling images.

[Means and effects for solving the problems] Pit pine according to the present invention! - The raster scan display processing unit performs the function of managing the frame buffer on a per scan line basis.

The portion of the frame buffer memory that is not used for display stores raw P/decode parameters. The row processor drives these meters during horizontal blanking and utilizes these t42 meters for display and data movement operations during primary scan line refresh.

The nogturn memory provides pixel mask values for scrolling along with the cursor-pattern.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention. The frame buffer αI comprises a frame buffer memory (FBM') U having one or more planes (A, B, C, D). For illustration, frame buffer memory (6) a640X48064
With 0x480 pixel α◆.

It has a row processing unit area (RPU) αQ of 112×512 pixels in the A plane. The remaining area of the 1024 x 512 pixel frame buffer memory (6) is available for other purposes.

FIG. 2 shows the structure of one frame buffer, with each frame buffer word being 16 bits or 2 bytes long. Cathode ray tube (CRT) controller)
Refresh display during cycle period.

To select one row address to generate row and column addresses for the frame buffer memory (2).

CRT controller (to) and frame buffer memory (to
6) Frame buffer address circuit (FBA)
) (1) is placed. Color Map Circuit Co., Ltd.
The CRT controller receives pixel display data from the display bit mag α which is accessed upstream and outputs a video signal containing color information to one display.

Row processing device c! which is an execution means! It receives the data stored in the one-line processing area α, codes the data, and executes various functions. Tsuyaturn memory (RAM)
) stores the cursor pattern and scroll mask value. As the CRT controller alpha frame clocks through the columns, the one row processor (c) selects the cursor gloss turn or scroll mask value from the 79 turn memory (c) depending on the row. The column address from the CRT controller α is also input to the row processing device (c).

As well as a display processing unit or central processing unit i1 (CPU).

The row processing unit (c) accesses the frame buffer address circuit (b). The row processing unit 124 also has access to the color map circuit @ to control the change of the arm dot color and the cursor color. The frame buffer state machine acts as a signal traffic controller and generates timing signals for the frame buffer. Pattern memo IJ H selected by line processing device
A cursor signal from the color map circuit (2) is inputted to a color map circuit (2) for output as video data to one display.

Details of the row processing device (c) and pattern memory (g) are shown in FIGS. 3 to 5. For purposes of explanation, the circuit will be described with reference to the frame buffer processor P of FIGS. 2a-2f, which creates the RPU domain αQ as shown in FIG. 2g. The A7' lane data (APD) from the frame buffer memory (6) is input to the data latch 2 between each column clock pulse (CCLK), ie.

clock only once between each frame buffer word
Go out. The output of data latch (1) is.

Form a row processing data (RPD) path.

Decoder 0 inputs bit 0 of each RPD word as input.
(right end in Fig. 2), l and 15 (left end), column count value (CC) from CRT controller α and top pit of needle firing value (CR9), row block transfer enable (R() from display processor). 7* BLTEN) signal as well as the row processing straw! (RPS) signal from the state machine.
TB) Receive a signal. Bit 15 of each row processing word (words 40-46 for each scan line) is the load bit (LD
). Decoder 0■ is inhibited until the column count value reaches 40, that is, until the column count value is outside the display bit map area α◆. When CR9 is set and corresponds to rows 512 and above that are outside the range of frame buffer memory (6), the decoder is inhibited.

When the column and stroke values (CC and CR9) indicate that the frame buffer word is within the row processing area (to),
Check whether bit 15 of each word is set. If bit 15 is set, the command for the row function to be executed on the primary scan line is output.

Next, FIGS. 2a to 2f will be referred to in sequence. In word 40, if bit 15 (leftmost) and bit 0 (rightmost) and/or bit 1 are set, the interrupt signal (I
NTQ and/or INT 1 ) is output from decoder 0■. One line processing word using INT O/1 (c)
Synchronize with the CPU. Bit 1 in word (b)
When set to 5, cursor load (CUR8
ORLD) signal is output. If bit 15 is set in words 42 and 43, zJ? (PALD) signal, each word references one of the bit planes. Bit 15 in word 44 is set.

(pi) is set to 0, and the display processing device
When the OWBLTEN signal is input, a one row block transfer request (ROW BLTRQ) signal is output. When bit 15 is set in word 45, the one row block transfer mask load (RBMASKLD) signal is output. Finally, one line counter load (RCNTLD
If bit 15 of word 46 is set, word 46 provides a row processing counter enable (RPCNTEN) signal as well as the ``) signal.

If the load bit is set in one of the row processing words, the meter carrying that word is immediately executed or loaded into a register.

The executed functions were 1 interrupt/9 pulses INT O, INT
It may be for a single scan line, such as I?1, and remains the same until a new value is loaded or a feature such as cursor and scrolling is disabled. may be executed in consecutive scan lines using the n h0 fourth
As shown in the figure, the decoder (to) selects the cursor word (9
), the CUR8ORLD signal goes into the cursor register (b) and bits 0 to 4 of the ?J? clock parameter value. The value in the cursor register (b) is the row address (PROff) for the arm turn RAM (1).
It is i. For each successive scan line, during the refresh scan time, when the video enable (VIDEN) signal enables the output of the cursor register (b).

The shift register low y (5RLD) signal from the frame buffer controller (FBC) (to) and the cursor enable (CU) signal from the cursor register (ro)
R8EN) signal and transfers the pattern in that row to the cursor shift register (to).Next, the dot clock pulse (DCLK'') is sent to the cursor shift register (to) for display via the color map circuit. clock out the cursor to the video display circuit.

For the scroll/fill operation, the RBMASKLD signal from the decoder (a)
Clock the turn value and plane mask value into the mask register. This plane mask value is.

Enable signal (APE) from mask register (to)
N.

BPEN, CPEN, DPEN) are also supplied to each plane, and when the row pack transfer write (ROWBLTWR) signal from the frame buffer controller (TO) enables the output of the mask register (TO), the mask pattern is Supply the address to the pattern RAM (2). R.P.
The CNTEN signal causes the row destination counter (7
) and loads the register with the address destination for the following scan line's data by the RCNTLD signal.

During the update cycle, the ROWBLTWR signal also outputs the frame packer row address (FR) to write that scanline's data to PR for the pixel in each column specified by the mask pattern. During scroll/fill operations when synchronized by RPCNTKN, the RPSTB signal generated on every word access increments the row destination counter (6).

Figures 6 and 7 show the operation of the frame buffer.
Between frame buffer word reads, the CPU reads each frame buffer word, including the cursor from the 7V memory buffer (AM).
) can be accessed. For scroll/fill operations, the video data read from the 7-frame buffer memory (6) is latched and held until the update cycle. During the update cycle.

Rewriting the video data to the storage location in the frame buffer memory (7) specified by the one-row destination counter (6) for the pixel indicated by the mask parable.

During the horizontal retrace period, that is, during the blanking period, the CRT
The controller maintains increments through the 7 frame buffer memory. Reads and decodes the word from RPU area αQ and loads the nine count meter it contains into the appropriate register for execution during the next scan line. do. Again as a normal representation, during the update portion of the f'7 linking cycle, the CPU has 7 frame buffers.
Access memory (a). Upon completion of the horizontal retrace, the 1 column count is reset to zero and the CRT controller increments the row address to display the next scan line.

〔Effect of the invention〕

As described above, the bit map display processor of the present invention utilizes the unused portion of the frame buffer memory for each scan line to store instructions and parameters to be executed on subsequent scan lines. and removes image distortion during scroll/fill operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred embodiment of the invention. ! Figures 2 to 2g are diagrams showing the row processing device area in the frame buffer memory, Figure 3 is a block diagram of a decoder for the row processing device, and Figure 4 is a diagram showing the pattern area for the row processing device.
Memory block diagram, Figure 5 shows the row destination counter for the row processing unit! FIG. 42 and FIG. 6 are diagrams showing the operation of the line processing device, and FIG. 7 is a state diagram of the operation of the line processing device. In the figure, (2) is a frame-buffer memory. 2) is an execution means, and 2) is a pattern memory. FB Daiminr FIG, 2a 41LDX X X X X X XENX
X X X X X X X
X ENFIG, 2d FIG, 2e FIG, 2f t-IG, 6

Claims (1)

[Claims] A parameter consisting of a specific function and its parameter value.
A frame where words are stored in a non-display area for each scan line.
a buffer memory, a pattern memory storing a plurality of patterns, decoding the specific function, accessing the pattern according to the parameter value, and scanning the specific function according to the parameter value and the pattern; A processing device for a bit map display, comprising execution means for line by line execution.