JPH06102842A - Graphic display system including video random access memory having divided serial register and operation counter - Google Patents

Abstract

PURPOSE: To provide a graphic display and processing system provided with a video random access memory provided with a division serial register, an access start point address register and a constitution body for stopping an access operation at the end of an operation length. CONSTITUTION: This graphic system is provided with the video random access memory 105 provided with the division serial register 109 provided with the plural storage elements of a low-order half and a high-order half, the access start point address register 137 and the constitution bodies 140, 142 and 145 for stopping the access operation at the end of a desired operation length. Both start and stop point addresses are specified for a read data access operation and the operation speed of the processing system is accelerated by using them. The random access memory 105 is also provided with a multiplexer 160 for connecting the column of memory cells to the storage elements of the division serial register 109.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a graphic display and processing system for generating a graphic display, and more particularly to a system using a semiconductor memory in the form of a random access memory having a split serial register configuration. Pertain to.

[0002]

2. Description of the Related Art In a typical random access memory, the time required to access a row is approximately twice the time required to access a column. In order to get an overall speedy operation, it is desirable to access a row and hold the row while also accessing a number of columns along it. This is referred to as "page mode" operation. If all columns along the array are accessed while accessing one row, a time savings of 50-70% is achieved.
Such time savings are obtained during memory write operations or memory read operations. For certain system designs, memory write times and memory read times can be traded off to achieve efficient operation.

In computer graphics system applications, there is a further trade-off between memory read and write times and the capability and speed of the microprocessor used to generate the data to be sent to the video screen. Other factors to consider include the width and height of the display, the size of the video random access memory, and whether the system is line oriented or tile oriented. The final choice among many trade-offs remains with the system designer or user.

Suppliers of equipment used in such applications prefer that designers and users manufacture equipment that includes a large number of optional features, so that each type of equipment can be fitted into a number of different applications. . This allows a large-scale manufacturing operation with a single device design effort, and reduces the cost per device.

To facilitate the above design strategies, integrated circuit manufacturers have improved the design of video random access memory integrated circuit devices by adding features that increase the flexibility and speed of operation of these devices. . Some additional features of the random access memory design include the addition of a split serial register to improve accessibility to and from the memory array, and a selectable read from this split serial register. That is the addition of a tap. These features allow users to closely pack data into the video random access memory, thus avoiding wasting memory space.

As described above, there are two operation modes, one for line and one for tile. In line-oriented operation, the graphics processor generates and stores data in sequential order, which is visible line by line on the display. Storing the data in the video random access memory and reading it out to the display is done bit by bit and line by line in serial order. Reading from the split serial register to the display is timed to correlate with the sweep signal of the display. The known video random access memory device design has the highly desirable feature of being widely used in line-oriented systems.

[0007]

Known video random access memory device designs are considerably less flexible and useful for tile oriented systems. Typically, tile-oriented displays have a grid of equal size and shape,
It is divided into tiles. The size and shape of the tiles are factors that should be selected, inter alia, by the system designer or user. For example, tiles are square or rectangular. In the case of a rectangle, the orientation is determined by laying the longer dimension sideways or standing vertically. For certain tile sizes and orientations, currently available video random access memory devices are not flexible enough to be used efficiently in some possible system applications. More specifically, the data representing a single tile must be stored in various rows of storage cells of a random access memory array.

Prior to the advent of split serial registers, graphic processing systems transferred an entire row of data bits from a dynamic random access memory to a long data register for reading. From this data register, all the data bits of one row have been read in a serial sequence. It is now known that this operation has severely limited its speed in some graphics processing systems. The output of the data register is a serial bit stream read out under the control of the serial clock. During the long read operation, new data could not be transferred from the dynamic random access memory to the data register.
This is because new data destroys this existing data before it is possible to read the existing data in the data register.

With the advent of split serial registers used in graphics processing systems, it has become possible to define the upper half and lower half of the split serial register.
This is done by referencing the most significant bit in each half of the counter used to address the split serial register. Thus, while accessing data from one half of the split serial register, it can be reloaded from the random access memory to the other half. Also, while loading one half of the split serial register, the address within the half of the split serial register at which to begin serial access is loaded into the start point address register. The start point address of the data access operation can be defined by the information loaded in the start point register, but the data read access operation ends at the midpoint of the divided serial register when reading from the lower half,
When reading from the upper half, it ends at each end of the split serial register. This manner of operation for split serial registers poses significant problems or constraints in the design of certain graphics processing systems.

For example, when the divided serial register stores 512 bits, the end point of the access operation in the lower half of the divided serial register is bit 25.
5, and the endpoint of the access operation in the upper half of the split serial register becomes bit 511. Since the access operations typically available in graphics processing systems often vary from 8 bits to 128 bits, the access operation is either bit 255 or bit 511.
In order to force the end, the operation speed of the graphic processing system is unnecessarily reduced.

[0011]

These and other problems
Provided is a video random access memory having a split serial register having a plurality of storage elements in a lower half and an upper half, an access start point address register, and a structure for stopping an access operation at the end of a desired operation length. Solved by a graphic display and processing system.

For the divided serial registers of the graphics processing system, the start and stop points of the data access operation, that is, the specific operation length, are defined by the method and apparatus. The access start point address in the split register is loaded into the access start point address register. The motion length is loaded into the motion length counter. Combine this information,
Start and stop point addresses for each access operation of the divided serial register are determined.

The graphics processing system has the operational advantage of being able to start and stop read access operations at selected storage elements of the split serial register. Graphic displays and processing systems operate at high speeds.

The graphic display and processing system has a random access memory configured with a novel split register and multiplexer to transfer data from this memory array to the split register. The data stored in either the lower half or the upper half of the column address of the memory array is selectively transferred to either the lower half or the upper half of the division register address via the multiplexer.

The advantage of this arrangement is that system designers have greater flexibility or selectivity in determining where in the memory array to store a particular bit of information to display, particularly in tile-oriented operation. Is especially useful for tile-oriented operation. The data tiles are
Storage elements can be mapped along a single row of a random access memory array. Thereafter, the data from the storage elements of the random access memory is transferred to the split register and sent to the raster scan display in a line-by-line sequence.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a data processing system 100 including a graphic display structure for providing information.
Are shown in block diagram form. A more detailed description of the construction and operation of the system of FIG. 1 can be found in US patent application Ser. No. 821,641 filed January 23, 1986, which is hereby incorporated by reference.

The data processing system 100 includes a host processing system 102 and a graphics processor 10 such as the Texas Instruments TMS34010 or TMS34020 graphics system processor.
3, a video random access memory 105, a data register 107, a video palette 108, a digital / video converter 110, and a video display 11
2 and.

The host processing system 102 performs the main calculation function of the data processing system 100. Included in the host processing system 102 is a processor and
An input device, a long-term storage device, a read-only memory, a random access memory, and associated peripheral devices for forming a computer system. The configuration and operation of this host processing system is conventional. Depending on its processing capabilities, the host processing system 102
Determines the information content of the graphical display to be displayed on the screen for the user.

The graphics processor 103 serves as the main part of the data manipulation to generate the particular graphic display to be displayed on the screen. The graphic processor 103 is bidirectionally connected to the host processing system 102 by the host bus 101. In the configuration of FIG. 1, the graphic processor 103 operates independently of the host processing system 102. However, the graphics processor 103 is not compatible with the host processing system 102.
Respond to requests from. Also, the graphic processor 1
03 communicates with the memory 105 and the video palette 108 by the memory bus 104. The data stored in the video random access memory 105 is controlled by the graphic processor 103. The graphics processor then uses the video random access memory 10
5 or partially or wholly controlled by a program stored in the read-only memory 114. The read only memory 114 stores graphic image data of various formats.

Further, the graphic processor 103 is
Controls the data stored in the video palette 108,
The operation of the digital / video converter 110 is controlled via the video control bus 116. The digital / video converter allows the graphic processor 103 to control the line length and the number of lines per frame of the video graphic image. Importantly, the graphics processor 103 determines and controls where in the video random access memory 105 the graphic display information is stored. Thereafter, while reading from the video random access memory 105, the graphics processor may generate a desired graphic image on the display 112, the read sequence from the video random access memory and the split serial register 107, the address to be accessed, and the display 112. Determine the required control information.

The video random access memory 105 is
Store bitmap graphic data that defines the graphic image to be presented to the user. The graphic processor 103 controls to transfer data from the video random access memory 105 to the display 112 via the data register 107, the video palette 108 and the digital / video converter 110. The video data output from the video random access memory 105 is transferred by the video output bus 118 to the data register 107, where it is assembled into a display bit stream. The data register 107 is a shift register.

The storage elements of the data register 107 are composed of dynamic or static electronic circuits.
Alternatives to storage elements include bistable electronic devices,
These include magnetic devices, optical devices, and optoelectronic devices with sufficient operating speed.

A typical configuration of video random access memory 105 provides a bank of multiple individual random access memory integrated circuits. The storage cells of the video random access memory 105 are manufactured as dynamic or static electronic circuits. In the case of a single read access operation, only 1 bit of data is read from the storage element selected for each of the integrated circuits. Thus, a group of bits is read at a time, including one bit from each of a number of individual integrated circuits.
The data register 107 assembles the display bitstream for delivery by the leads 120 to the video palette 108. In the above description, the video random access memory 10
Although 5 is described as an electronic circuit, the invention can also be implemented with a memory manufactured as a bistable electronic device, a magnetic device, an optical device or an optoelectronic device with sufficient speed.

Under the control of information from the graphic processor 103, the Texas Instruments T
A video palette 108, such as the MS34070 video palette, translates the data received from the data register 107 into video level signals on the bus 125. This conversion is done via a look-up table. The video level signal output from the video palette 108 is
It contains color, saturation and luminance information.

The digital / video converter 110 receives the digital video signal from the video palette 108 and, under the control of the signal received by the video control bus 116, converts the digital video signal to an analog level, which are output lines. It is sent to the video display 112 via 127. The number of pixels per horizontal line and the number of lines per display are determined by the graphics processor 103. Also, the sync, blanking and blanking signals are controlled by the graphics processor 103. This entire group of signals specifies the desired video output to video display 112.

The video display 112 produces a designated video image for viewing by the user. Two techniques are widely known. The first technique is for each pixel to have a color,
Specify video data in terms of hue, brightness and saturation.
In the second technique, red, blue and green color levels are specified for each pixel. Video palette 108, digital / video converter 110, and video display are designed and manufactured to fit the selected technology.

FIG. 2 shows a block diagram of the layout of the video random access memory 105 of the integrated circuit. Included within memory 105 are four arrays of memory cells 105-1, 105-2, 105-3 and 105-4. These cells are arranged in a matrix configuration. For random access, the matrix address is sent to the integrated circuit by the address read and address buses. Also, in the case of random access, the matrix address is decoded by the matrix decoder. Data is written from the data bus through the column decoder and the sensitivity amplifier to the selected cell of the memory array. For serial read, data is read from the selected row of the memory array through the transfer gate into the data register. The serial address counter sends a series of serial data register addresses to the serial data pointer or decoder. In response to these addresses, a series of data is sent from the serial data register via the data bus to the serial output buffer. From there, the data is shown in Figure 1.
To the register 107, video palette, digital / video signal converter, and video display, as shown in FIG.

To complete the random access structure, various random access input and output circuits are quadrupled.

In the case of serial output operation, a group of common circuits controls the read operation very efficiently. This group of circuits includes an initial tape register, a motion count register, a motion counter, a comparator and a serial address counter, which provides a series of addresses associated with each serial data register via a separate address bus. To the serial data pointer. The operation of these common circuits for serial reading will be described below.

FIG. 3 shows the graphic processor 10.
3, video random access memory 105-1, split register 109-1, certain control circuits, and interconnection buses and leads are shown in a detailed block diagram. The video random access memory 105 includes four memory arrays 105-1, 105-2, 10 having storage cells arranged in a matrix.
5 is an exemplary memory including 5-3 and 105-4. Typically, four memory arrays are included on one semiconductor chip. The information representing one pixel of the display contains a number of data bits. For each pixel, one bit is stored in each array, eg B0. All of these bits for a pixel are stored at the same row address and the same column address, so they can be written to and read from the entire memory in one access operation. In a particular design, there are usually as many memory arrays as there are bits in a pixel. More arrays or more chips may be provided per chip if more than 5 bits per pixel are required.

Although four video random access memory arrays 105-1, 105-2, 105-3 and 105-4 are shown connected together in FIG. 3, they are shown and illustrated without affecting versatility. To simplify the explanation,
Only one of them, the array 105-1 will be described below. Illustrating and describing this one memory array 105-1 and its associated multiplexer 130-1, division register 109-1 and control circuit is to describe other memory arrays connected to each other from one or more semiconductor chips and It can also be applied to related circuits.

The screen of the video display 112 of FIG. 1 may be constructed in one of two ways. Usually, in a display, there are a large number of horizontal lines, each of which contains a large number of pixels. Another often used but different mechanism is to divide the display into multiple tiles. Each tile contains a number of pixels in an adjacent area of the display. Since the tile area of the display is uniform in size, it contains a certain number of pixels laterally and a certain number of pixels vertically. In the following description, the number of pixels across a tile is equal to the number of columns in the partition of video random access memory array 105-1 and the number of storage elements in the partition of split register 109-1. The division register 109-1 is a shift register or a serial register. Hereinafter, the division register will be described as the division serial register 109-1. Consider the information within a line across a tile as a segment of the tile. Since the memory array 105-1 has only one bit per pixel, the number of bits in the tile segment of the array 105-1 is used for the number of columns used to partition the memory array and the partition of the split serial register 109-1. Equal to the number of storage elements The number of pixels in the height direction is equal to the number of lines in the tile. In the example below, in the display shown in FIG. 12, the tile is 32 pixels wide and 8 pixels high. This will be described below.

Video Random Access Memory Array 10
5-1 is configured such that data representing tiles of the display are stored in a single row of memory array 105-1 as sequential segments of tiles. All data tiles are
It is stored in a single row of memory array 105-1. Row and column address information and desired display or pixel information is generated by the graphics processor 103.

For random access writes, an address is sent via bus 104 to address register 106 to access the identified matrix storage location in random access memory array 105-1. The display data to be stored at each address is the bus 104 and the lead 111.
To the random access memory array 105-1. When the graphics processor generates a random access address and display data for any tile, this data is sent over bus 104 to random access memory 105-, unlike in the prior art.
Written to 1. This is done by accessing a single row and then a sequentially selected column to write data to. This is a random access write operation that allows writing data for almost all tiles during a single row access. A row access operation takes almost twice as long as a column access, so doing a single row access and then multiple column accesses while the row access is in effect saves considerable operating time. It

Each of memory array 105-1 and divided serial register 109-1 is divided into a lower portion and an upper portion by an address. By this division, the memory array 105-1 to the video display 112 of FIG.
Read-out is considerably facilitated. Memory array 10
Reading from 5-1 is performed sequentially by the lines of the display. When scanning a line of display with a raster, the appropriate data for each pixel is sequentially added to the beam to be projected onto the display screen. The graphics processor 103 determines the order in which the storage cells of the memory array 105-1 are addressed, the selection made by the multiplexer 130-1, and the order for reading data from the storage elements of the split serial register 109-1. To obtain the desired output sequence of information sent to the video display 112.

Rows of memory are addressed by sub-rows, eg, lower address half row and upper address half row.
Under the control of the graphic processor 103, the multiplexer 130-1 sends the data read from either the lower half or the upper half of the memory array to the address of the lower half of the divided serial register 109-1 by bit lines. Be sent or sent to the upper half address. Once the data is stored in the split serial register 109-1, one or more bits of the tile's data or segment are split serial register 1
09-1 to the video display 112.

Another control circuit common to a large number of memory arrays is provided, and the divided serial register 109-
1 to determine the particular part of the data to be sent. The data from split serial register 109-1 can be read from individual taps in each storage element. Conceptually, these taps are gate circuits 132
And is adapted to receive a separate output from each storage element of the split serial register 109-1. The counter decoder 135 receives the time slot determined by the read clock signal CLOCK during the time slot.
Determine which one of the split serial register storage element outputs is to be sent to the video display 112.

Since the first pixel data to be transmitted can be anywhere in the split serial register 109-1, the graphics processor 103 loads the address of the first pixel data into the initial tap or start point register 137. To do. Upon receiving the reset signal from the comparator 145, the initial tap register 137
Is the first pixel data address for the counter decoder 1
35 to allow the gate circuit 132 to send data from the correct storage element of the split serial register. The initial pixel data address load operation may be parallel to the counter decoder 135.

The data that is subsequently read is generally
It is sequentially sent along the storage elements of the divided serial register 109-1, but unlike the known technique, it is not necessarily sent continuously. In some cases, it has been found effective to read the data from only one half of the split serial register 109-1. In such a state, the display system is oriented to the tile, and the data representing the tile is stored in the memory array 1 as described above.
Occurs when stored along a single row of 05-1. Therefore, in terms of efficiency, the divided serial register 109
The sequential address operation for reading data from -1
It must be interrupted before the end of half of the register. Unlike in the known art, these interrupts are generated by the graphic processor 103 in the operation count register 140.
To the counter decoder 135 and gate circuit 132 before the interrupt
Is determined by determining the serial address number of the split serial register 109-1 that is accessed before jumping to a new initial or start tap address for the next read. The convenient working length is equal to the number of pixels contained in the segment. Count register 1
The numerical value of 40 and the motion count from the motion counter 142 are compared by the comparator 145. If they do not match, the current sequence of addresses is continued while incrementing the operation counter by the signal CLOCK for each read operation. When the two counts coincide, for example, at the end of a segment, the signal for resetting the motion counter 142 and loading the new initial tap address into the initial tap register 137 is provided by the comparator 14.
Generated by 5. As a result, the counter decoder 1
In the reference numeral 35, the gate circuit 132 is the divided serial register 10
It is possible to jump to a new initial tap address of 9-1 so that the sequential address operation can be interrupted.

A tile-oriented system reads all the pixels in one segment of a tile from one half of the split serial register 109-1 and transfers them to the other half of the split serial register to transfer the pixels of the segment from another tile. It is effective to operate through a series of addresses equal to the number of addresses needed to read Since tiles typically end before the end of the register half, it is beneficial to interrupt the read operation at the end of the tile rather than at the end of the register half. For a detailed description of this operation, see FIGS.
With reference to 2 below.

FIG. 4 shows the physical structure of the storage cells and bit lines of the memory array 105-1 and the storage elements of the divided serial register 109-1 associated therewith. Both the memory array 105-1 and the divided serial register 109-1 have, depending on the address, the lower half L of the memory array address including the half of the memory cell.
And the upper half H of the memory array address including the remaining memory cells. Lower half name L
0. ． ． L127 is the designation H0. ． ． H127
And the two halves seem to stand out from each other in FIG.

Unlike the known memory array, the memory cell L of the lower half address of the memory array 105-1 is interleaved with the memory cell H of the upper half address of the memory array. Similarly, unlike the known random access memory system structure, the storage element L of the lower half address of the divided serial register 109-1 is
Are interleaved with the storage element H of the upper half address of the divided serial register 109-1.

In this way, by interleaving the storage cells of the two parts of the memory column and the storage elements of the two parts of the divided serial register 109-1, the memory array 105-1 and the divided serial register 109 are interleaved.
Significant advantages are obtained when -1 is manufactured as an integrated circuit. Also, by interleaving, the memory array 10
The total length and complexity of the bit lines configured to connect the storage cells of 5-1 to the storage elements of the split serial register 109-1 via the multiplexer 130-1 is dependent on the memory array 105-1 and the split serial register 109-. The upper and lower halves of 1 are substantially reduced for the bitline layout required when divided by the entire physical partition rather than the interleaving of column and register elements as shown in FIG.

FIG. 4 is a schematic diagram for section 130-1.1 of multiplexer 130-1, which shows a split serial register 109 from one cell at either half of the address of memory array 105-1. It can be used to transfer data to storage elements at either half of the -1 address. Multiplexer 1
The illustrated section 130-1.1 of 30-1 divides one column address in the upper half or one column address in the lower half of memory array 105-1 into a serial register 109.
-1 to the associated upper or lower half storage element. The complete multiplexer 130-1 has such a multiplexer section 130-for each bit line pair.
Use one of 1.1.

FIG. 5 shows the multiplexer 1 shown in FIG.
A truth table is shown that illustrates the logical operation of section 130-1.1 of 30-1. One out-of-four (one out of four) codes received from the graphics processor via path 160 in FIG. 3 are the control terminals H-H, L-L, L-H and H-L of the switching device shown as an example. Sent to. In response to this one out of four code, one of multiplexer sections 130-1.1
Two gates are enabled. The other three gates remain disabled. The input control signals are lower half-lower half L-L, lower half-upper half L-H, upper half-lower half H-L and upper half-upper half H-H.
Is indicated. The input is sent from the upper half H or the lower half L of the memory array, and the output is sent to the upper half H or the lower half L of the split serial register.

Note that the operation of the multiplexer represented by the truth table of FIG. 5 is independent of the interleaving of the storage elements of the memory array or split serial register, as shown in FIG. The operation of the multiplexer described herein is used to connect the column address of the other structure of the split memory array to the address of the split serial register.

Graphic processor 10 of FIGS. 1 and 3.
3 generates all the information of the graphic display. Each data bit can occur at any time and in any order. Processor 103 knows when, which bit is generated and where that bit is predesignated or mapped for storage in random access memory 105. When writing bits to the random access memory 105 at random,
The order in which the bits are written is not important except for efficiency, but each bit must be stored in a storage element at its own pre-specified or bitmapped location in the random access memory.

For efficient and speedy random writing of data to the memory array, it is useful to access to write by tile rather than individual pixels. All changed information for one or more tiles is quickly generated and written. All stored information for other unchanged tiles need only be refreshed and not rewritten. Since it is only necessary to write to the tile when the information changes in this way, all the writing can be performed very efficiently.

FIG. 6 shows Cartesian coordinates representing storage locations within the random access memory array 105-1 shown in FIGS. 3 and 4. Note that the lower and upper halves of the array are split in the middle rather than interleaving the columns. This array is
It is shown divided in the middle for the purpose of illustrating the concept by means of a simple figure. However, in practice it may be preferable to interleave the memory storage elements and the column leads by address, as shown in FIG. The interleaved configuration can handle the upper half and lower half transfer operations based on the random access memory array 105-1 shown in FIG. 6 and the following description.

The grid of FIG. 6 is an 8 × 8 square array, where each square represents information provided as ⅛ of the tile to be displayed on the graphic display. In FIG. 6 and subsequent FIGS. 7-12, squares represent segments of data. Each segment is numbered and the reader can follow the numbered segment as described below from the memory array storage location through the multiplexer and the split serial register to the display. The numbers in the square identify the information as segments of tiles. Each data segment is stored in a row section of memory. The data represented by each one of the numbered squares or segments is 32-bit data (i.e., 3 bits) stored as shown in memory array 105-1.
2 columns x 1 row). The tile of the displayed image is a single row of random access memory array 105-1, namely row 1
Is represented by all the bits stored in the memory cell along. As noted above, for the display of Figure 12, the tiles are 32 bits wide x 8 bits high,
As described below with respect to FIG. 12, the display is oriented in vertical columns.

Recall that data can be written to the storage cells of random access memory array 105-1 in sequential order, but each bit must be stored in its predesignated location. To increase the overall operating speed of the display system, the graphics processor forms the information of the display image by the tiles and stores that information in the memory array. In FIG. 6, all the data contained in each row of the memory array is equivalent to a complete tile. Graphic processor 103
Generates all the data that forms a single tile, so it accesses only one selected row at a time in memory array 105-1. One column at a time is accessed while the selected row is accessed,
This is done until all new data associated with a tile is stored in the accessed row of random access memory. Significant system operating efficiency is obtained because the graphics processor 103 writes or stores all the data contained in a tile while accessing only one row of the memory array. Accessing each row is typically twice as long as accessing each column. For efficient operation, it is the worst case when only one column is accessed each time each row is accessed. With the configuration of the present invention, when writing to the random access memory at random, the operation time can be reduced by about 70% with respect to this worst case.

After the complete display screen of data has been stored in the random access memory 105 of FIG. 1, the system begins reading the data from the random access memory and splits the serial register 109-.
1, data register 107 and video display 11
2 can be transferred. The data is stored in memory by segment, as shown in FIG. Video displays use known raster scanning techniques to display graphical information on a display screen or cathode ray tube. Meanwhile, the graphic processor 103
The random access memory 105 is scanned to transfer the data to the display. Data from the memory array is transferred through a multiplexer, a split serial register, a data register 107 and a color palette, when the raster beam sweeps across one horizontal line after another projection of graphic information at a predetermined location on the screen. Is aligned with this raster beam. The sequential order of reading data from the memory array is fixed by the hardware and firmware of the graphic display system. The first data on the display is segment 1
, Then segment 2, and so on, and finally segment 64. The data from one half line of the address of the data register 107 is displayed on the display 112.
Data from another half row of addresses while being read from
-1 can be transferred to half of the idle state. The information sent from the split serial register is less (often less) than the full half register for each half register of data transferred from the memory.

Data from the divided serial register is shown in FIG.
Data register 107 to send to the video palette. The data register 107 is the array 105-1, 10
5-2, 105-3 and 105-4 respectively to output leads 118-1, 118-2, 118-3 and 11 of FIG.
It is configured to receive serial data streams in parallel via 8-4. During operation, the data register 107 takes in multiple parallel streams of input data and shifts them out in one interleaved sequence. All bits for each pixel are grouped together in the output data stream. Therefore, all the data that describes each pixel is sent to the video palette at once.

The Video Palette transforms the pixel data into the form desired for feeding into the Digital / Video Converter. From the digital / video converter, the video signal is fed to the display. At the end of each line of the screen, the raster typically retraces or returns one line or more down to the beginning of the screen. During this retrace, the graphic information is erased from the beam. When the blanking is complete, the raster begins a sweep across another line of the screen, projecting graphic display information. Since the raster beam sweeps and retraces across the entire screen, the data read from the memory array is sent to the beam modulator of video display 112 in the proper sequential order for each complete sweep across the screen. I have to.

The operation of reading data from memory and transferring it through the multiplexer, serial shift register, and gate to the data register will be understood by a careful reading of the following discussion of FIGS.

FIG. 7 is a table showing the operation of sequentially reading the stored data shown in FIG. 7 from the random access memories of FIGS. 3 and 4. In FIG. 7, the leftmost column shows a time slot for reading a data segment from the memory array 105-1. The columns designated as the lower half of the registers indicate which bit groups or tile portions from the memory array are split serial in FIG. 4 in preparation for transferring the selected segment to the video display 112 during the odd numbered time slots of the read operation. It indicates whether the data is read to the lower half of the register 107-1. Similarly, the column labeled the upper half of the register divides the serial register 10 from the memory array in preparation for transferring another selected segment to the display during even numbered time slots.
7-1 shows a group of bits read to the upper address of 7-1. The column labeled Multiplexer 130 is used to transfer data to the split serial register 107-1 before sending it to the video display.
-1 represents control signal information for operating -1. In the columns labeled RAM and Register, the letters indicate the lower half L or the upper half H of the memory array 105-1 and the split serial register 107-1, respectively, and accordingly, FIG.
3 shows a multiplexer control signal configuration used in the.

During read time slot 0, data from the lower half L of the first row of memory array 105-1 is passed through the multiplexer as shown in FIGS.
It is read to the lower half L of the divided serial register 107-1. The multiplexer 130-1 is set for the transfer from the lower half L to the lower half L (control signal LL). There are 32 bits in each segment or square 1, 9, 17 and 25. It should be understood that these numbers indicate that they are tile 1 segments. While this data resides in the split serial register 107-1 during time slot 1, only 32 bits representing segment 1 are sent to video display 112. The number 1 representing tile segment 1 is enclosed in a circle to indicate that segment should be sent to the video display. The initial tap address to be stored in the initial tap register 137 is the address of the first bit of segment 1. Operation count register 1
32 is stored in 40, which interrupts sequential reading when 32 bits are read from the split serial register. Segments 9, 17 and 25 are not sent during timeslot 1. The next step of the sequential reading will be described with reference to FIGS. While segments 1, 9, 17 and 25 are in the lower half of the register, the lower half L of the second row of memory array 105-1
Data is transferred to the upper half H of the divided serial register 107-1 through the multiplexer. The multiplexer 130-1 is set for the transfer from the lower half L to the upper half H (control signal L-H). The bits of segments 2, 10, 18 and 26 are transferred to the upper half of split serial register 107-1. During timeslot 2, 32 bits representing segment 2 are sent to the display device. This is done by storing the appropriate start address and operation count while the segment is transferred to the split serial register. The number 2 is circled to indicate that segment 2 is sent to the display in the sequence following segment 1. In FIGS. 7-11, for each Timestro, only one segment number is circled, indicating which tile segment is in the sequence towards the display. For each time slot, the appropriate start address and operation count are stored and used.

10 and 11 show segments 57 and 5
8 is an additional example showing data from memory rows 1 and 2 transferred to a split serial register via a multiplexer to send 8 to the display.

FIG. 8 shows a timeline for a sequence of tile segments sent from the split serial display 107-1 of FIG. 3 to the display.
The tiles are stored by alternately sending the data stored in the sequential rows of the lower half of the random access memory to the lower and upper halves of the split serial register, and then the data stored in the upper half of the random access memory as well. The segment is, as shown in FIG.
2, 3. ． ． 1 to the video display 112 of FIG.

Referring to FIG. 13, the memory array 105
-1 stored data from the video display 1
12 is a graphic display as an image formed by the tile segment information represented by the raster scanning sequence. The numbered segments of data are ordered 1, 2 ,. ． ． 64 to the video display.
Each scan of the raster contains eight data segments, one segment for each of the eight tiles per scan. There are 8 tiles on the full screen of the display. Each tile is in a separate row on the screen,
It is identified by the number in the top row of that column. Thus, tiles are 1, 2 ,. ． ． Numbered 8 Note that all data for each tile of the display screen is mapped from different rows of memory array 105 of FIG.

FIG. 14 shows another configuration of the serial read circuit and the serial read control circuit for the system using the split shift register. Note that the same features as those in FIG. 3 are designated with the same identification numbers. Different identification numbers are used for different features.

When data is to be read serially from an array of memory cells, a control signal on lead 160 transfers data from either the lower or upper half of the memory to either the lower or upper half of the split shift register. To be done. The split shift register is configured to have a tap for data output in each stage. The tap address register 175 is loaded with the address of the tap at which the first bit of the data sequence and the subsequent data is to be output. When the signal is sent from the comparator 145 to the tap address register 175, the tap address is loaded into the register decoder 192. The register decoder 192 stores the tap address during the current serial read operation. The decoded signal is sent to gate 132-1 to identify the selected tap and to enable the tap to read data from its associated shift register stage.

The shift clock signal sent to the division shift register 191-1 and the operation counter 142 shifts the data along the stage of the shift register 191-1 and increases the count of the operation counter 142. During each clock cycle, a new bit of data is stored in the shift register stage associated with the selected tap. This new bit is gate 132-1 and lead 1
It is read out via 18-1 and transmitted to a video display (not shown).

The comparator 145 continuously compares the count of the operation counter 142 with the operation count value stored in the operation count register 140. If they do not match, the comparator produces a low output signal. However, if they match, the comparator produces a high output signal. This high output signal is a signal that resets the operation counter 142 to zero, and the tap address register 175 outputs a new tap address to the register decoder 19.
It is also a signal that allows it to be sent to

Although the preferred embodiments of the present invention have been described above in detail, it is clear that the present invention merely describes the present invention and that various modifications can be made within the scope of the claims.

The following items will be disclosed in relation to the above description. (1) A data register including a plurality of data storage elements having sequential addresses, the storage elements being divided into a first portion and a second portion by addresses, and an address generation for sequentially addressing the storage elements. And a start address register for presetting the address generator to a first start address in a first portion of the address of the storage element, and disabling the sequential address operation of the storage element, and A random access memory system comprising: a control circuit for presetting the address generator at a second start address in a second portion of the address.

(2) The control circuit includes a start address register, an operation counter that counts the number of sequential addresses in the access operation, and a comparator that determines when to stop the sequential address operation of the storage element. The random access memory system according to the above item 1.

(3) It includes a plurality of storage elements for storing data, the storage element having a sequential address, and a data register divided into an upper half and a lower half by an address, and a storage A decoder for generating a series of storage element addresses to read the stored data; an address register for sending a first start address to preset the decoder to start the storage element addresses of the lower half of the series; and an access operation. At a higher storage element address, including a counter for counting the number of sequential addresses in, a comparator for determining when to stop generating a series of lower half storage element addresses, and an address register. To make the decoder jump to the second start address Random access memory system characterized by comprising a circuit.

(4) A memory array of memory cells,
A memory array configured to store data to be accessed by an individual address of a storage cell, such that the storage cell is divided into an upper half and a lower half of a storage element by the address, and serial access by the address A data register having a storage element configured to store data to be stored, wherein the storage element is divided into an upper half and a lower half by an address; A gate for transferring the stored data, an access circuit for generating a series of addresses of the storage element, and a first address to the access circuit for starting the series of addresses of the storage element in the lower half of the data register. Register for presetting, Random access memory system characterized by comprising a control circuit for presetting the second address in the lower half of the data register access circuit to stop the generation of the address of the communication.

(5) The random access memory system according to the above item 4, wherein the storage cells and elements are dynamic memory devices. (6) The random access memory system according to item 4, wherein the storage cells and elements are static memory devices. (7) The random access memory system according to the above item 4, wherein the storage cells and elements are bistable electronic devices.

(8) The random access memory system according to the above item 4, wherein the storage cells and elements are bistable magnetic devices. (9) The random access memory system according to the above item 4, wherein the storage cells and elements are bistable optical devices. (10) The random access memory system according to the above item 4, wherein the storage cells and elements are bistable optoelectronic devices.

(11) A video display including a screen, a data processor for generating a data signal representing information to be displayed on the screen of the video display, and a storage cell for storing the data signal received from the data processor. Memory array, a data register having upper and lower address portions for receiving and storing a data signal sent from a memory cell of the memory array, both a specific start address and a specific stop address in the data register And a structure for respectively determining where to start and stop the data access operation for sending a data signal from the storage location of the data register to the screen of the video display. Processing system.

(12) A data processor that generates data to be displayed as tiles, a random access memory system configured to store all data tiles in selected rows of storage cells, and random access from the data processor. An access circuit for transferring tiles of data to selected rows of the memory system.

(13) A plurality of column lines connected to the storage cells and including the lower half and upper half column lines associated with each storage cell, and the random access memory system includes a split register, each of the split registers The half is configured to receive data simultaneously from half of multiple column lines of a random access memory system, and through the column line from either the lower half or the upper half of the storage cells, the lower or upper half of the split register. 13. The graphic display system of claim 12, further comprising a multiplexer configured to transfer data to any of the.

(14) A raster scanning display device,
13. A graphic display system according to claim 12, comprising a serial read circuit for transferring data in a line-by-line sequence from a random access memory to a raster scan display device. (15) A data processor for generating data for a display screen tile containing a predetermined number of line segments, a random access memory with information storage locations arranged in a matrix, and transmitting tile data to the random access memory and displaying the display screen tile. An access circuit for storing a predetermined number of line segments in a single row of data storage locations.

(16) A random access memory including a plurality of column lines connected to the memory cells including the lower half memory cell and the upper half memory cell and a division register, each half of the division register being a random access memory. A random access memory configured to receive data from half of multiple column lines at a time, and either the lower half or the upper half of the storage cells through the column line to either the lower half or the upper half of the split register. 16. A graphic display system according to claim 15 comprising a multiplexer configured to transfer data to and from.

(17) A processor that generates data to be displayed as tiles, a random access memory whose information storage location is composed of addressable rows and columns for storing tile data, and stores tile data. An address register for selecting addressable row and column information storage locations for: and a bus for transmitting the storage location address and tile data to the address register and the random access memory, respectively, the random access memory comprising: A graphic display system further configured to store all tile data in a single addressable row of information storage locations.

(18) The random access memory is
A split register including storage elements, configured to receive data from one half of the storage cells simultaneously, and from either the lower half or the upper half of the storage cells, the lower half or the upper half of the storage elements of the split register. 18. The graphic display system of claim 17, further comprising a multiplexer configured to transfer data to either half.

(19) The thirteenth aspect further comprising a display device and a circuit for transferring data from the division register to the display device in a line-by-line sequence.
Item 19. A graphic display system according to item 16, item 16 or item 18. (20) The graphic display system according to any one of items 1, 3, 4, 11, 13, 16 or 18, wherein the division register is a division serial register.

(21) The division register is a division serial register, and the first, third, fourth, eleventh, and first sections are provided.
The graphic display system according to item 3, 16, or 18.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a portion of a graphics processing system.

FIG. 2 is a block diagram showing circuitry on a video random access memory integrated circuit chip.

FIG. 3 is a block diagram of a random access memory system configured with a multiplexer between a memory array and a split serial register.

FIG. 4 is a circuit diagram of a multiplexer for connecting either the lower half or the upper half of the memory array address to either the lower half or the upper half of the divided serial register address.

5 is a truth table defining the operation of the multiplexer of FIG.

FIG. 6 is a map showing where tile data is stored in a memory array to define a screen of information in operation of an exemplary tile orientation system.

FIG. 7 is a table showing a sequence for transferring data from a memory cell of a random access memory array and storing it in a storage element of a split serial register.

FIG. 8 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 9 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 10 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 11 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 12 is a timeline showing a sequence for moving data from a split serial register to a display.

FIG. 13 is a map showing where tile information is displayed on a display screen.

FIG. 14 is a block diagram of a random access memory system in which a multiplexer is arranged between a memory array and a split shift register.

[Explanation of symbols]

 100 Data Processing System 102 Host Processing System 103 Graphic Processor 104 Memory Bus 105 Video Random Access Memory 107 Data Register 108 Video Palette 110 Digital / Video Converter 112 Video Display 114 Read Only Memory 116 Video Control Bus 127 Output Line 130 Multiplexer 132 Gate Circuit 135 Counter decoder 137 Initial tap register 140 Operation count register 145 Comparator

[Procedure amendment]

[Submission date] August 9, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a portion of a graphics processing system.

FIG. 2 is a block diagram showing circuitry on a video random access memory integrated circuit chip.

FIG. 3 is a block diagram of a random access memory system configured with a multiplexer between a memory array and a split serial register.

FIG. 4 is a circuit diagram of a multiplexer for connecting either the lower half or the upper half of the memory array address to either the lower half or the upper half of the divided serial register address.

5 is a diagram showing a truth table that defines the operation of the multiplexer shown in FIG. 3;

FIG. 6 is a map showing where tile data is stored in a memory array to define a screen of information in operation of an exemplary tile orientation system.

FIG. 7 shows a sequence table for transferring data from a memory cell of a random access memory array and storing it in a storage element of a split serial register.

FIG. 8 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 9 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 10 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 11 is a block diagram showing selected rows of memory, multiplexers, split serial registers and control circuits in four different operating states.

FIG. 12 is a timeline showing a sequence for moving data from a split serial register to a display.

FIG. 13 is a map showing where tile information is displayed on a display screen.

FIG. 14 is a block diagram of a random access memory system in which a multiplexer is arranged between a memory array and a split shift register.

DESCRIPTION OF SYMBOLS 100 data processing system 102 host processing system 003 graphic processor 104 memory bus 105 video random access memory 107 data register 108 video palette 110 digital / video converter 112 video display 104 read-only memory 116 video control bus 127 output line 130 Multiplexer 132 Gate circuit 135 Counter decoder 137 Initial tap register 140 Operation count register 145 Comparator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Antony M Balistrelli United States Texas 77056 Huston Woodway 4944 Apartment 23 (72) Inventor Karl M Guggtag Texas, USA 77459 Missouri City South Sandy Court 4015 (72) Invention By Richard Dee Simpson United Kingdom Bedford Carlton Pavenham Road 16

Claims (1)

[Claims] 1. A data register comprising a plurality of data storage elements having sequential addresses, the storage elements being divided into a first part and a second part by an address, and for sequentially addressing said storage elements. An address generator, a start address register for presetting the address generator to a first start address in a first part of the address of the storage element, and disabling the sequential address operation of the storage element, A random access memory system comprising: a control circuit for presetting the address generator to a second start address in a second portion of the address of the element.