JPS61204719A - Information processing system - Google Patents

Abstract

PURPOSE:To prevent a breakdown of a data which is being transferred, by avoiding positively an influence caused by cut-off of a power source and an issue of system reset, so that the execution of an operation is not halted, in case of executing a write or read-out operation to and from an input/output device. CONSTITUTION:An information processor 7 always checks a signal line 52 before executing a write or read-out operation to and from an input/output device 8, and executes the operation only in case when an advance notice signal is in a low level. As for an advance notice circuit, when one of signal lines 11, 41 becomes a low level, a counter 403 starts to count, and when one of the signal lines 11, 41 is maintained as a low level for a specified time, a high level is outputted to a signal line 51. During this time, the advance notice signal from the signal line 52 outputs continuously a high level for a specified time. Also, when the low level of the signal lines 11, 41 is released within the specified time, an output line 411 becomes a low level, the counter 403 is cleared, and the advance notice signal becomes a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing system that uses an input/output device having a recording medium, and relates to an information processing system that avoids failures due to power interruption and issuance of a system reset.

[Background of the invention]

If a system reset is issued to initialize the system or the power is turned off while an information processing device is writing to or reading from an input/output device, not only will the execution become invalid, but the transfer The data inside may be destroyed. Conventional countermeasures are to generate an interrupt signal when the above situation is detected, and
The idea was to perform corresponding processing, but these were:
This has the problem that the interrupted execution must be re-executed.

In addition, as a related device of this type, for example, Japanese Patent Application Laid-Open No. 58
Examples include those described in No. 165498 and No. 223996.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing system in which power-off and issuance of a system reset not based on software commands do not harm write or read operations to input/output devices.

[Summary of the invention]

In the present invention, when an information processing device performs a write or read operation to an input/output device, it always checks the power input state and the system reset issue instruction state, and checks whether the power input is normal and there is no system reset issue instruction. After confirming the above, these operations are performed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows an example of the advance notice circuit shown in FIG. 1, and FIG. 3 is a flowchart during write and read operations.

In FIG. 1, 1 is a power input detection circuit, which transmits the power as it is to the DC power supply device 2, and sends a high level signal to the signal line 11 when there is a power input, and a low level signal when there is no power input. Output. The DC power supply device 2 generates a current of a predetermined voltage from the power input and supplies it to each part of the system, and even if the power input is interrupted, it maintains the DC power necessary for the system for a specified period of time or longer. 3 is a circuit that instructs the issuance of a system reset that is not based on a software instruction; the system reset resets the registers and flip-flops of the system and initializes the system. When instructing to issue a system reset, a low level signal is output to the signal line 41, and when not issuing an instruction, a high level signal is output to the signal line 41. Reference numeral 4 denotes a warning circuit which, when a power-off and system reset issuance instruction is detected via signal lines 11 and 41, sends a signal to signal line 52.
outputs a high-level warning signal for the specified time.

Signal line 11 for power failure detection and system reset issue instruction.
41 does not return to the high level within the specified time, a system reset issue instruction is further output to the signal line 51. If it returns, the warning signal is set to low level at that point. Reference numeral 5 denotes a system reset issuing circuit which outputs a system reset signal to the signal line 61 in response to a high level pulse signal from the signal line 51. 7 is an information processing device. Reference numeral 8 denotes an input/output device having, for example, a floppy disk as a recording medium, and read/write operations thereof mean input/output to the floppy disk.

The information processing device 7 always checks the signal line 52 before performing a write or read operation to the input/output device 8.
The operation is executed only when the warning signal is low level. At this time, the specific time is set to be sufficiently long with respect to the maximum execution time of the operation.

Here, the operation of the advance notice circuit 4 will be described. The notice circuit is the second
This can be realized with the configuration of the block diagram shown in the figure. 401 is a NAND gate for input signals.

402 is a clock generation circuit, 403 is a counter to which the specific time is set, 404 is a NOR gate for generating a notice signal from the output of the counter, and 405 is a system reset issue instruction signal that detects the end of the specific time. The output line 411 of the NAND gate 401 is branched into two lines, and one input to the counter 403 is at a high level to enable the counter 403, and the other is at a low level to enable the counter 403. This is for inputting to CLEAR of the counter 403.

In this warning circuit, when either of the signal lines 11 or 41 becomes low level, the counter 403 starts counting.
as it is for the specified time.

If either of the signal lines 11 and 41 is maintained at a low level, a high level is output to the signal line 51. During this time,
The warning signal from the signal line 52 continues to output a high level during the specified time.

Furthermore, if the low level of the signal line 11.41 is canceled within the specified time, the output line 411 becomes low level,
The counter 403 is cleared, the advance notice signal becomes low level, and no high level signal is output to the signal line 51. Further, even when the system maintains a normal state, the counter 403 of the notice circuit 4 maintains the CLEAR state, and the notice signal and system reset issue instruction signal are not generated.

FIG. 3 is a flowchart showing an algorithm when the information processing device 7 performs a writing or reading operation to the input/output device 8. As shown in FIG.

As a result, a write or read operation is executed only when the notice signal is at a low level. The specific time is set to be sufficiently longer than the maximum execution time of the operation, so that it is possible to avoid being affected by power-off and issuance of a system reset during execution of the operation. Even if a power-off and system reset is issued immediately after the start of operation, the system will not be affected until after the specified time;
The execution of the action has finished.

〔Effect of the invention〕

As described above, according to the present invention, when an information processing device performs a write operation or a read operation to an input/output device having a recording medium, the influence of power outage and system reset issuance is actively avoided and the operation is performed. The execution of the data is not interrupted, so the data being transferred is not destroyed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the notice circuit shown in FIG. 1, and FIG. 3 is a flowchart during write/read operations. 1... Power input detection circuit, 2... DC power supply device, 3
...System reset issue instruction circuit. 4... Notice circuit, 5... System reset issuing circuit, 7... Information processing device, 8... Input/output device, 402... Clock generation circuit, 403... Counter. Figure 1 Figure 2

Claims (1)

[Claims] In a system in which an information processing device and an input/output device having a recording medium are connected, the power supply device supplies power to the information processing device and the input/output device, and even if the power input is cut off, the power supply is turned off for a specific time. a circuit that can continue to supply power, a circuit that detects disconnection of power input to the power supply device, a circuit that instructs the information processing device to issue a system reset, and a circuit that writes to or reads from the input/output device. An information processing system characterized in that the information processing system further comprises means for detecting the state of the power input disconnection detection circuit and the system reset issue instruction circuit.