JPS61191955A - Semiconductor sensor and manufacture thereof - Google Patents

Semiconductor sensor and manufacture thereof

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Publication number
JPS61191955A
JPS61191955A JP60033101A JP3310185A JPS61191955A JP S61191955 A JPS61191955 A JP S61191955A JP 60033101 A JP60033101 A JP 60033101A JP 3310185 A JP3310185 A JP 3310185A JP S61191955 A JPS61191955 A JP S61191955A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor sensor
base
elements
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60033101A
Other languages
Japanese (ja)
Other versions
JPH068800B2 (en
Inventor
Tadashi Sakai
忠司 酒井
Masaki Katsura
桂 正樹
Hideaki Hiraki
平木 英朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60033101A priority Critical patent/JPH068800B2/en
Priority to CA000501835A priority patent/CA1251514A/en
Priority to US06/831,314 priority patent/US4791465A/en
Priority to DE8686301229T priority patent/DE3681938D1/en
Priority to EP86301229A priority patent/EP0192488B1/en
Publication of JPS61191955A publication Critical patent/JPS61191955A/en
Publication of JPH068800B2 publication Critical patent/JPH068800B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403Cells and electrode assemblies
    • G01N27/414Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

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  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Molecular Biology (AREA)
  • Analytical Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Power Engineering (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

PURPOSE:To obtain a sensor suitable for volume production at a low cost, by forming a plurality of sensor elements on an Si substrate separately after the Si substrate is joined on the surface of a base body without the use of an adhesive. CONSTITUTION:An Si substrate is adhered is adhered on to the tip surface of an Si base body 11 with the surface thereof machined flat in a clean atmosphere, joined together directly through a SiO2 film 13 by heating up to higher than 200 deg.C and then, a plurality of sensors are formed on the Si substrate 12 separately. Then, the Si portion is removed except for the area where the sensor elements were formed and the exposed surface of the Si substrate is covered with an insulation film 17 for passivation made of Si3N4 or the like. The base body 11 is divided into respective sensor elements by dicing. This enables the passivation of the entire elements without any special process such as outline machining thereof to achieve the complete insulation without exposing Si of the elements to the cut section.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体センサに係わり、特に素子が直接溶液
に晒される半導体センサの構造及びその製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor sensor, and more particularly to a structure of a semiconductor sensor whose elements are directly exposed to a solution and a method for manufacturing the same.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体センサ、特に直接素子が溶液に触れるl5FET
においては、素子全体を絶縁する必要がある。素子全体
を絶縁する方法としては、これまで次の2つの方法が代
表的である。
Semiconductor sensors, especially 15FETs whose elements directly touch the solution
In this case, it is necessary to insulate the entire device. To date, the following two methods have been typical as methods for insulating the entire element.

(1)  素子全体をSigN+等のパッシベーション
膜で覆う方法。
(1) A method of covering the entire element with a passivation film such as SigN+.

(2]  サファイア基板上にSiをエピタキシャル成
長させた、所m5os基板を用いる方法。
(2) A method using an m5os substrate in which Si is epitaxially grown on a sapphire substrate.

しかしながら、この種の方法にあっては次のような問題
があった。
However, this type of method has the following problems.

即ち、第1の方法では、パッシベーション膜形成前に予
め、素子外形をくり汰き(実際はエツチングしてすかし
ぼり状に素子を残す)、外周全面に躾が形成できるよう
にしておかねばならない。
That is, in the first method, before forming the passivation film, the outer shape of the element must be cut out (actually, the element is etched to leave a diagonal shape) so that the groove can be formed on the entire outer periphery.

このため、工程が煩雑となる他、くり扱き加工によるウ
ェハの強度低下、エツチング液による汚染の虞れ(アル
カリ性エッチャントを通常用いるため、エツチング後は
通常のプロセスに入れることができない)等の問題があ
る。従って、現在広く普及しているウェハスケールの半
導体製造ラインを用いることができず、大量生産にも適
さない。
For this reason, the process becomes complicated, and there are other problems such as a reduction in the strength of the wafer due to handling, and the risk of contamination from the etching solution (because an alkaline etchant is normally used, the wafer cannot be used in the normal process after etching). be. Therefore, the currently widely used wafer scale semiconductor manufacturing line cannot be used, and it is not suitable for mass production.

第2の方法では、第5図に示す如くサファイア基板51
上のSi層52に素子を形成した後、素子以外のSi層
をエツチング除去し、サファイア基板51を露出させる
。その後、全面にS:3N4等のパッシベーション膜5
3を形成し、素子部分を完全にサファイアとパッシベー
ション膜で覆ってしまう。この方法を用いれば、素子の
外形加工は必要なく、ウェハから通常のダイシングによ
って、素子を切り出すことができる(切断面は、Si3
N+とサファイアとがでるだけで、素子は絶縁されてい
る)。このように優れた方法ではあるが、基板となるS
oSウェハの作成に工数がかかり高価となる他、基板サ
ファイアからのA℃による汚染の可能性もある。
In the second method, a sapphire substrate 51 as shown in FIG.
After forming an element on the upper Si layer 52, the Si layer other than the element is removed by etching to expose the sapphire substrate 51. After that, a passivation film 5 of S:3N4 etc. is applied to the entire surface.
3, and the element portion is completely covered with sapphire and a passivation film. If this method is used, there is no need to process the external shape of the device, and the device can be cut out from the wafer by normal dicing (the cut surface is Si3
The element is insulated with only N+ and sapphire appearing). Although this is an excellent method, the S
In addition to requiring many man-hours to create an oS wafer and making it expensive, there is also the possibility of contamination by A° C. from the sapphire substrate.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情を考慮してなされたもので、その目的
とするところは、SO8基板を用いることなく、廉価に
実現することができ、且つ大量生産に適した半導体セン
サの構造及びその製造方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to provide a structure of a semiconductor sensor that can be realized at low cost without using an SO8 substrate, and is suitable for mass production, and a method for manufacturing the same. Our goal is to provide the following.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、接着剤を用いないSiウエハの直接接
着技術を利用して半導体センサを形成することにある。
The gist of the present invention is to form a semiconductor sensor using direct bonding technology of Si wafers without using an adhesive.

即ち本発明は、素子自体が直接溶液等に晒される半導体
センサにおいて、表面が平坦に加工された基体と、この
基体上の表面中央部に接着剤を用いることなく接合され
センサ素子が形成されたSi基板と、少なくともこのS
i基板の露出表面を被覆するよう形成された絶縁膜とを
具備してなるものである。
That is, the present invention provides a semiconductor sensor in which the element itself is directly exposed to a solution, etc., in which a sensor element is formed by bonding to a base whose surface is processed to be flat and the center of the surface of this base without using an adhesive. Si substrate and at least this S
and an insulating film formed to cover the exposed surface of the i-substrate.

また本発明は、上記構造の半導体センサを製造する方法
において、表面がそれぞれ平坦な状態にある基体とSi
基板とを清浄な雰囲気中で密着し、この状態で200 
[’C]以上に加熱して上記基体及びSi基板を接合し
たのち、上記Si基板に複数のセンサ素子を離間して形
成し、次いで上記センサ素子が形成された領域以外のS
i部分を除去し、次いで少なくともSi基板の露出表面
を絶縁膜で被覆し、しかるのち前記基体をダイシングし
て個々のセンサ素子に分割するようにした方法である。
Further, the present invention provides a method for manufacturing a semiconductor sensor having the above structure, in which a substrate having a flat surface and a silicon
The substrate is placed in close contact with the substrate in a clean atmosphere, and in this state it is heated for 200
['C] After bonding the base body and the Si substrate by heating to a temperature above ['C], a plurality of sensor elements are formed on the Si substrate in a spaced manner, and then S
In this method, the i-portion is removed, at least the exposed surface of the Si substrate is coated with an insulating film, and then the substrate is diced and divided into individual sensor elements.

本発明では、Siウエハの直接接着技術を用いているが
、この接着には次のような接合法を用いればよい。即ち
、S(ウェハ等の接合すべき表面を表面粗さ500[人
]以下に鏡面研磨したのち、水洗処理等により研磨表面
を親水性にする。次いで、親水性となった表面同志を密
着し、この状態で200 [’C]以上に加熱すること
によって、強固な直接接合が得られることになる。
In the present invention, a direct bonding technique for Si wafers is used, but the following bonding method may be used for this bonding. In other words, the surfaces of S (wafers, etc.) to be bonded are mirror-polished to a surface roughness of 500 [mm] or less, and then the polished surfaces are made hydrophilic by washing with water or the like.Then, the surfaces that have become hydrophilic are brought into close contact with each other. , By heating to 200 ['C] or higher in this state, a strong direct bond can be obtained.

本発明では、この接合ウェハの片面のSiを10〜30
[μm]の厚みを残して研磨ラツビングする。そして、
このSi面上に素子を形成し、不要Si部分をエツチン
グ除去する。その後、S i3N4 ,Al2O3.T
az Os等の無機物絶縁膜を全体に看護し、パッシベ
ーションとする。
In the present invention, the Si on one side of this bonded wafer is 10 to 30
Polish and rub, leaving a thickness of [μm]. and,
A device is formed on this Si surface, and unnecessary Si portions are removed by etching. After that, Si3N4, Al2O3. T
An inorganic insulating film such as az Os is applied to the entire surface to provide passivation.

ここまでをウェハスケールで処理した後ダイシングすれ
ば、切断面に素子部のシリコンは露出せず、完全に絶縁
することができることになる。
If the process up to this point is performed on a wafer scale and then diced, the silicon in the element portion will not be exposed on the cut surface and can be completely insulated.

(発明の効果〕 本発明によれば、素子外形加工等の特殊なプロセスなし
に、素子全体をパッシベーションすることができる。し
かも、SO8基板等を用いる必要もないので、製造コス
トの増大を招くこともない。
(Effects of the Invention) According to the present invention, the entire device can be passivated without special processes such as processing the device external shape.Furthermore, there is no need to use an SO8 substrate, etc., so there is no need to increase manufacturing costs. Nor.

このため、半導体センサの大量生産を実現することがで
き、且つ製造コストの低減をはかり得る。
Therefore, mass production of semiconductor sensors can be realized, and manufacturing costs can be reduced.

〔発明の実施例〕[Embodiments of the invention]

第1図は本発明の一実施例に係わるl5FETの概略構
造を示す平面図、第2図は第1図の矢視A−A断面断面
筒3図は第1図の矢視B−8断面図である。Si基体1
1の上面にSiO2膜13を介しでSi基板12が直接
接合されている。
FIG. 1 is a plan view showing a schematic structure of an 15FET according to an embodiment of the present invention, and FIG. 2 is a cross section taken along arrow A-A in FIG. It is a diagram. Si substrate 1
A Si substrate 12 is directly bonded to the upper surface of the substrate 1 with an SiO2 film 13 interposed therebetween.

Si基板12はSi基体11の表面中央部に選択的に形
成されている。Si基板12の表面には、不純物拡散に
よりソース14及びドレイン15がそれぞれ形成されて
いる。また、Si基板12の上面にはゲート酸化膜(S
in2膜)16が形成されている。そして、上記接合さ
れたSi基体11及びSi基板12の上面全面には、パ
ッシベーション膜として5isN+膜17が形成されて
いる。
The Si substrate 12 is selectively formed at the center of the surface of the Si substrate 11. A source 14 and a drain 15 are formed on the surface of the Si substrate 12 by impurity diffusion. Further, on the upper surface of the Si substrate 12, a gate oxide film (S
in2 film) 16 is formed. A 5isN+ film 17 is formed as a passivation film on the entire upper surface of the bonded Si base 11 and Si substrate 12.

このような構造であれば、Si基板12に形成された素
子はその周囲を5iO2113及びSi3N+膜17で
完全に覆われたものとなり、素子は完全にパッシベーシ
ョンされることになる。
With such a structure, the device formed on the Si substrate 12 is completely covered with the 5iO2113 and Si3N+ film 17, and the device is completely passivated.

第3図(a)〜(d)は上記実施例センサの製造工程を
示す断面図である。まず、Si基体として、厚さ400
[μTrL]のSiウエハ(3インチ径、P型、8濃度
10”/Q13)11.12を用意し、これらの接合す
べき各表面を表面粗さ500[人]以下に鏡面研磨した
。次いで、第1のSi基体11の表面に厚さ1000[
入コの熱酸化膜13を形成したのち、第1及び第2のS
i基体を水洗処理等により親水性とした。続いて、第3
図(a)に示す如く基体11.12を清浄な雰囲気中で
密着し、この状態で200 [”01以上に加熱して各
基体11.12同志を接合した。
FIGS. 3(a) to 3(d) are cross-sectional views showing the manufacturing process of the sensor of the above embodiment. First, as a Si substrate, the thickness is 400 mm.
[μTrL] Si wafers (3 inch diameter, P type, 8 concentration 10”/Q13) 11.12 were prepared, and each surface to be bonded was mirror polished to a surface roughness of 500 [person] or less. Next, , the surface of the first Si substrate 11 has a thickness of 1000 [
After forming the thermal oxide film 13, the first and second S
The i-substrate was made hydrophilic by washing with water or the like. Next, the third
As shown in Figure (a), the substrates 11 and 12 were brought into close contact with each other in a clean atmosphere, and in this state, the substrates 11 and 12 were bonded together by heating to a temperature of 200°C or more.

次いで、第3図(b)に示す如く上側の第2のSi基体
12を30[μmlの厚さになるまで研磨し、ラッピン
グ仕上げした。これにより、前記Si基体12が簿いS
i基板となる。。
Next, as shown in FIG. 3(b), the upper second Si substrate 12 was polished to a thickness of 30 μml and finished by lapping. As a result, the Si substrate 12 is
This will be the i-board. .

次いで、第3図(C)に示す如<Si基板12に不純物
を選択的に拡散し、ソース14及びドレイン15を形成
した。これにより、ゲート幅400 [μTrL] 、
ゲート長20[μTrL]のゲートが形成される。なお
、この構造では、ゲート部以外のソース・ドレイン間の
分離が完全なため、チャネルストッパが不要である。ま
た、この工程では、複数のFET素子をそれぞれ離間し
て形成した。その後、素子部以外のSiをエツチング除
去し、Si基体1113を露出させた。
Next, as shown in FIG. 3(C), impurities were selectively diffused into the Si substrate 12 to form a source 14 and a drain 15. As a result, the gate width is 400 [μTrL],
A gate with a gate length of 20 [μTrL] is formed. Note that this structure does not require a channel stopper because the isolation between the source and drain other than the gate portion is complete. Further, in this step, a plurality of FET elements were formed separately from each other. Thereafter, the Si other than the element portion was removed by etching to expose the Si substrate 1113.

次いで、第3図(d)に示す如く、素子ゲート部をゲー
ト酸化して厚さ500[人]、のゲート酸化1116を
形成したのち、全体にSi3N+膜17をCVD法で厚
さ800 [人]着躾した。その後、コンタクト形成部
をのSi3N+膜17及びSiO2膜16をエツチング
除去し、コンタクトパッド(図示せず)を蒸着形成した
。その後、ダイシングにより、個々のセンサに切り出す
ことによって、前記第1図及び第2図に示す如き形状が
得られた。
Next, as shown in FIG. 3(d), after gate oxidizing the device gate portion to form a gate oxidation layer 1116 with a thickness of 500 mm, a Si3N+ film 17 is formed on the entire surface by CVD to a thickness of 800 mm. ] I was disciplined. Thereafter, the Si3N+ film 17 and the SiO2 film 16 in the contact formation area were removed by etching, and a contact pad (not shown) was formed by vapor deposition. Thereafter, the sensor was cut into individual sensors by dicing, thereby obtaining the shapes shown in FIGS. 1 and 2.

かくして形成されたl5FETは、H+イオンセンサと
して、従来型のセンサと同様、約50[mV/PH]の
感度を示し、長時間の使用においても絶縁破壊は見られ
なかった。
The thus formed 15FET exhibited a sensitivity of about 50 [mV/PH] as an H+ ion sensor, similar to conventional sensors, and no dielectric breakdown was observed even after long-term use.

このように本実施例によれば、ウェハスケールの通常の
半導体製造ラインで、素子部が完全にパッシベーション
されたl5FETを製造することができる。さらに、S
O8基板を用いる必要もなく、Si基体を用いるのみで
よい。このため、l5FETの大量生産が可能となり、
その製造コストの大幅な低減をはかり得る。
As described above, according to this embodiment, an 15FET whose element portion is completely passivated can be manufactured on a normal wafer scale semiconductor manufacturing line. Furthermore, S
There is no need to use an O8 substrate, and only a Si substrate is sufficient. For this reason, mass production of 15FET is possible,
The manufacturing cost can be significantly reduced.

また、素子形成側のSi層を十分厚く形成することがで
きる。例えば、一般的な3インチウェハを用いれば、4
50[μ7rL]の厚さが可能である。
Further, the Si layer on the element forming side can be formed sufficiently thick. For example, if a typical 3-inch wafer is used, 4
A thickness of 50 [μ7rL] is possible.

このため、深い拡散が可能であり、フンタクトまでの配
線抵抗を減少させることができる等の利点もある。これ
に対しSO8では、エピタキシャル成長による堆積層の
ため、その厚みに限界があり、約20[μyyt]以上
に厚く形成することはできなかったのである。
Therefore, deep diffusion is possible, and there are also advantages such as being able to reduce wiring resistance up to the contact point. On the other hand, in SO8, since it is a deposited layer formed by epitaxial growth, there is a limit to its thickness, and it was not possible to form it thicker than about 20 [μyyt].

なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記同一チップ状に形成する素子は1つに
限るものではなく、2つ以上の素子を形成してもよい。
Note that the present invention is not limited to the embodiments described above. For example, the number of elements formed on the same chip is not limited to one, and two or more elements may be formed.

この場合にも、素子相互間の絶縁分離は完全であり、ま
たゲート部以外のチャネルストッパも不要でマルチ化が
容易である。
In this case as well, the insulation isolation between the elements is perfect, and there is no need for a channel stopper other than the gate portion, making multiplication easy.

また、前記Si基板の素子領域以外を全て除去すること
なく、第4図に示す如く一部に残してここに拡散抵抗層
18を形成し、この拡散抵抗層18によりヒータを内蔵
したセンサの実現が可能となる。また、前記パッシベー
ション膜は、Si3N+に一部るもノテハナク、SiO
2゜S i N、 Affiz 03或いはTa205
等の絶縁膜を使用することが可能である。さらに、素子
を形成する側のSi基板と直接接合可能であれば、前記
Si基体の代りに絶縁基体を用いることも可能 。
Furthermore, without removing all of the Si substrate other than the element area, a diffused resistance layer 18 is formed by leaving a part of the Si substrate as shown in FIG. 4, and this diffused resistance layer 18 realizes a sensor with a built-in heater. becomes possible. In addition, the passivation film is partially made of Si3N+, but is also made of SiO2.
2゜S i N, Afiz 03 or Ta205
It is possible to use an insulating film such as Furthermore, it is also possible to use an insulating substrate instead of the Si substrate as long as it can be directly bonded to the Si substrate on which the element is formed.

である。この場合、基体自体が絶縁体であるため、Si
基板と基体との間のSi02膜を省略することもできる
。その他、本発明の要旨を逸脱しない範囲で、種々変形
して実施することができる。
It is. In this case, since the substrate itself is an insulator, Si
The Si02 film between the substrate and the base body can also be omitted. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係わる半導体センサの概略
構成を示す平面図、第2図(a)は第1図の矢視A−A
断面図、第2図(b)は第1図の矢視8−8断面図、第
3図(a)〜(d)は上記実施例センサの製造工程を示
す断面図、第4図は変形例を説明するための断面図、第
5図は従来のSO8構造の半導体センサの概略構成を示
す断面図である。 11・・・第1のSi基体、12・・・第2のSi基体
(Si基板)、13・・・SiO2!II、14−’/
−ス、15・・・ドレイン、16・・・ゲート酸化膜、
17・・・Si3N+膜(パッシベーション用絶縁II
)、18・・・拡散抵抗層。 出願人代理人 弁理士 鈴江武彦 jl!1  図 第2図 (a) (b) 第3図 第4図 第5図 手続補正書 昭和61年5月20日 、16事件の表示 特願昭60−33101号 2、発明の名称 半導体センサ及びその製造方法 3、補正をする者 事件との関係 特許出願人 (307)  株式会社 東芝 4、代理人 東京都港区虎ノ門1丁目26番5号 第11森ビル6、
補正の対象 7、補正の内容 (1)特許請求の範囲の記載を別紙の通りに訂正する。 (2)明IRiIの第5頁15行目から同頁16行目に
かけて「表面中央部に・・接合さ゛れ」とあるのを、[
表面に接着剤を用いることなく直接接合により接合され
」と訂正する。 (3明細書の第6頁12行目に「接合法」とあるのを、
「直接接合法」と訂正する。 (明 明細書の第6頁14行目にr500 [入]以下
に」とあるのをr500 [入〕以下、好ましくは50
[入]以下に」と訂正する。 ■ 明細書の第10頁4行目に「形成部をの」とあるの
を、「形成部の」と訂正する。 (a 明細層の第11頁9行目と同頁10行目との間に
下記の文章を挿入する。 記 次に、本発明の他の実施例について説明する。 なお、この実施例は、同−基体上に多数個のセンサ素子
を形成した例であり、基本的には先の実施例と同様であ
る。従って、前記第1図及び第2因を参照して説明する
。 先の実施例と同様に、Si基体11の上面にSi基体1
13を介してSi基板12が直接接合により接合されて
いる。ここで、Si基板12は、Si基体11の表面に
複数組形成されている。また、先の実施例と同様に、S
i基板12の表面にはソース14及びドレイン15が、
Si基板12の上面にはゲート酸化膜16が、Si基体
11及びSi基板12の上面全面にはSi3N+17膜
がそれぞれ形成されている。 このような構造であれば、Si基板12に形成された素
子はその周囲を5iOzll113及び313N+−膜
17で完全に覆われたものとなり、素子は完全にバッシ
ベ、−ジョンされることになる。 従って、多数個の素子を同−基体上に形成しても相互に
影響を及ぼすことがなく、多種類の成分検知用として好
都合である。 上記実施例センサの製造工程は、次の通りである。まず
、Si基体として、厚さ20o[μ7FL]のSiウェ
ハ(3インチ径、P型、B濃度10” ’ /4” )
 11 、12ヲ用1にシ、コレラノ接合すべき各表面
を表面粗さ50[人]以下に鏡面研磨する。次いで、第
1のSi基体11の表面に厚さ1[μm]の熱酸化膜1
3を形成したのち、第1及び第2のSi基体を水洗処理
等により親水性にする。続いて、基体11.12を清浄
な雰囲気中で密着し、この状態で1100[’C]に加
熱して各基体11.12同志を接合する。次いで、上側
の第2のSi基体12を10[μm]の厚さになるまで
研磨し、鏡面仕上げする。これにより、5i基体12が
薄いSi基板となる。 次いで、先の実施例と同様に、不純物拡散によりソース
14及びドレイン15を形成し、その後素子部以外のS
iをエツチング除去し、5iO2Si113を露出させ
る。続いて、ゲート酸化11116及びSi3N+j!
17を形成した後、コンタクト形成部の5t3N+膜1
7及び5102膜16をエツチング除去し、コンタクト
パッドを蒸着形成する。その後、ダイシングにより、個
々の組に切出すことによって、前記第1図及び第2図に
示す形状が得られることになる。 かくして形成されたl5FETにあっても、先の実施例
と同様に、H+イオンセンサとして約50 [mv/ 
ph]の感度を示し、長時間の使用においても絶縁破壊
は見られない。なお、H+イオン以外のセンサ上には、
例えば第4級アンモニウム塩、パリノマイシン等をPv
C中に分散してコートする。この場合、それぞれC−、
に◆イオン等を他素子の影響なく(C2−は10°1〜
104mol/1. K” 4;tl 0’ 〜10’
  mol/nの濃度範囲で)検出することができる。 2、特許請求の範囲 (1)表面が平坦な状態に加工された基体と、この基体
上のm1接着剤を用いることなく【111【LL接合さ
れセンサ素子が形成されたSi基板と、少なくともこの
Si基板の露出表面を被覆するよう形成された絶縁膜と
を具備してなることを特徴とする半導体センサ。 (2)前記基体はSi基体であり、前記Si基板は酸化
膜を介して上記5iti体に    e、b1接合され
たものであることを特徴とする特許請求の範囲第1項記
載の半導体センサ。 (3前記基体は、絶縁体であることを特徴とする特許請
求の範囲第1項記載の半導体センサ。 (勾 前記絶縁膜は、SiO2,SiN。 S i3N4 、An203或いはTa205であるこ
とを特徴とする特許請求の範囲第1項記載の半導体セン
サ。 (5)  表面がそれぞれ平坦な状態にある基体とSi
基板とを清浄な雰囲気中で密着し、この状態で200 
[’C]以上に加熱して上記基体及びSi基板を接合す
る工程と、次いで上記Si基板に複数のセンサ素子を離
間して形成する工程と、次いで上記センサ素子が形成さ
れた領域以外のS’+部分を除去する工程と、次いで少
なくともSi基板の露出表面を絶縁膜で被覆する工程と
、次いで前記基体をダイシングして個々のセンサ素子に
分割する工程とを含むことを特徴とする半導体センサの
製造方法。 (61前記基体として5i基体を用い4、前記S1!!
板を酸化膜を介して上記Si基体に接合したことを特徴
とする特許請求の範囲第5項記載の半導体センサの製造
方法。 (7)前記基体として、絶縁体を用いたことを特徴とす
る特許請求の範囲第51N!!a載の半導体センサの製
造方法。 (8)前記絶縁膜として、SiO2,SiN。 S i3N4 、Al1z Os或いはTaz Osを
用いたことを特徴とする特許請求の範囲第5項記載の半
導体センサの製造方法。 出願人代理人 弁理士 鈴江武彦
FIG. 1 is a plan view showing a schematic configuration of a semiconductor sensor according to an embodiment of the present invention, and FIG. 2(a) is a view taken along arrow A-A in FIG.
2(b) is a sectional view taken along arrow 8-8 in FIG. 1, FIGS. 3(a) to 3(d) are sectional views showing the manufacturing process of the above embodiment sensor, and FIG. 4 is a modified view. A sectional view for explaining an example, FIG. 5 is a sectional view showing a schematic configuration of a conventional SO8 structure semiconductor sensor. 11... First Si substrate, 12... Second Si substrate (Si substrate), 13... SiO2! II, 14-'/
- source, 15... drain, 16... gate oxide film,
17...Si3N+ film (passivation insulation II
), 18... Diffused resistance layer. Applicant's agent Patent attorney Takehiko Suzue jl! 1 Figure 2 (a) (b) Figure 3 Figure 4 Figure 5 Procedural amendment May 20, 1985, indication of case 16 Japanese Patent Application No. 1983-33101 2 Title of invention Semiconductor sensor and Manufacturing method 3, relationship with the amended case Patent applicant (307) Toshiba Corporation 4, Agent 11 Mori Building 6, 1-26-5 Toranomon, Minato-ku, Tokyo;
Target of amendment 7, content of amendment (1) The description of the scope of claims is corrected as shown in the attached sheet. (2) From page 5, line 15 to line 16 of Mei IRiI, the phrase “joined in the center of the surface” was replaced with [
"It is joined by direct bonding without using adhesive on the surface." (The ``joining method'' is written on page 6, line 12 of the 3 specifications,
Correct to "direct bonding method." (In the 14th line of page 6 of the specification, it should be 500 [in] or less") should be changed to 500 [in] or less, preferably 50
[Enter] Below” and correct it. ■ On page 10, line 4 of the specification, the phrase ``Formation part wo'' is corrected to ``Formation part no''. (a) Insert the following sentence between line 9 and line 10 of page 11 in the details layer. Next, other embodiments of the present invention will be explained. This is an example in which a large number of sensor elements are formed on the same substrate, and is basically the same as the previous embodiment.Therefore, the explanation will be given with reference to FIG. 1 and the second factor. Similar to the example, the Si substrate 1 is placed on the top surface of the Si substrate 11.
The Si substrate 12 is directly bonded to the Si substrate 12 via the silicon substrate 13 . Here, a plurality of sets of Si substrates 12 are formed on the surface of the Si base 11. Also, as in the previous embodiment, S
A source 14 and a drain 15 are provided on the surface of the i-substrate 12.
A gate oxide film 16 is formed on the upper surface of the Si substrate 12, and a Si3N+17 film is formed on the entire upper surface of the Si substrate 11 and the Si substrate 12, respectively. With such a structure, the device formed on the Si substrate 12 is completely covered with the 5iOzll113 and 313N+- film 17, and the device is completely destroyed. Therefore, even if a large number of elements are formed on the same substrate, they will not affect each other, which is convenient for detecting many types of components. The manufacturing process of the above example sensor is as follows. First, as a Si substrate, a Si wafer (3 inch diameter, P type, B concentration 10''/4'') with a thickness of 20° [μ7FL] was used.
11. For 1.1 and 12., each surface to be joined is mirror polished to a surface roughness of 50 [mm] or less. Next, a thermal oxide film 1 with a thickness of 1 [μm] is formed on the surface of the first Si substrate 11.
3, the first and second Si substrates are made hydrophilic by washing with water or the like. Subsequently, the substrates 11 and 12 are brought into close contact with each other in a clean atmosphere, and heated to 1100['C] in this state to bond each of the substrates 11 and 12 together. Next, the upper second Si substrate 12 is polished to a thickness of 10 [μm] to give it a mirror finish. As a result, the 5i substrate 12 becomes a thin Si substrate. Next, as in the previous embodiment, the source 14 and drain 15 are formed by impurity diffusion, and then the S other than the element portion is
i is removed by etching to expose 5iO2Si113. Subsequently, gate oxidation 11116 and Si3N+j!
After forming 17, 5t3N+ film 1 of the contact forming part
7 and 5102 films 16 are etched away and contact pads are deposited. Thereafter, the shapes shown in FIGS. 1 and 2 are obtained by cutting out individual sets by dicing. Even in the thus formed 15FET, as in the previous embodiment, as an H+ ion sensor, the power of about 50 [mv/
pH], and no dielectric breakdown is observed even after long-term use. Note that on sensors other than H+ ions,
For example, quaternary ammonium salts, palinomycin, etc.
Disperse and coat in C. In this case, C-,
◆Ions etc. without the influence of other elements (C2- is 10°1~
104mol/1. K"4; tl 0' ~ 10'
(mol/n concentration range). 2. Claims (1) A base whose surface is processed to be flat, a Si substrate on which a sensor element is formed by [111[LL] bonding without using m1 adhesive on this base, and at least this 1. A semiconductor sensor comprising: an insulating film formed to cover an exposed surface of a Si substrate. (2) The semiconductor sensor according to claim 1, wherein the base body is a Si base body, and the Si substrate is bonded to the 5iti body through an oxide film. (3) The semiconductor sensor according to claim 1, wherein the base body is an insulator. A semiconductor sensor according to claim 1. (5) A substrate and a Si substrate each having a flat surface.
The substrate is placed in close contact with the substrate in a clean atmosphere, and in this state it is heated for 200
['C] A step of joining the base body and the Si substrate by heating to a temperature above ['C], a step of forming a plurality of sensor elements on the Si substrate in a spaced manner, and then a step of bonding the base body and the Si substrate by heating to a temperature above ['C]; A semiconductor sensor characterized by comprising the steps of removing the '+ part, then covering at least the exposed surface of the Si substrate with an insulating film, and then dicing the base to divide it into individual sensor elements. manufacturing method. (61 Using a 5i substrate as the substrate 4, S1!!
6. The method of manufacturing a semiconductor sensor according to claim 5, wherein the plate is bonded to the Si substrate via an oxide film. (7) Claim 51N, characterized in that an insulator is used as the base! ! A method for manufacturing a semiconductor sensor. (8) The insulating film is SiO2 or SiN. The method for manufacturing a semiconductor sensor according to claim 5, characterized in that S i3N4 , Al1z Os, or Taz Os is used. Applicant's agent Patent attorney Takehiko Suzue

Claims (8)

【特許請求の範囲】[Claims] (1) 表面が平坦な状態に加工された基体と、この基
体上の表面中央部に接着剤を用いることなく接合されセ
ンサ素子が形成されたSi基板と、少なくともこのSi
基板の露出表面を被覆するよう形成された絶縁膜とを具
備してなることを特徴とする半導体センサ。
(1) A base whose surface is processed to be flat, a Si substrate on which a sensor element is formed by bonding to the center of the surface of this base without using an adhesive, and at least this Si substrate.
A semiconductor sensor comprising: an insulating film formed to cover an exposed surface of a substrate.
(2) 前記基体はSi基体であり、前記Si基板は酸
化膜を介して上記Si基体に接合されたものであること
を特徴とする特許請求の範囲第1項記載の半導体センサ
(2) The semiconductor sensor according to claim 1, wherein the base is a Si base, and the Si substrate is bonded to the Si base via an oxide film.
(3) 前記基体は、絶縁体であることを特徴とする特
許請求の範囲第1項記載の半導体センサ。
(3) The semiconductor sensor according to claim 1, wherein the base is an insulator.
(4) 前記絶縁膜は、SiO_2,SiN,Si_3
N_4,Al_2O_3或いはTa_2O_5であるこ
とを特徴とする特許請求の範囲第1項記載の半導体セン
サ。
(4) The insulating film is SiO_2, SiN, Si_3
The semiconductor sensor according to claim 1, characterized in that the semiconductor sensor is N_4, Al_2O_3 or Ta_2O_5.
(5) 表面がそれぞれ平坦な状態にある基体とSi基
板とを清浄な雰囲気中で密着し、この状態で200[℃
]以上に加熱して上記基体及びSi基板を接合する工程
と、次いで上記Si基板に複数のセンサ素子を離間して
形成する工程と、次いで上記センサ素子が形成された領
域以外のSi部分を除去する工程と、次いで少なくとも
Si基板の露出表面を絶縁膜で被覆する工程と、次いで
前記基体をダイシングして個々のセンサ素子に分割する
工程とを含むことを特徴とする半導体センサの製造方法
(5) The substrate and the Si substrate, both of which have flat surfaces, are brought into close contact with each other in a clean atmosphere, and heated to 200°C in this state.
] A step of joining the base body and the Si substrate by heating the above, a step of forming a plurality of sensor elements on the Si substrate in a spaced manner, and then removing a Si portion other than the area where the sensor elements are formed. A method for manufacturing a semiconductor sensor, comprising the steps of: coating at least the exposed surface of the Si substrate with an insulating film; and then dicing the substrate to separate it into individual sensor elements.
(6) 前記基体としてSi基体を用い、前記Si基板
を酸化膜を介して上記Si基体に接合したことを特徴と
する特許請求の範囲第5項記載の半導体センサの製造方
法。
(6) The method of manufacturing a semiconductor sensor according to claim 5, characterized in that a Si substrate is used as the substrate, and the Si substrate is bonded to the Si substrate via an oxide film.
(7) 前記基体として、絶縁体を用いたことを特徴と
する特許請求の範囲第5項記載の半導体センサの製造方
法。
(7) The method for manufacturing a semiconductor sensor according to claim 5, wherein an insulator is used as the base.
(8) 前記絶縁膜として、SiO_2, SiN,S
i_3N_4, Al_2O_3或いはTa_2O_5
を用いたことを特徴とする特許請求の範囲第5項記載の
半導体センサの製造方法。
(8) As the insulating film, SiO_2, SiN, S
i_3N_4, Al_2O_3 or Ta_2O_5
A method for manufacturing a semiconductor sensor according to claim 5, characterized in that the method uses:
JP60033101A 1985-02-20 1985-02-20 Semiconductor sensor and manufacturing method thereof Expired - Lifetime JPH068800B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP60033101A JPH068800B2 (en) 1985-02-20 1985-02-20 Semiconductor sensor and manufacturing method thereof
CA000501835A CA1251514A (en) 1985-02-20 1986-02-14 Ion selective field effect transistor sensor
US06/831,314 US4791465A (en) 1985-02-20 1986-02-20 Field effect transistor type semiconductor sensor and method of manufacturing the same
DE8686301229T DE3681938D1 (en) 1985-02-20 1986-02-20 SEMICONDUCTOR SENSOR AND METHOD FOR THE PRODUCTION THEREOF.
EP86301229A EP0192488B1 (en) 1985-02-20 1986-02-20 Semiconductor sensor and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60033101A JPH068800B2 (en) 1985-02-20 1985-02-20 Semiconductor sensor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS61191955A true JPS61191955A (en) 1986-08-26
JPH068800B2 JPH068800B2 (en) 1994-02-02

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ID=12377272

Family Applications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01250849A (en) * 1988-03-31 1989-10-05 Toshiba Corp Chemical sensor
US5734809A (en) * 1989-02-27 1998-03-31 Ricoh Company, Ltd. Controller for a photocopier providing the ability to transfer data to a replacement controller through communication channels used to control sections of the photocopier

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4638367B2 (en) * 2006-03-15 2011-02-23 立山科学工業株式会社 Gas sensor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57191540A (en) * 1981-05-21 1982-11-25 Nec Corp Semiconductor field effect type ion sensor
JPS59164952A (en) * 1983-03-11 1984-09-18 Hitachi Ltd Fet ion sensor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57191540A (en) * 1981-05-21 1982-11-25 Nec Corp Semiconductor field effect type ion sensor
JPS59164952A (en) * 1983-03-11 1984-09-18 Hitachi Ltd Fet ion sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01250849A (en) * 1988-03-31 1989-10-05 Toshiba Corp Chemical sensor
US5734809A (en) * 1989-02-27 1998-03-31 Ricoh Company, Ltd. Controller for a photocopier providing the ability to transfer data to a replacement controller through communication channels used to control sections of the photocopier

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