JPH07183477A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH07183477A
JPH07183477A JP32359293A JP32359293A JPH07183477A JP H07183477 A JPH07183477 A JP H07183477A JP 32359293 A JP32359293 A JP 32359293A JP 32359293 A JP32359293 A JP 32359293A JP H07183477 A JPH07183477 A JP H07183477A
Authority
JP
Japan
Prior art keywords
substrate
silicon
film
silicon substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32359293A
Other languages
Japanese (ja)
Inventor
Tsukasa Ooka
宰 大岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32359293A priority Critical patent/JPH07183477A/en
Publication of JPH07183477A publication Critical patent/JPH07183477A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form an SOI substrate with a ultrathin film layer readily with good reproducibility by joining a silicon substrate forming a main surface through an insulation film and a supporting substrate and by removing an oxide film after polishing the main surface. CONSTITUTION:A silicon substrate 1 forming a main surface and a silicon substrate 2 which becomes a supporter are joined through an insulation film 3, and thermal treatment is performed at 900 deg.C or higher for at least one hour to realize firm junction between the insulation film 3 and the silicon substrates 1, 2. A surface of the silicon substrate 1 is polished and ground to form a few mum-thick silicon layer 4. The silicon layer 4 is made to remain about 0.1mum thick by thermal oxidation as required. An oxide film is etched and removed by hydrofluoric oxide water solution, etc., and an SOI substrate with a ultrathin film layer 5 is acquired. Thereby, a uniform ultrathin film SOT substrate of extremely good reproducibility of thickness and little crystal defect can be readily acquired.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板、特にSOI
基板の製造方法に関する。
FIELD OF THE INVENTION This invention relates to semiconductor substrates, especially SOI.
The present invention relates to a method for manufacturing a substrate.

【0002】[0002]

【従来の技術】SOI基板の作製法は種々の方法が提案
されている。例えばダイレクトボンディング法(ウェハ
直接貼り合せ)、SIMOX法等が良く知られている。
前者は良好な結晶性を得られるが、薄膜化が難しく後者
は、薄膜化は容易であるが、結晶性が悪いなどの欠点が
あった。これらを改善するための提案がなされている。
すなわち、図2は、特開平2−252265号公報に示
されている方法である。P型シリコン基板11上にN型
薄膜層12をエピタキシャル成長により形成し、支持基
板2と絶縁膜3を介して接合する。P型シリコン基板1
1の一表面を研削研磨して数μm程度の厚さにする。次
に陽極化成法によりP型シリコン基板11を多孔質化し
て、熱酸化でSiO2層に変えエッチング除去して0.
1μm程度のN型薄膜層12を得る。
2. Description of the Related Art Various methods for manufacturing an SOI substrate have been proposed. For example, the direct bonding method (wafer direct bonding), the SIMOX method and the like are well known.
The former can obtain good crystallinity, but it is difficult to form a thin film, and the latter has a defect such as poor crystallinity although it is easy to form a thin film. Suggestions have been made to improve these.
That is, FIG. 2 shows the method disclosed in Japanese Patent Application Laid-Open No. 2-252265. The N-type thin film layer 12 is formed on the P-type silicon substrate 11 by epitaxial growth and bonded to the support substrate 2 via the insulating film 3. P-type silicon substrate 1
One surface of No. 1 is ground and polished to a thickness of about several μm. Next, the P-type silicon substrate 11 is made porous by the anodization method, converted into a SiO2 layer by thermal oxidation, and removed by etching.
An N-type thin film layer 12 of about 1 μm is obtained.

【0003】また図3に酸化膜を研磨のストッパーとし
て用いて形成されたものが特開平1−136328号公
報に示されている。
A structure formed by using an oxide film as a polishing stopper is shown in FIG. 3 of Japanese Patent Laid-Open No. 1-133628.

【0004】[0004]

【発明が解決しようとする課題】これらの従来の薄膜S
OI基板の形成方法では、図2の実施例では、エピタキ
シャル成長による薄膜層のバラツキが大きくなる、エッ
チング除去後のN型薄膜表面の結晶欠陥が多くなる、図
3の実施例ではシリコン層の研磨しすぎによる表面平坦
性が悪くなるなどの問題点があった。
SUMMARY OF THE INVENTION These conventional thin films S
In the method of forming the OI substrate, in the embodiment of FIG. 2, the variation of the thin film layer due to epitaxial growth becomes large, and the crystal defects on the surface of the N-type thin film after etching removal increase, and in the embodiment of FIG. There was a problem that the surface flatness was deteriorated due to excess.

【0005】[0005]

【課題を解決するための手段】本発明の半導体基板の製
造方法は、絶縁膜を介して接合した基板の一主表面を数
μmの厚さが残るまで研削、研磨する工程と、数μmの
厚さのシリコン層を0.1μm程度残すまで酸化膜にす
る熱酸化工程と、酸化膜をエッチング除去する工程とを
有している。
According to the method of manufacturing a semiconductor substrate of the present invention, a process of grinding and polishing one main surface of a substrate bonded via an insulating film until a thickness of several μm remains, and a process of several μm. The method includes a thermal oxidation step of forming an oxide film until a silicon layer having a thickness of about 0.1 μm is left, and a step of etching away the oxide film.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0007】図1は本発明の一実施例のSOI基板の製
法断面図である。同図(a)に示すように、主表面を形
成するシリコン基板1と、支持体となるシリコン基板2
を絶縁膜3を介して接合し、900℃以上、1時間以上
の熱処理を行い、絶縁膜3とシリコン基板1及び2の接
合を強固にする。ここで接合前の絶縁膜3はシリコン基
板1又は2のどちらか一方又は、両方に形成しておく、
次に、図1(b)のようにシリコン基板1の一表面を研
削、研磨して数μmの厚さのシリコン層4にする。従来
の技術では、数μmの残し厚さであれば、精度良く研磨
が可能である。
FIG. 1 is a sectional view of a method for manufacturing an SOI substrate according to an embodiment of the present invention. As shown in FIG. 1A, a silicon substrate 1 forming a main surface and a silicon substrate 2 serving as a support body.
Are bonded via the insulating film 3 and heat treatment is performed at 900 ° C. or higher for 1 hour or longer to strengthen the bond between the insulating film 3 and the silicon substrates 1 and 2. Here, the insulating film 3 before bonding is formed on one or both of the silicon substrates 1 and 2.
Next, as shown in FIG. 1B, one surface of the silicon substrate 1 is ground and polished to form a silicon layer 4 having a thickness of several μm. In the conventional technique, if the remaining thickness is several μm, polishing can be performed with high precision.

【0008】次に、図1(c)のように熱酸化により、
シリコン層4を要求される厚さ0.1μm程度残るよう
にする。数μmの熱酸化による酸化膜形成はバラツキが
少なく、従来のエピタキシャル成長による膜厚制御など
に比べ精度良く行うことができる。ここで酸化前のシリ
コン層4厚さを測定して酸化条件を決定すれば一般と精
度が向上する。シリコン層厚さの測定は、非破壊で容易
に精度良く、測定する方法が一般に知られており、コス
トアップ、工程の複雑化にはならず、非常に有益であ
る。
Next, as shown in FIG. 1 (c), by thermal oxidation,
The silicon layer 4 is left to have a required thickness of about 0.1 μm. There is little variation in the formation of an oxide film by thermal oxidation of several μm, and it can be performed more accurately than in the conventional film thickness control by epitaxial growth. Here, if the thickness of the silicon layer 4 before oxidation is measured to determine the oxidation conditions, generality and accuracy are improved. The measurement of the thickness of the silicon layer is nondestructive, easy and accurate, and a method of measuring the thickness is generally known, which does not increase the cost and complicate the process and is very useful.

【0009】そして、図1(d)のように、酸化膜をフ
ッ化水素酸化水溶液などでエッチング除去して、超薄膜
層5を有するSOI基板を得ることができる。なお、本
製造方法によれば、N型、P型どちらの超薄膜層でも形
成することが可能である。
Then, as shown in FIG. 1D, the oxide film can be removed by etching with an aqueous solution of hydrogen fluoride oxide to obtain an SOI substrate having an ultrathin film layer 5. According to this manufacturing method, it is possible to form an N-type or P-type ultrathin film layer.

【0010】[0010]

【発明の効果】以上説明したように本発明は、SOI基
板の一表面を数μmまで研磨し、酸化工程しつのみで、
シリコン薄膜層を形成し、酸化膜除去して、0.1μm
程度の超薄膜層を形成できる。上記製造方法によれば、
均一で極めて厚さの再現性が良い。結晶欠陥の少ない超
薄膜SOI基板を容易に得ることができる。
As described above, according to the present invention, one surface of the SOI substrate is polished to several μm and only the oxidation process is performed.
Forming a silicon thin film layer, removing oxide film, 0.1μm
It is possible to form a very thin film layer. According to the above manufacturing method,
Uniform and extremely good thickness reproducibility. An ultra-thin film SOI substrate with few crystal defects can be easily obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によるSOI基板の製造方法
の実施例を示す工程図。
FIG. 1 is a process drawing showing an embodiment of a method for manufacturing an SOI substrate according to an embodiment of the present invention.

【図2】従来のSOI基板の製造方法を示す工程図。FIG. 2 is a process drawing showing a conventional method for manufacturing an SOI substrate.

【図3】従来の他の製造方法による実施例の断面図。FIG. 3 is a sectional view of an example according to another conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 支持体シリコン基板 3 絶縁膜 4 シリコン層 5 超薄膜シリコン層 6 酸化膜 11 P型シリコン基板 12 N型薄膜層 13 P型シリコン層 21 超薄膜シリコン層 22 ストッパー酸化膜 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Supporting silicon substrate 3 Insulating film 4 Silicon layer 5 Ultra thin silicon layer 6 Oxide film 11 P type silicon substrate 12 N type thin film layer 13 P type silicon layer 21 Ultra thin silicon layer 22 Stopper oxide film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/316 S 7352−4M 21/762 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/316 S 7352-4M 21/762

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1のシリコン基板と第2のシリコン基
板とを絶縁膜を介して接合する工程と、前記第1のシリ
コン基板の一主表面を研磨する工程と、前記形成した複
合基板を酸化し、酸化膜を除去する工程とを有すること
を特徴とする半導体基板の製造方法。
1. A step of joining a first silicon substrate and a second silicon substrate via an insulating film, a step of polishing one main surface of the first silicon substrate, and the formed composite substrate And a step of removing the oxide film, the method of manufacturing a semiconductor substrate.
JP32359293A 1993-12-22 1993-12-22 Manufacture of semiconductor substrate Pending JPH07183477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32359293A JPH07183477A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32359293A JPH07183477A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH07183477A true JPH07183477A (en) 1995-07-21

Family

ID=18156430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32359293A Pending JPH07183477A (en) 1993-12-22 1993-12-22 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH07183477A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000024059A1 (en) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method
WO2000062343A1 (en) * 1999-04-09 2000-10-19 Shin-Etsu Handotai Co., Ltd. Soi wafer and method for producing soi wafer
JP2003510799A (en) * 1999-08-20 2003-03-18 エス オー イ テク シリコン オン インシュレータ テクノロジース Microelectronics substrate processing method and substrate obtained by the method
JP2005005674A (en) * 2003-05-21 2005-01-06 Canon Inc Method of manufacturing substrate and substrate treatment apparatus
US7256104B2 (en) 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
JP2009158918A (en) * 2007-09-24 2009-07-16 Applied Materials Inc Method for improving oxide growth rate of selective oxidation process
KR20110137806A (en) * 2009-04-21 2011-12-23 에스오아이테크 실리콘 온 인슐레이터 테크놀로지스 Method to thin a silicon-on-insulator substrate
JP2018121070A (en) * 2018-03-23 2018-08-02 富士通セミコンダクター株式会社 Method of manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03109731A (en) * 1989-09-25 1991-05-09 Seiko Instr Inc Manufacture of semiconductor substrate
JPH03250617A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Manufacture of bonded wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03109731A (en) * 1989-09-25 1991-05-09 Seiko Instr Inc Manufacture of semiconductor substrate
JPH03250617A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Manufacture of bonded wafer

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372609B1 (en) 1998-10-16 2002-04-16 Shin-Etsu Handotai Co., Ltd. Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method
WO2000024059A1 (en) * 1998-10-16 2000-04-27 Shin-Etsu Handotai Co., Ltd. Method of producing soi wafer by hydrogen ion implanting separation method and soi wafer produced by the method
KR100688629B1 (en) * 1999-04-09 2007-03-09 신에쯔 한도타이 가부시키가이샤 Soi wafer and method for producing soi wafer
US6461939B1 (en) 1999-04-09 2002-10-08 Shin-Etsu Handotai Co., Ltd. SOI wafers and methods for producing SOI wafer
WO2000062343A1 (en) * 1999-04-09 2000-10-19 Shin-Etsu Handotai Co., Ltd. Soi wafer and method for producing soi wafer
EP2413352A3 (en) * 1999-04-09 2012-03-07 Shin-Etsu Handotai Co., Ltd. Soi wafer and method for producing soi wafer
JP2003510799A (en) * 1999-08-20 2003-03-18 エス オー イ テク シリコン オン インシュレータ テクノロジース Microelectronics substrate processing method and substrate obtained by the method
JP2005005674A (en) * 2003-05-21 2005-01-06 Canon Inc Method of manufacturing substrate and substrate treatment apparatus
US7256104B2 (en) 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
JP2009158918A (en) * 2007-09-24 2009-07-16 Applied Materials Inc Method for improving oxide growth rate of selective oxidation process
KR20110137806A (en) * 2009-04-21 2011-12-23 에스오아이테크 실리콘 온 인슐레이터 테크놀로지스 Method to thin a silicon-on-insulator substrate
JP2012524420A (en) * 2009-04-21 2012-10-11 ソイテック Method for thinning a silicon-on-insulator substrate
JP2018121070A (en) * 2018-03-23 2018-08-02 富士通セミコンダクター株式会社 Method of manufacturing semiconductor device

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