JPS61177054A - Receiving circuit of phase modulating signal - Google Patents

Receiving circuit of phase modulating signal

Info

Publication number
JPS61177054A
JPS61177054A JP60017484A JP1748485A JPS61177054A JP S61177054 A JPS61177054 A JP S61177054A JP 60017484 A JP60017484 A JP 60017484A JP 1748485 A JP1748485 A JP 1748485A JP S61177054 A JPS61177054 A JP S61177054A
Authority
JP
Japan
Prior art keywords
frequency
signal
phase
circuit
psk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60017484A
Other languages
Japanese (ja)
Inventor
Akiyuki Yoshisato
善里 彰之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP60017484A priority Critical patent/JPS61177054A/en
Publication of JPS61177054A publication Critical patent/JPS61177054A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2272Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To reduce beat interruption and to reduce the number of oscillators by multiplying the frequency of an intermediate frequency signal N times to use the multiplied signal as an oscillation signal from a fixed station part and then dividing the N-multiplied frequency by N to use the N-divided signal as a reference carrier to be applied to a phase detector. CONSTITUTION:In a PSK receiving circuit 40, a frequency multiplier 41 multiplies the frequency of the 2nd intermediate frequency signal by N and applies the N-multiplied signal to a PLL circuit 42 as a reference frequency. When a modulation signal is M phases, the multiplier 41 multiplies the frequency by N which is integer times of M. A part of the output signal of the circuit 42 is divided by N by a frequency divider 46 and the N-divided signal is applied to a phase detector 8 as a reference carrier. Consequently, the phase of N-times frequency of said frequency is not influenced by PSK-modulated phase information. Since the signal is divided by N by the frequency divider 46, the reference carrier having the same frequency as that of the 2nd intermediate frequency signal and controlled at a fixed phase is outputted.

Description

【発明の詳細な説明】 (産業上の利用分野) 、本発明は、位相変調された受信信号を固定局部発振信
号を用いて中間周波信号に変換し、この中間周波信号を
基準搬送波が与えられる位相検波器で位相復調するため
の位相変調信号の受信回路に関するものである。
Detailed Description of the Invention (Industrial Application Field) The present invention converts a phase-modulated received signal into an intermediate frequency signal using a fixed local oscillation signal, and this intermediate frequency signal is given a reference carrier wave. The present invention relates to a receiving circuit for a phase modulated signal for phase demodulation using a phase detector.

(従来の技術) 近年、超短波およびマイクロ波等の搬送波を用いてディ
ジタル信号を伝送する場合、周波数帯域を有効に使用で
きる高能率変調方式として、PSK (Page 5h
ift Keying )方式やQAM (直交振幅変
調)方式等の位相変調方式が研究実用化されている。一
方、衛星通信や衛星放送およびCATV等にあっては1
画像や音声の高品質化のために信号のディジタル化がな
されると同時に、信号を低いビットレートに圧縮して、
伝送に必要とする周波数帯域幅を圧縮する研究がなされ
ている。そこで、−例として、20Mb/sの低いビッ
トレートまで圧縮されたカラーテレビジョン信号を、1
6相PSK方式または16値QAM方式で伝送するなら
ば、従来のアナログ伝送で必要とされるテレビジョン放
送の1チャンネル分の6 Mn2の周波数帯域幅で伝送
することが可能となる。よって、ディジタル化されたカ
ラーテレビジョン信号が、従来のアナログ信号によるカ
ラーテレビジョン信号と同様のチャンネル密度で伝送で
き、CATV等で実用的に極めて有益である。
(Prior art) In recent years, when transmitting digital signals using carrier waves such as very short waves and microwaves, PSK (Page 5h
Phase modulation methods such as the QAM (Quadrature Amplitude Modulation) method and the QAM (Quadrature Amplitude Modulation) method have been researched and put into practical use. On the other hand, for satellite communications, satellite broadcasting, CATV, etc.
At the same time that signals are digitized to improve the quality of images and audio, they are compressed to a lower bit rate,
Research is being conducted to compress the frequency bandwidth required for transmission. Therefore, - As an example, if a color television signal compressed to a low bit rate of 20 Mb/s is
If it is transmitted using the 6-phase PSK method or the 16-value QAM method, it becomes possible to transmit with a frequency bandwidth of 6 Mn2, which is equivalent to one channel of television broadcasting, which is required in conventional analog transmission. Therefore, digitized color television signals can be transmitted with the same channel density as conventional analog color television signals, which is extremely useful for CATV and the like.

ここで、位相変調されたカラーテレビジョン信号を位相
復調するための位相変調信号の受信回路を、CATVコ
ンバータにPSK方式で応用した従来のPSK受信回路
のブロック回路図を第2図に示す、第2図に示すものは
、PSK変調された50〜550 M)+2の受信信号
からダブルス−パーヘテロゲイン方式で中間周波信号を
生成し、この中間周波信号よりPSKf4I調回路でP
SK復調するように構成されたものである0図において
、PSK受信回路lは、CATV信号が第1の混合器2
に与えられ、受信すべきチャンネルに応じて可変調整さ
れる可変局部発振器3から与えられる可変局部発振信号
と混合され、バンドパスフィルタ4により650 Mn
2の第1の中間周波信号が抽出される。この第1の中間
周波信号は、第2の混合器5に与えられ、固定局部発振
器6から与えられる固定局部発振信号と混合され、45
MH2の第2の中間周波信号が生成される。この第2の
中間周波信号は、IF増幅器7で増幅され位相検波器8
に与えられて、キャリア再生回路9から与えられる基準
搬送波により位相情報に変換される。さらに、この位相
情報は、識別器10に与えられ、クロック同期回路11
から与えられるクロック信号により正しいタイミングで
識別され、ディジタル信号に変換されてディジタル信号
処理回路12に与えられる。そして、このディジタル信
号処理回路12によりアナログ信号のカラーテレビジョ
ン信号に復調される。
Here, a block circuit diagram of a conventional PSK receiving circuit in which a phase modulated signal receiving circuit for phase demodulating a phase modulated color television signal is applied to a CATV converter using the PSK method is shown in FIG. The system shown in Figure 2 generates an intermediate frequency signal from a PSK modulated 50 to 550 M)+2 received signal using the double superhetero gain method, and uses the PSKf4I modulation circuit to generate an intermediate frequency signal from this intermediate frequency signal.
In FIG.
is mixed with a variable local oscillation signal provided from a variable local oscillator 3 that is variably adjusted depending on the channel to be received, and is mixed with a variable local oscillation signal provided from a variable local oscillator 3 that is variably adjusted depending on the channel to be received.
Two first intermediate frequency signals are extracted. This first intermediate frequency signal is applied to a second mixer 5 and mixed with a fixed local oscillation signal applied from a fixed local oscillator 6.
A second intermediate frequency signal of MH2 is generated. This second intermediate frequency signal is amplified by an IF amplifier 7 and a phase detector 8
is converted into phase information by the reference carrier wave provided from the carrier regeneration circuit 9. Furthermore, this phase information is given to the discriminator 10, and the clock synchronization circuit 11
The signal is identified at the correct timing by the clock signal provided from the , and is converted into a digital signal and provided to the digital signal processing circuit 12 . The digital signal processing circuit 12 demodulates the signal into an analog color television signal.

ここで、位相検波器8とキャリア再生回路9と識別器1
0およびクロック同期回路11等から構成されるPSK
復調回路13は、公知の技術であって、各種の方式が知
られており、詳細な説明は省略するが、本発明に関連す
るキャリア再生回路9につき第3図および第4図を参照
してその構造を簡単に説明する。第3図は、ベースバン
ド処理形(コスタス形)の4相PSK信号のキャリア再
生回路9のブロック回路図であり、4相PSKの位相検
波器8から2つの位相情報が出力され、この2つの位相
情報は、それぞれ加算回路21と減算回路22に与えら
れ、これらの加算回路21と減算回路22の出力は、第
1の排他オア回路23に与えられる。また、位相検波器
8の2つの位相情報は、第2の排他オア回路24に与え
られ、このJ$2の排他オア回路24と第1の排他オア
回路23の出力が、第3の排他オア回路25に与えられ
る。この第3の排他オア回路25cr+出力は、ローパ
スフィルタ2Bで高調波成分が除かれて電圧制御発振器
(■C0)27に与えられる。そして、この電圧制御発
振器27から第2の中間周波信号の周波数と同じ周波数
でかつ一定の位相に制御された基準搬送波が出力されて
、位相検波器8に与えられるように構成されている。
Here, the phase detector 8, the carrier regeneration circuit 9, and the discriminator 1
PSK consisting of 0 and clock synchronization circuit 11, etc.
The demodulation circuit 13 is a well-known technique, and various systems are known.Detailed explanation is omitted, but please refer to FIGS. 3 and 4 for the carrier regeneration circuit 9 related to the present invention. Its structure will be briefly explained. FIG. 3 is a block circuit diagram of a baseband processing type (Costas type) four-phase PSK signal carrier recovery circuit 9. Two phase information is output from the four-phase PSK phase detector 8, and these two phase information are output from the four-phase PSK phase detector 8. The phase information is provided to an addition circuit 21 and a subtraction circuit 22, respectively, and the outputs of these addition circuits 21 and subtraction circuits 22 are provided to a first exclusive OR circuit 23. Further, the two phase information of the phase detector 8 is given to the second exclusive OR circuit 24, and the outputs of the J$2 exclusive OR circuit 24 and the first exclusive OR circuit 23 are input to the third exclusive OR circuit 24. is applied to circuit 25. The output of the third exclusive OR circuit 25cr+ is supplied to the voltage controlled oscillator (C0) 27 after the harmonic components are removed by the low pass filter 2B. The voltage controlled oscillator 27 outputs a reference carrier wave having the same frequency as the second intermediate frequency signal and controlled to have a constant phase, and is provided to the phase detector 8.

また、第4図は、周波数逓倍形の4相PSK@号のキャ
リア再生回路9のブロック回路図であり、位相検波器8
に与えられる第2の中間周波信号の周波数が4逓倍回路
31により周波数逓倍されて4倍の周波数の信号に変換
される。この4倍の周波数の信号の位相は、PSK変調
されている位相情報により影響されない、そして、この
4逓倍回路31の出力信号の周波数を、位相検波器32
とローパスフィルタ33および電圧制御発振器34から
なるPL、L回路の基準周波数として、電圧制御発振器
34゛から一定の位相に制御された4倍の周波数を出力
させる。さらに、この4倍の周波数を4分周器35で分
周して、第2の中間周波信号と同じ周波数で、かつ一定
の位相に制御された基準搬送波が出力されて、位相検波
器8に与えられるように構成されている。
Further, FIG. 4 is a block circuit diagram of the carrier regeneration circuit 9 of the frequency multiplication type 4-phase PSK @ signal, and the phase detector 8
The frequency of the second intermediate frequency signal given to the second intermediate frequency signal is frequency-multiplied by the quadrupling circuit 31 and converted into a signal of four times the frequency. The phase of this quadrupled frequency signal is not affected by the PSK modulated phase information, and the frequency of the output signal of this quadrupling circuit 31 is detected by
As the reference frequency of the PL and L circuits consisting of the low-pass filter 33 and the voltage-controlled oscillator 34, the voltage-controlled oscillator 34' outputs a quadrupled frequency controlled to have a constant phase. Furthermore, this four-times frequency is divided by a 4-frequency divider 35, and a reference carrier wave having the same frequency as the second intermediate frequency signal and controlled to a constant phase is outputted to the phase detector 8. It is configured to be given.

(発明が解決しようとする問題点) 上記した従来のPSK受信回路lにあっては、受信信号
から中間周波信号を生成するための可変局部発振器3と
固定局部発振器6およびPSK復調のためのキャリア再
生回路9の発振器とがそれぞれに必要である。そして、
これらの発振器から出力される周波数は、整数倍の関係
等にはないために、相互の高調波成分によりビート妨害
が生じ易い、また、従来のダブルスーパーヘテログイン
方式によるアナログ伝送に比して、PSK復調のための
発振器が1つ多くなり、より一部ビート妨害の対策が困
難である。さらに、PSK復調のための発振器が1つ多
くなるので、その分だけ製造コストが高くなるとともに
、大型化するという問題点がある。
(Problems to be Solved by the Invention) The conventional PSK receiving circuit l described above includes a variable local oscillator 3 for generating an intermediate frequency signal from a received signal, a fixed local oscillator 6, and a carrier for PSK demodulation. An oscillator of the reproduction circuit 9 is required for each. and,
Since the frequencies output from these oscillators are not in an integer multiple relationship, beat interference is likely to occur due to mutual harmonic components.Also, compared to analog transmission using the conventional double super heterolog system, The number of oscillators for PSK demodulation increases by one, making it more difficult to take measures against some beat disturbances. Furthermore, since the number of oscillators for PSK demodulation increases by one, there are problems in that the manufacturing cost increases and the size increases accordingly.

本発明の目的は、上記した従来の位相変調信号の受信回
路の問題点を解消すべくなされたもので、中間周波信号
の周波数をN逓倍して固定局部発振信号として用い、さ
らに、このN逓倍された周波数をN分周して位相検波器
に与えられる基準搬送波として用いることにより、基準
搬送波の周波数に対して固定局部発振信号等の周波数を
整数倍の関係として、ビート妨害の発生を軽減させると
ともに、発振器の個数を減少させるようにして安価に製
造できるようにした位相変調信号の受信回路を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the conventional phase modulation signal receiving circuit described above. By dividing the obtained frequency by N and using it as a reference carrier wave given to a phase detector, the frequency of a fixed local oscillation signal, etc. is set as an integral multiple of the frequency of the reference carrier wave, thereby reducing the occurrence of beat interference. Another object of the present invention is to provide a phase modulation signal receiving circuit that can be manufactured at low cost by reducing the number of oscillators.

(問題を解決するための手段) かかる目的を達成す°るために、本発明の位相変調信号
の受信回路は、位相変調された受信信号を混合器で固定
局部発振信号と混合して中間周波信号を生成し、この中
間周波信号を位相検波器で位相復調する位相変調信号の
受信回路において、前記中間周波信号の周波数をN逓倍
する周波数逓倍器と、この周波数逓倍器の出力信号の周
波数を基準周波数とするPLL回路と、このPLI、回
路の出力信号の周波数をN分周する分周器と、を設け、
前記PLL回路の出力信号を前記混合器に与えられる固
定局部発振信号とするとともに、前記分周器の出力信号
を前記位相検波器に与えられる基準搬送波とするように
構成されている。
(Means for Solving the Problem) In order to achieve the above object, the phase modulated signal receiving circuit of the present invention mixes the phase modulated received signal with a fixed local oscillation signal in a mixer to generate an intermediate frequency signal. A phase modulation signal receiving circuit that generates a signal and demodulates the phase of this intermediate frequency signal using a phase detector includes a frequency multiplier that multiplies the frequency of the intermediate frequency signal by N, and a frequency multiplier that multiplies the frequency of the output signal of the frequency multiplier. A PLL circuit that uses a reference frequency, and a frequency divider that divides the frequency of the output signal of the PLI and the circuit by N,
The output signal of the PLL circuit is used as a fixed local oscillation signal applied to the mixer, and the output signal of the frequency divider is used as a reference carrier wave applied to the phase detector.

(作用) 中間周波信号の周波数をN逓倍して固定局部発振信号と
して用い、さらに、このN逓倍された周波数をN分周し
て位相検波器に与えられる基準搬送波として用いるので
、混合器から出力される中間周波信号および基準搬送波
の周波数に対して、固定局部発振信号の周波数が整数倍
の関係にあり、これらの周波数の相互の高調波成分によ
るビート妨害を軽減することができ、ビート妨害対策が
容易である。また、固定局部発振器を必要としないので
、それだけ安価に製造できるとともに、小型化が容易で
ある。
(Function) The frequency of the intermediate frequency signal is multiplied by N and used as a fixed local oscillation signal, and this N-multiplied frequency is further divided by N and used as the reference carrier wave given to the phase detector, so the output from the mixer is The frequency of the fixed local oscillation signal is an integer multiple of the frequency of the intermediate frequency signal and reference carrier wave, which makes it possible to reduce beat interference due to mutual harmonic components of these frequencies. is easy. Furthermore, since a fixed local oscillator is not required, it can be manufactured at a lower cost and can be easily miniaturized.

(実施例の説明) 以下、本発明の位相変調信号の受信回路の実施例を第1
図を参照して説明する。第1図は、本発明の位相変調信
号の受信回路をCATVコンバータにPSK方式で応用
したPSK受信回路の一実施例のブロック回路図である
。第1図において、第2図と同一の回路には、同一の符
号を付して、重複する説明を省略する。
(Description of Embodiments) Hereinafter, a first embodiment of the phase modulation signal receiving circuit of the present invention will be described.
This will be explained with reference to the figures. FIG. 1 is a block circuit diagram of an embodiment of a PSK receiving circuit in which the phase modulated signal receiving circuit of the present invention is applied to a CATV converter using the PSK method. In FIG. 1, circuits that are the same as those in FIG. 2 are designated by the same reference numerals, and redundant explanation will be omitted.

第1図において、本発明に係わるPSK受信回路40は
、IF増幅器7からの第2の中間周波信号の周波数を周
波数逓倍器41でN逓倍し、この周波数逓倍器41の出
力信号の周波数がPLL回路42に基準周波数として与
えられる。ここで、周波数逓倍器41は、PSK変調信
号がM相であれば、IF増幅器7からの第2の中間周波
信号の周波数をMの整数倍のN逓倍する。なお、PLL
回路42は公知のごとく、位相検波器43とローパスフ
ィルタ44および電圧制御発振器45から構成されてい
る。そして、このPLL回路42の出力信号が固定局部
発振信号として第2の混合器5に与えられている。
In FIG. 1, the PSK receiving circuit 40 according to the present invention multiplies the frequency of the second intermediate frequency signal from the IF amplifier 7 by N in a frequency multiplier 41, and the frequency of the output signal of the frequency multiplier 41 is set to PLL. It is applied to circuit 42 as a reference frequency. Here, if the PSK modulation signal is M-phase, the frequency multiplier 41 multiplies the frequency of the second intermediate frequency signal from the IF amplifier 7 by N, which is an integral multiple of M. In addition, PLL
As is well known, the circuit 42 includes a phase detector 43, a low-pass filter 44, and a voltage controlled oscillator 45. The output signal of this PLL circuit 42 is given to the second mixer 5 as a fixed local oscillation signal.

さらに、このPLL回路42の出力信号の一部は、分周
器46によりN分周されて、位相検波器8に基準搬送波
として与えられている。
Furthermore, a part of the output signal of this PLL circuit 42 is frequency-divided by N by a frequency divider 46 and is given to the phase detector 8 as a reference carrier wave.

かかる構成において、M相のPSK変調されている第2
の中間周波信号の周波数が、周波数逓倍器41によりM
相の整数倍のN逓倍されるために、周波数逓倍器41の
出力信号の周波数であるN倍の周波数の位相は、PSK
変調されている位相情報により影響されることがない、
そして、この周波数逓倍器41の出力信号の周波数を分
周器4BでN分周することにより、第2の中間周波信号
と同じ周波数で、かつ一定の位相に制御された基準搬送
波が出力される。この基準搬送波が位相検波器8に与え
らて、PSK変調信号が復調される。
In such a configuration, the M-phase PSK modulated second
The frequency of the intermediate frequency signal is changed to M by the frequency multiplier 41.
Since the phase is multiplied by an integral number N, the phase of the frequency N times the frequency of the output signal of the frequency multiplier 41 is PSK
unaffected by the phase information being modulated,
Then, by dividing the frequency of the output signal of the frequency multiplier 41 by N by the frequency divider 4B, a reference carrier wave having the same frequency as the second intermediate frequency signal and controlled to have a constant phase is output. . This reference carrier wave is applied to the phase detector 8, and the PSK modulated signal is demodulated.

ところで、PSK受ゼ受路回路40ける第1の中。By the way, the first part of the PSK receiver circuit 40.

間周波信号や第2の中間周波信号の周波数は、50〜5
50MH2(7)CATV信号(7)帯域ニオイテ、イ
メージ妨害やビート妨害の生じない適宜な値に選定され
ていればよく、第1および第2の中間周波信号の周波数
を、第2図で説明したごと5650 MB2および45
 MB2からそれぞれ数拾MH2程度だけ変更して選定
することもできる。
The frequency of the intermediate frequency signal and the second intermediate frequency signal is 50 to 5.
50MH2 (7) CATV signal (7) The frequency of the first and second intermediate frequency signals may be selected as appropriate values that do not cause image interference or beat interference. 5650 MB per 2 and 45
It is also possible to select by changing from MB2 by about several dozen MH2.

そこで、例えば、16相PSK変調方式において、第2
の混合器5で生成する第2の中間周波信号の周波数を4
3MH2に設定すれば、この周波数を周波数逓倍器41
で16倍に逓倍して688 MB2の周波数に変換する
。さらに、この688 MB2の周波数をPLL回路4
2より固定局部発振信号として第2の混合器5に与える
。そして、第1の中間周波信号の周波数を、固定局部発
振信号の周波数として選定された6 88 MB2から
、第2の中間周波信号の周波数として選定された43M
H2だけ差を設けられた6 45 MB2に選定する。
Therefore, for example, in the 16-phase PSK modulation method, the second
The frequency of the second intermediate frequency signal generated by the mixer 5 is set to 4.
If set to 3MH2, this frequency will be transmitted to the frequency multiplier 41.
The frequency is multiplied by 16 times and converted to a frequency of 688 MB2. Furthermore, the frequency of this 688 MB2 is changed to the PLL circuit 4.
2 to the second mixer 5 as a fixed local oscillation signal. Then, the frequency of the first intermediate frequency signal is changed from 688 MB2, which is selected as the frequency of the fixed local oscillation signal, to 43M, which is selected as the frequency of the second intermediate frequency signal.
645 MB2 with a difference of H2 is selected.

さらに、固定局部発振信号の周波数を、分周器48で1
6分周して43 MB2の基準搬送波に変換し1位相検
波器8に与える。このようにして選定された第1と第2
の中間周波信号の周波数および固定局部発振信号の周波
数は、第2図で説明したそれぞれの周波数と、はぼ同様
の関係となり、イメージ妨害やビート妨害を格別に生じ
させる値でない。
Furthermore, the frequency of the fixed local oscillation signal is divided into 1 by a frequency divider 48.
The frequency is divided by 6, converted into a 43 MB2 reference carrier wave, and applied to the 1-phase detector 8. The first and second selected in this way
The frequency of the intermediate frequency signal and the frequency of the fixed local oscillation signal have approximately the same relationship as the respective frequencies explained in FIG. 2, and do not have values that cause particular image disturbance or beat disturbance.

したがって、第2の中間周波信号および基準搬送波の周
波数に対して、固定局部発振信号の周波数が整数倍の関
係にあり、さらに、第1の中間周波信号の周波数が、第
2の中間周波信号の周波数に対して整数倍の関係にあり
、ビート妨害の発生が軽減され、その対策が容易である
。また、固定局部発振信号を発生させるための固定局部
発振器が不要となり、それだけ安価に製造できるととも
に、小型化が容易である。
Therefore, the frequency of the fixed local oscillation signal is an integral multiple of the frequency of the second intermediate frequency signal and the reference carrier wave, and furthermore, the frequency of the first intermediate frequency signal is the same as that of the second intermediate frequency signal. It is an integral multiple of the frequency, so the occurrence of beat disturbance is reduced and countermeasures against it are easy. Further, a fixed local oscillator for generating a fixed local oscillation signal is not required, which makes manufacturing cheaper and easier to downsize.

なお、上記説明では、CATVコンバータにPSK方式
で応用したPSK受信回路を一例として説明したが、こ
れに限られることなく、衛星通信および衛星放送等の固
定局部発振器を用いて周波数変換する信号受信装置に使
用してもよく、また位相変調方式としては、8相PSK
や16相PSKおよび32相PSK、さらには16値Q
AMや256値QAMの変調方式が用いられていてもよ
いことは勿論である。
In the above explanation, the PSK receiving circuit applied to a CATV converter using the PSK method was explained as an example, but the present invention is not limited to this, and signal receiving devices that convert frequencies using fixed local oscillators for satellite communication and satellite broadcasting etc. It may also be used for 8-phase PSK as a phase modulation method.
16-phase PSK, 32-phase PSK, and 16-level Q
Of course, AM or 256-value QAM modulation methods may also be used.

(発明の効果) 以上説明したように、本発明に係わる位相変調信号の受
信回路は、中間周波信号の周波数をN逓倍して固定局部
発振信号として用い、さらに、このN逓倍された周波数
をN分周して位相検波器に与えられる基準搬送波として
用いるので、混合器から出力される中間周波信号および
基準搬送波の周波数に対して、固定局部発振信号の周波
数が整数倍の関係にあり、これらの周波数の相互の高調
波成分によるビート妨害を軽減することができ、ビート
妨害対策が容易である。また、固定局部発振器を必要と
しないので、それだけ安価に製造できるとともに、小型
化が容易である等の優れた効果を奏する。
(Effects of the Invention) As explained above, the phase modulation signal receiving circuit according to the present invention multiplies the frequency of an intermediate frequency signal by N and uses it as a fixed local oscillation signal, and further uses the N-multiplied frequency by N. Since the frequency of the fixed local oscillation signal is divided and used as the reference carrier wave given to the phase detector, the frequency of the fixed local oscillation signal is an integral multiple of the frequency of the intermediate frequency signal and reference carrier wave output from the mixer. Beat interference due to mutual harmonic components of frequencies can be reduced, and measures against beat interference are easy. Further, since a fixed local oscillator is not required, it can be manufactured at a correspondingly low cost and has excellent effects such as easy miniaturization.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の位相変調信号の受信回路をCATV
コンバータにPSK方式で応用したPSK受信回路の一
実施例のブロック回路図であり、第2図は、CATVコ
ンバータにPSK方式で応用した従来のPSK受信回路
のブロック回路図であり、第3図は、ベースバンド処理
形の4相PSK信号のキャリア再生回路のブロック回路
図であり、第4図は1周波数逓倍形の4相PSK信号の
キャリア再生回路のブロー、り回路図である。 1.40:PSK受信回路、5:第2の混合器、8:位
相検波器、41=周波数逓倍器、42:PLL回路、4
8:分周器。
FIG. 1 shows a phase modulation signal receiving circuit of the present invention in a CATV system.
FIG. 2 is a block circuit diagram of an embodiment of a PSK receiving circuit applied to a converter using the PSK method. FIG. 2 is a block circuit diagram of a conventional PSK receiving circuit applied to a CATV converter using the PSK method. FIG. 4 is a block circuit diagram of a carrier regeneration circuit for a four-phase PSK signal of baseband processing type, and FIG. 4 is a block circuit diagram of a carrier regeneration circuit for a one-frequency multiplication type four-phase PSK signal. 1.40: PSK receiving circuit, 5: second mixer, 8: phase detector, 41 = frequency multiplier, 42: PLL circuit, 4
8: Frequency divider.

Claims (1)

【特許請求の範囲】[Claims] 位相変調された受信信号を混合器で固定局部発振信号と
混合して中間周波信号を生成し、この中間周波信号を位
相検波器で位相復調する位相変調信号の受信回路におい
て、前記中間周波信号の周波数をN逓倍する周波数逓倍
器と、この周波数逓倍器の出力信号の周波数を基準周波
数とするPLL回路と、このPLL回路の出力信号の周
波数をN分周する分周器と、を設け、前記PLL回路の
出力信号を前記混合器に与えられる固定局部発振信号と
するとともに、前記分周器の出力信号を前記位相検波器
に与えられる基準搬送波とすることを特徴とした位相変
調信号の受信回路。
In a phase modulated signal receiving circuit that mixes a phase modulated received signal with a fixed local oscillation signal in a mixer to generate an intermediate frequency signal, and phase demodulates this intermediate frequency signal in a phase detector, A frequency multiplier that multiplies the frequency by N, a PLL circuit that uses the frequency of the output signal of this frequency multiplier as a reference frequency, and a frequency divider that divides the frequency of the output signal of this PLL circuit by N, A receiving circuit for a phase modulated signal, characterized in that the output signal of the PLL circuit is used as a fixed local oscillation signal given to the mixer, and the output signal of the frequency divider is used as a reference carrier given to the phase detector. .
JP60017484A 1985-01-31 1985-01-31 Receiving circuit of phase modulating signal Pending JPS61177054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60017484A JPS61177054A (en) 1985-01-31 1985-01-31 Receiving circuit of phase modulating signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60017484A JPS61177054A (en) 1985-01-31 1985-01-31 Receiving circuit of phase modulating signal

Publications (1)

Publication Number Publication Date
JPS61177054A true JPS61177054A (en) 1986-08-08

Family

ID=11945273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60017484A Pending JPS61177054A (en) 1985-01-31 1985-01-31 Receiving circuit of phase modulating signal

Country Status (1)

Country Link
JP (1) JPS61177054A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187935A (en) * 1987-01-30 1988-08-03 Sharp Corp Pll circuit
EP0345515A2 (en) * 1988-06-07 1989-12-13 Robert Bosch Gmbh Method for carrier recovery

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177058A (en) * 1974-12-27 1976-07-03 Fujitsu Ltd
JPS55132164A (en) * 1979-03-30 1980-10-14 Nec Corp Carrier regenerating circuit for psk demodulator
JPS55134532A (en) * 1979-04-02 1980-10-20 Siemens Ag High frequency electromagnetic wave reciever with frequency control circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177058A (en) * 1974-12-27 1976-07-03 Fujitsu Ltd
JPS55132164A (en) * 1979-03-30 1980-10-14 Nec Corp Carrier regenerating circuit for psk demodulator
JPS55134532A (en) * 1979-04-02 1980-10-20 Siemens Ag High frequency electromagnetic wave reciever with frequency control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187935A (en) * 1987-01-30 1988-08-03 Sharp Corp Pll circuit
EP0345515A2 (en) * 1988-06-07 1989-12-13 Robert Bosch Gmbh Method for carrier recovery

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