JPH06204971A - Spread spectrum modulation and/or demodulation device - Google Patents

Abstract

PURPOSE:To simplify constitution and to stabilize operations by providing an angle modulation means, a frequency multiplying means, a frequency divider means and a spreading code generation means, spread-modulating a multiplication angle modulated wave by an obtained spreading code and outputting it. CONSTITUTION:Information signals are supplied from an input terminal In 1 to an angle modulation circuit 52 and frequency modulation being primary modulation is performed. Frequency modulated signals are supplied to a frequency multiplier 53 and a carrier frequency f0 and frequency shift are multiplied by N1 to be supplied to a multiplier 6 for spread modulation. In the meantime, the frequency modulated signals are also supplied to a frequency divider 28, a basic carrier frequency becomes f0/N2 and the frequency shift becomes DELTAf/N2. Frequency divided output signals are supplied to the spreading code generator PNG 48 as clock signals with the frequency Fc and the spreading codes are generated based on the clock signals. The spreading codes are supplied through an LPF 31 to the multiplier 6, spectrum spreading by multiplication with frequency modulated waves is performed and output is performed from a transmission antenna A1 through an amplifier 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SS modulator in a transmitter, an SS demodulator in a receiver, or an SS modulator / demodulator in a transceiver used for spread spectrum (hereinafter referred to as "SS") communication. In particular, a synchronization type SS modulation (where the carrier frequency and the spreading code are in a synchronous relationship) that can be applied to a simple wireless device without requiring a synchronization holding function such as a delay lock loop (DLL) or an AGC circuit, and And / or a demodulator.

[0002]

[Technical background] In SS communication in recent years, mobile communication using a multiple access method by SS technology has reached a practical range. As is well known, since radio resources are limited, it is necessary to effectively use frequencies. In that respect, the SS signal is spread over a wide frequency band and its power spectral density becomes very small, which has a small effect on other communications,
Since it can be used in the existing communication frequency band, it has a great effect in that respect, and in principle, it can contribute to the improvement of frequency use efficiency. Recently, the Ministry of Posts and Telecommunications in Japan is also approving the frequency band dedicated to SS communication, and it is expected that the application will be expanded to wireless communication for homes in the future, and its future potential and development are greatly expected. ing.

[0003]

2. Description of the Related Art In a receiver (demodulation device) for SS communication, synchronization acquisition and synchronization holding during demodulation operation are basically important, and various synchronization acquisition methods and holding methods have been proposed so far. And, it has been put to practical use. Among them, the carrier for the angle modulation which is the primary modulation at the time of modulation,
In the so-called synchronous SS modulation and demodulation method that performs SS modulation in synchronization with the spread code clock signal used for SS modulation which is the secondary modulation, the circuit configuration of the receiver (demodulation device) is somewhat different. It is becoming known as a method that can be simplified. Note that there are FM (frequency modulation), PM (phase modulation), and the like as the angle modulation, and when the modulated signal is a digital signal in particular, it is called Shift Keying (SK), and F ( Frequency) SK, P
(Phase) SK, M (Minimum) SK and GM (Gausian Min)
imum) SK and other modulation methods.

A conventional example of the SS modulator and / or demodulator will be described with reference to the drawings. 1 and 2 are block configuration diagrams of a conventional SS modulator and SS demodulator, respectively, and FIG. 3 is a DLL implemented in the SS demodulator.
A concrete block diagram of the signal processing circuit 36, which is the main part of the (delay lock loop) type synchronization holding operation, is shown in FIG.
FIG. 5 is a correlation characteristic diagram for explaining the synchronization acquisition operation of the sliding correlation type in the type synchronization holding operation. It goes without saying that the SS modulation / demodulation device is provided with both the configurations of FIG. 1 and FIG. 2 as the modulation section and the demodulation section, respectively.

First, the configuration and operation of the SS modulator in the transmitter (or the modulator of the SS modulator / demodulator in the transceiver) will be described with reference to FIG. The signal S (t) such as voice and information is supplied from the input terminal In1 and the carrier for primary modulation (cosine wave represented by cos ωt) is supplied from the oscillator 59 to the multiplier 5 for modulation. The signal S (t) is subjected to primary modulation to obtain a modulated wave S (t) cosωt.

Further, the output of the oscillator 59 is supplied to a frequency divider (hereinafter abbreviated as "divider") 25, where 1
/ N ₁ (N ₁ is a natural number such as 9) is divided to generate a clock signal for a repetition frequency, and a spread code generator (PNG) 48 generates a spread code P (t) based on this clock signal. To generate. Therefore, the spread code P (t) and the carrier for the primary modulation have a synchronous relationship.
The spread code P (t) is generally pseudo-random noise, and its clock frequency is f _{r and its} carrier frequency is f _c .
The central frequency of the main lobe of the SS signal spectral distribution is f
_c, the frequency band is as well known is that the _{(f c -f r) ~ (} f c + f r).

The spread code P (t) is supplied to a multiplier 6 for spread modulation, where SS modulation is performed to generate an SS modulated wave P (t) S (t) cosωt, and a BPF (bandpass filtering) is performed. vessel)
An electric wave is output from an antenna (not shown) via 11 and the output terminal Out1. Therefore, the SS modulated wave is caught by the antenna of another receiver (transceiver) for SS communication via a transmission medium such as air, demodulated by the demodulation device (demodulation unit), and the original signal is obtained. S (t) is restored. The BPF 11 and the BPF 12 described later
As is well known, is for attenuating or removing unnecessary frequency band components.

Next, the configuration and operation of the conventional SS demodulator of the receiver (the demodulator of the transceiver) will be described with reference to FIG. S received by an antenna (not shown)
The S modulated wave is transmitted from the input terminal In2 via the BPF12 to the AG
It is supplied to a C (automatic gain control circuit) 60, where it is amplified or attenuated as necessary, and then a multiplier 8 for both sliding correlation and despreading demodulation by multiplication, which will be described later, and DL
The signal is supplied to an L-type synchronization holding signal processing circuit (hereinafter simply referred to as “signal processing circuit”) 36. PN for multiplier 8
A spreading code generated by a G (spreading code generator) 49 is also supplied, and the clock signal frequency for this spreading code is VCO (higher than that at the time of holding the synchronization until the synchronization is acquired). Voltage controlled oscillator) 21. Sliding correlation is performed by gradually lowering the frequency and searching for a correlation point.
The sliding correlation operation and the despread demodulation operation are performed in time series.

Now, the operation leading to synchronization acquisition (synchronization establishing operation) will be described. SS modulated wave P (t) S (t) cosω in which unnecessary frequency band components are attenuated or removed by the BPF 12.
t is the spread code P from the PNG 49 in the multiplier 8.
Correlation is performed by multiplication with (t). The cycle of this spreading code is actually different from the cycle of the spreading code P (t) generated by the PNG 48 of the SS modulator by the time τ, so that this can be represented by ρ (t). For example, the output from the multiplier 8 is represented by P (t) * ρ (t) S (t) cosωt (the multiplication operator * is used only for convenience of notation).

The multiplication output is supplied to the multipliers 3 and 10, where the reproduction carrier cos from the VCO 24 is supplied.
Synchronous detection is performed by multiplication with (ωt-φ). Therefore, from the multiplier 10, P (t) * ρ (t) S (t) cosφ} / 2 and P
Two signals of (t) * ρ (t) S (t) cos (2ωt-φ) / 2 are output. Therefore, the latter LPF (low-pass filter) 45 removes the latter signal component and outputs only the signal P (t) * ρ (t) S (t) cosφ from the output terminal Out2 and performs multiplication. Supply to the container 61.

On the other hand, the reproduction carrier cos from the VCO 24
(ωt-φ) has a phase of π / 2 in the π / 2 phase shift circuit 62.
It is shifted to be sin (ωt-φ) and supplied to the multiplier 3. Therefore, the output signal of the multiplier 3 is (-1/2) P (t) * ρ
(t) * S (t) {sinφ + sin (2ωt-φ)}, and the LPF 46 outputs a signal − {P (t) * ρ (t) S (t) sinφ} / 2, If the value of φ is close to 0, sinφ is almost 0, so the actual level is close to 0. The outputs of the LPF 45 and the LPF 46 are both supplied to the multiplier 61, where multiplication is performed and − {P ² (t) * ρ ² (t) S ² (t) * sin2
φ} / 2 is output as an error signal.

This error signal is -K at the loop filter (characteristically LPF) 23 which determines the response time constant of the loop.
After being converted into a signal of sin2φ, it is supplied to the VCO 24 as a control signal. Therefore, the frequency of the reproduction carrier cos (ωt-φ) output from the VCO 24 changes in accordance with the voltage change of the control signal, and in the carrier reproduction circuit 50 including such a loop of phase-locked loop,
It is possible to perform PSK demodulation simultaneously in synchronization with the carrier of the SS modulated wave from the input terminal In2.

It is this carrier reproducing circuit 50 that first starts to work after the SS demodulator (SS modulator / demodulator) is turned on. After the carrier is reproduced, the correlation output P (t) * obtained by the LPF 45 is obtained. ρ (t) That is, the output centered on the time t ₀ point based on the triangular output characteristic of FIG. 5 is supplied to the synchronization determination circuit 34 for synchronization acquisition in sliding correlation, where P (t) * ρ (t). After the output level exceeds the SHL, that is, after the synchronization acquisition point SHL is detected (at the time of synchronization acquisition), the output shaping circuit 35 performs envelope detection to obtain a constant DC output. This DC output is added by the adder circuit 41.
Is supplied to the VCO 21 after being added to the correlation output from the signal processing circuit 36. Since the oscillating frequency of the VCO 21 is controlled by the addition output obtained as described above, the oscillating output of the VCO 21 becomes a clock signal for generating the spread code at the time of normal synchronization holding.

Next, the synchronization holding operation will be described with reference to FIG. 3, which is a specific circuit configuration of the signal processing circuit 36. The input SS modulated wave is supplied to the input terminal In3 of the signal processing circuit 36 via the BPF 12 and the AGC 60, and in the multipliers 7 and 8 forming the signal processing circuit 36,
Spreading code (a) supplied from G49 via input terminals In4 and In5, respectively, {P (t−Δt)} whose phase is Δt earlier than the regular spreading code P (t), and the spreading code (b) {also Δt Slow P (t
+ Δt)}, respectively. Since Δt is the time for one bit of the spread code in the SS system, that is, one chip time, the output of the multiplier 7 is the despread output during normal operation P
It becomes an SK modulated wave.

This PSK modulated wave is supplied to an absolute value circuit (or envelope detection circuit) 38 via a BPF 43 having a narrow band characteristic capable of transmitting the PSK modulated wave and becomes a DC signal output. The output of the multiplier 8 is converted into a DC signal output by the absolute value circuit 39 after removing such frequency components by the BPF 44. Therefore, the output from the absolute value circuit 38 becomes a signal in which a component of approximately twice the carrier frequency is multiplied by P (t) * P (t−Δt), and the output of the absolute value circuit 39 is also the carrier. It is obtained as a signal in which the component of twice the frequency is multiplied by P (t) * P (t + Δt).

When the outputs of both absolute value circuits 38 and 39 are supplied to the subtraction circuit 40 and subtracted, the characteristic of the subtraction calculation force is shown in FIG.
The inverse S-shaped correlation characteristic shown in FIG. The point (C) is a synchronization holding point. The correlation output thus obtained is output from the output terminal Out3 to the adder circuit 41 of FIG. 2 via the loop filter 37 for processing this into a control signal,
Here, the signal added to the output of the output shaping circuit 35 is supplied to the VCO 21 to maintain the synchronization.

[0017]

In the above-described conventional spread spectrum modulation and / or demodulation device, P (t from the PNG 49 in the multiplier 8 forming the signal processing circuit 36 is used.
+ Δt) in the SS modulated wave converted by up-conversion, that is, the down conversion in which the carrier frequency of the SS modulated wave and the spread code are kept in a synchronous relationship to have symmetry with the modulation time during demodulation. Since it is performed by the multipliers 3 and 10, SS synchronization at the time of demodulation can be surely obtained, and the performance such as securing the signal-to-noise ratio (CN ratio) at the time of demodulation can be substantially satisfied. Has arrived.

However, the configuration of the SS demodulator is still complicated, and for example, an AGC 60 for making the level of the input SS modulated wave appropriate, a circuit for maintaining synchronization such as DLL, etc. are indispensable, and , An expensive VCO (21, 24) is used one each for carrier regeneration and synchronization holding, and the circuit configuration is complicated as a whole, especially for consumer use such as mobile communication. When applied to equipment, further cost reduction is required. Further, in the SS modulation / demodulation device having both the modulation unit and the demodulation unit, by sharing the circuit components in the respective constituent circuits, it is possible to reduce the component cost and ensure sufficient modulation performance and demodulation performance. It is desired to improve stability.

[0019]

In order to solve the above-mentioned problems, the present invention provides an SS modulator and an SS demodulator configured as follows, and further, an S having both functions is provided.
An S modulation / demodulation device is also proposed.

First, the SS modulator on the transmitting side has an angle modulating means for angle-modulating an information signal such as a voice, and the obtained angle-modulated signal is frequency-multiplied by a multiplication factor of 2 or more natural numbers N ₁ to obtain a multiplication angle. Frequency multiplying means for obtaining a modulated wave, frequency dividing means for obtaining a clock signal by dividing the angle modulated signal by a dividing number of 2 or more natural numbers N _2, and a spread code is generated based on the obtained clock signal. And a spreading modulation means for spreading-modulating the multiplied angle modulation wave with the obtained spreading code and outputting a spread spectrum modulation wave.

In the SS demodulation device on the receiving side, a local oscillator that outputs a local oscillation signal, frequency conversion means that converts the spreading code for demodulation to an intermediate frequency by the local oscillation signal, and an intermediate frequency are converted. Despreading demodulation means for despreading to obtain an angle modulated wave by multiplying the spread spectrum modulated wave by a spreading code for demodulation, a phase locked loop for demodulating the obtained angle modulated wave to obtain an angle demodulated signal, Clock signal generating means for generating a clock signal based on the voltage controlled oscillation signal output from the voltage controlled oscillator in the phase locked loop and the local oscillation signal, and the demodulation spread code based on the obtained clock signal. A demodulation spread code generating means for generating and a synchronization acquisition means for generating a control signal for synchronization acquisition from the angle demodulation signal and performing synchronization acquisition during spread spectrum demodulation are provided. Configuration was.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the spread spectrum modulation and / or demodulation device of the present invention will be described with reference to FIG. FIGS. 6 (A) and 6 (B) are a block diagram of an embodiment of the SS modulator 1 of the present invention and a block diagram of a first embodiment of the SS demodulator 2a, respectively. Incidentally, the SS modulator demodulator having both of the demodulating unit and the modulating unit, naturally FIG. 6 (A), the but not provided with the configuration of both (B), the antenna A _1, A
Some components such as ₂ and PNG 48, 49 can be used in common.
In FIG. 6, the same components as those of the conventional device shown in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description of the operation thereof will be omitted. Further, the description of the SS modulation and demodulation device will be replaced with the description of the SS modulation device and the SS demodulation device.

As shown in FIG. 6A, S in the transmitter is
The S modulator 1 includes an angle modulation circuit 52 for primary modulation, a frequency multiplier (multiplication number = N ₁ ) 53, and a frequency divider (frequency division number = 1 /).
N ₂ ) 28, PNG 48, LPF 31, multiplier 6 for spreading modulation, amplifier 16 and the like, and these are connected as shown in the figure. An oscillator for supplying a modulation carrier is built in the angle modulation circuit 52, and the angle modulation here generally refers to FM modulation or PM modulation. In a broad sense, each of the FSK, MSK, and GMSK is described. Data modulation is also included. In the present embodiment, the description will be limited to FM modulation, but any angle modulation can be applied to modulated waves other than FM modulation.

By the way, in the communication using the angle modulation, a method of directly selecting the carrier frequency for modulation and transmitting it directly, or a method of selecting a low frequency in advance and performing the angle modulation and then converting to a higher frequency by up-conversion. There is a way to send. In the former method of direct transmission, the circuit configuration becomes simpler. Therefore, in general, the higher the carrier frequency with respect to the frequency deviation, the worse the SN ratio in the modulation circuit tends to be. However, in the device of the present invention, the configuration is simplified. , I will use the former method.

In the configuration shown in FIG. 6 (A), an information signal S (t) = sinpt such as a voice signal or data is supplied from the input terminal In1 to the angle modulation circuit 52, where a carrier from an internal oscillator is supplied. Is modulated with the information signal S (t), FM modulation, which is the primary modulation, is performed. This angle modulation circuit 5
The output of 2 is represented by the FM modulation signal f _M (t).
In this case, the carrier frequency is f ₀ and the frequency deviation is ΔF.

The FM modulation signal f _M (t) is supplied to the frequency multiplier 53.
Where the carrier frequency and frequency transfer are N ₁
(N ₁ is a natural number such as 9). Therefore, the frequency multiplier 53 obtains final carrier frequencies and frequency shifts of N ₁ f ₀ and N ₁ ΔF, respectively, and the frequency modulated wave f (t) = E sin {ω ₀ t + (Δf / fm) The signal is output as sinpt} and is supplied to the multiplier 6 for spread modulation. Note that fm
Indicates the information frequency, and sin pt = S (t).

On the other hand, the FM modulated signal f _M (t) is divided by the frequency divider 28.
Is also supplied to the frequency division circuit, and the frequency is divided here so that the basic carrier frequency is f ₀ / N ₂ (N ₂ is a natural number such as 5) and the frequency transfer is Δ.
f / N ₂ . This frequency-divided output signal is supplied to the PNG 48 as the clock signal C (t) having the frequency fc, and the spread code P (t) is generated based on this clock signal. This spread code is supplied to the multiplier 6 for spread modulation via the LPF 31, and spread spectrum is performed by multiplication with the frequency modulated wave f (t). Therefore, the spread spectrum signal SS (t) of P (t) f (t) is obtained as the output of the multiplier 6, is appropriately amplified by the amplifier 16, and is output as a radio wave from the transmitting antenna A ₁ .

Next, a first embodiment of the SS demodulation device of the present invention on the receiving side will be described with reference to FIG. 6 (B). SS
The demodulator 2a includes multipliers (mixers, phase comparators) 8 to 10, BPFs 12 to 14, amplifiers 17 to 2 as shown in the figure.
0, PNG 48, local oscillators 57, 58, synchronous supplementary control circuit 32, exclusive OR circuit 22, LF (loop filter) 23, VCO 24, and frequency divider {frequency division number = 1 / (N
₁ * N ₂ ); hereinafter simply referred to as “1 / N ₁ N ₂ ”} 26,
27, LPFs 29, 30 and the like, which are connected as shown in the drawing. In addition, LF23, VCO2
4, a phase comparator 10 and an amplifier 19 form a PLL (phase locked loop) 41.
In the case where the output of the above or the local oscillation signal from the local oscillator 58 is an analog signal, the A /
Binarization means such as a D converter is connected.

In the SS demodulator 2a having the above structure,
The spread spectrum signal SS (t) received by the receiving antenna N ₂ has its unnecessary frequency band component removed by the BPF 12, and is then appropriately amplified by the high frequency amplifier 17 to be supplied to the despreading multiplier 8. Supplied. Note that the spread spectrum signal SS (t) here is actually different from the spread spectrum signal SS (t) output from the transmitting antenna A ₁ ,
Noise components such as interference waves are included, but the same symbol is used for convenience.
We will use SS (t).

On the other hand, from the local oscillator 58, a frequency conversion frequency signal (hereinafter referred to as "local oscillation signal") is supplied to a multiplier (mixer) 9, where this signal is supplied to the LPF 29. The spread code converted to the intermediate frequency (beat down) is obtained by multiplying the spread code from the PNG 49 via the. Therefore, in the multiplier 8, despread demodulation is performed by multiplying the spread spectrum signal SS (t) by the spread code whose frequency has been converted from the multiplier 9, but in reality, both signals supplied to the multiplier 8 Since the despreading demodulation cannot be performed unless the synchronization is obtained, the operation principle for establishing the synchronization, that is, the synchronization acquisition operation in the SS demodulator 2a will be described.

The oscillator 57 outputs the signal Cs (t) for synchronization acquisition, and its frequency fs is δf which is slightly smaller than the frequency fc of the regular clock signal C (t) for SS demodulation.
Frequency (more or less), that is, fs = fc ± δf
It has become a frequency. The synchronization acquisition signal Cs (t) having the frequency fs is supplied as a clock signal to the PNG 49 via a switch circuit (hereinafter abbreviated as “switch”) Sw, and based on this, the spread code ρ (t) is supplied. Is being generated. The spread code ρ (t) is supplied to the multiplier 9 via the LPF 29.

The multiplier 9 has a local oscillator 5 as described above.
8 is a local oscillation signal E ₀ * cosωt having a frequency f _L
Is supplied, so the multiplier output is ρ (t) * E ₀ * cos
It becomes ωt and is supplied to the multiplier 8 for despreading. The output of the multiplier 8 is P (t) ρ (t) * f (t) * E ₀ * cosωt, but only the intermediate frequency band component is extracted by the BPF 13 and the synchronous acquisition carrier signal f _SI (t) is obtained. can get. This signal f _SI (t) _{is, f SI (t) = P} (t) ρ (t) (E * E 0/2) si
It is represented by n {ω _i t + (Δf / fm) sinpt}, and this waveform is shown on the time axis as shown in FIG. 7 (A).

In FIG. 7A, a and a'are correlation points,
b, b 'is a non-correlation part, the one period of the chip of the spread code [rho (t) and N _PN, a~a' between the N _PN / (fs-
The time is represented by fc). Note that FIG. 7B shows a noise voltage generated in a frequency band higher than the information frequency during the angle demodulation output which is the output signal of the error amplifier 19 in the phase locked loop 41 described later. As is apparent from FIG. 7 (B), the noise voltage becomes small (almost 0) at the correlation points a and a ', and becomes large at the uncorrelated portions b and b'.

The synchronous acquisition carrier signal f _SI (t) from the BPF 13 is supplied to the phase comparator (multiplier) 10 which constitutes the phase locked loop 41 via the amplitude limiting amplifier 18. From the phase-locked loop 41, an output synchronized with the frequency fi of the synchronous acquisition carrier signal supplied to the phase comparator 10 is obtained from the VCO 24 and supplied to the frequency divider 26 and the phase comparator 10.

On the other hand, a local oscillator signal cosωt from a local oscillator 58 is supplied to the frequency divider 27, and its frequency f _L is divided by this frequency divider 27 into 1 / N ₁ N ₂ to obtain a basic frequency division frequency. F _L / (N ₁ N ₂ ) and is supplied to one terminal of an exclusive OR circuit (hereinafter referred to as “EX-OR circuit”) 22. Similarly, the output of the VCO 24 is the frequency divider 2
It is divided into 1 / N ₁ N ₂ by 6 and its fundamental frequency is f
It becomes i / (N ₁ N ₂ ) and is supplied to the other terminal of the EX-OR circuit 22. Therefore, a multiplication operation is performed here, and an output obtained by multiplying both outputs of the frequency dividers 26 and 27 is obtained from the EX-OR circuit 22 (hence EX-O).
A multiplier may be used in place of the R circuit}, but from the output signal thereof, (fi + f _L ) / (N
_The frequency component ₁ N ₂ ) is selected and supplied to the switch Sw via the amplifier 20.

Since the center carrier frequency of the spread spectrum signal SS (t) is N ₁ * f ₀ , the output frequency of the amplifier 20 is (fi + f _L ) / N ₁ N ₂ , that is, f ₀ / N.
It becomes ₂ . This f ₀ / N ₂ is equal to the basic frequency division carrier frequency of the frequency divider 28 in the SS modulator 1, and S 0
P that generates a spreading code for modulation when S synchronization is established
It is equivalent to the clock signal supplied to the NG 48.

By the way, the output waveform of the BPF 13 is shown in FIG.
As shown in (A), in order to detect the correlation points a and a'in the figure, the present invention utilizes the output of the error amplifier 19 in the phase locked loop 41 which performs angle demodulation. Noise generated in the frequency band higher than the information frequency from this angle demodulation output is extracted by an HPF (high-pass filter; not shown) to detect the level, and as shown in FIG. ，
Since the noise voltage is small at a ′ and the noise voltage is large at the non-correlated portions b and b ′, the synchronous acquisition control circuit 32 discriminates the noise voltage and binarizes it, and differs from each other according to the magnitude of the output. By supplying the control signal converted into the digital signal to the switch Sw, the switch Sw is switched from the contact χ to the contact y at the correlation point a or a ′.

The level of the control signal for acquisition of synchronization is
Although it does not change depending on the received electric field strength, this is due to AGC (Auto Gain Controlle) in the conventional SS demodulator.
This is because the amplitude limiting amplifier 18 can be used instead of r) 60. As a result, the control signal is stably detected regardless of the magnitude of the received electric field strength. Since the clock signal switched to the correlation point a or a'by this control signal and supplied to the PNG 49 is equivalent to the clock signal at the time of modulation, the spreading code generated by the PNG 49 is applied to the contact y of the switch Sw. After switching, ρ (t) to PN
It changes to the same spreading code P (t) as G48.

The spread code P (t) is supplied to the multiplier (mixer) 9 through the LPF 29, where the frequency is converted by the local oscillator signal from the local oscillator 58 as described above, and then the multiplier 8 is supplied.
Is supplied to and where despread demodulating the spread spectrum signal SS (t), despread intermediate frequency signal f _I (t) is _{f I (t) = (E} * E 0/2) sin { ω _i t + (Δf / fm) sinp
The angle-modulated wave is converted to an intermediate frequency t}. By supplying this to the phase-locked loop 41 (phase comparator 10) via the BPF 13 and the amplitude limiting amplifier 18, angle demodulation is favorably performed in the phase-locked loop 41, and the LPF 3
After removing unnecessary components other than the frequency band of the demodulation information signal at 0, the demodulated information S '(t) is obtained from the output terminal Out2.

Next, a second embodiment of the SS demodulation device of the present invention will be described with reference to the block diagram of FIG. In FIG. 8, the same components as those of the apparatus 2a of the first embodiment shown in FIG. 6 are designated by the same reference numerals, and the description thereof will be omitted.
The main characteristics of the device 2b of the second embodiment are that, as is clear from a comparison between the two figures, there are some differences in the circuit configuration and the like for synchronization acquisition. That is, the synchronization acquisition clock signal generation circuit system from the VCO 24 to the switch Sw is different, and the operation principle is naturally different, which will be described in detail below.

One of the concrete differences is EX-OR.
The multiplier 4 is used in the device 2b of the second embodiment instead of the circuit, and the PLL is not divided by each divider.
The output of the VCO 24 in 41 and the local oscillator signal output E ₀ * cosωt (frequency f _L ) from the local oscillator 58 are directly multiplied here. Since the output signal of the VCO 24 is synchronized with the synchronization acquisition carrier signal fi as described above, the multiplier 4
Of course, a frequency component of f _L + fi is also output.
Therefore, the BPF 15 allows only the signal component having the frequency f _L + fi to pass therethrough, the amplifier 20 amplifies the signal as necessary, and the frequency divider 26 performs frequency division to obtain a fundamental frequency of (f _L + fi ) / (N ₁ N ₂ ) output signal.

As described above, since the center carrier frequency of the spread spectrum signal SS (t) is N ₁ * f ₀ , the frequency divider output becomes f ₀ / N ₂ and is supplied to the switch Sw. . This frequency of f ₀ / N ₂ is the same as the SS modulator 1
As described above, the frequency is equal to the basic frequency-divided carrier frequency of the frequency divider 28 and is equal to the clock signal supplied to the modulation spread code generation circuit 48 when SS synchronization is established.

With this configuration, the SS demodulator 2a of the first embodiment requires two frequency dividers, but only one is required in this embodiment, and the configuration is further simplified. Also, EX
-Since the multiplier 4 is used instead of the OR circuit, VC
Since the O output and the local oscillation signal may be in the form of analog signals, the binarizing means is not necessary.

Next, a third embodiment of the SS demodulation device of the present invention will be described with reference to the block diagram of FIG. 9, the same components as those of the first and second embodiment devices 2a and 2b shown in FIGS. 6 and 8 are designated by the same reference numerals, and the description thereof will be omitted. The main characteristics of the third embodiment device 2c are that there are some differences in the beat-down method of the spreading code for demodulation and the circuit configuration for synchronization acquisition, as is clear by comparing the drawings.

As a concrete difference, the local oscillator 58 for outputting a local oscillation signal is the same as the device 2 of the first and second embodiments.
The local oscillator 5 is configured to oscillate at a frequency lower than the oscillation frequency at a and 2b by the amount divided by N _2.
The frequency f _L of the local signal output E ₀ * cosωt from 8 is set to N ₂
A multiplier 33 for multiplying is provided. The clock signal generation circuit system for synchronization acquisition from the VCO 24 to the switch Sw is similar to that of the device 2a of the first embodiment, and the EX-OR
Since the circuit 22 is used, only a digital signal can be handled as an input signal, but it has a feature that balance adjustment is unnecessary as compared with a multiplier.

Now, the synchronization acquisition operation in the SS demodulator 2c of the third embodiment will be described. Synchronization acquisition signal Cs (t) from the synchronization acquisition signal generator 57 (its frequency f
s is slightly different from the frequency fc of the regular clock signal C (t)} to the spreading code generating circuit 49, and the spreading code ρ
(t) is generated and the spread code ρ (t) is supplied to the multiplier (mixer) 9 via the LPF 29.
This is similar to the second embodiment devices 2a and 2b.

On the other hand, the local oscillator 58 outputs the local oscillator signal E ₀ * cosω ₀ t having the frequency f _{L ′} , which is multiplied by N ₂ by the multiplier 33 and multiplied by the local oscillator signal E ₀ * cosω.
t, and is supplied to the mixer 9. Therefore, the mixer output is ρ (t) P (t) * f (t) * E ₀ * cosωt, but B
Only the synchronous acquisition carrier signal f _SI (t) converted into the intermediate frequency by the PF 13 is extracted. This signal f _SI (t) is
P (t) ρ (t) (E * E 0/2) sin {ω i t + (ΔF / fm) sinpt}
And is also shown on the time axis, as shown in FIG. 7 (A).

The synchronous acquisition carrier signal f _SI (t) is supplied to the phase comparator (multiplier) 10 which constitutes the PLL 41 via the amplitude limiting amplifier 18, and the VC which constitutes the PLL 41.
From O24, an output synchronized with the synchronous acquisition carrier signal fi supplied to the phase comparator 10 is supplied to the frequency divider 26. On the other hand, the local oscillator signal E ₀ * cosω ₀ t is also supplied to the frequency divider 25, where the fundamental frequency thereof is divided into 1 / N ₁ and the output signal of the fundamental frequency f _{L ′} / N ₁ And
It is supplied to one terminal of the EX-OR circuit 22.

The output of the VCO 24 is output by the frequency divider 26 to 1
/ N ₁ N ₂ and the basic division frequency is fi / (N ₁
N ₂ ), and is supplied to the other terminal of the EX-OR circuit 22. Therefore, the EX-OR circuit 22 performs multiplication by an exclusive OR operation and obtains a multiplied output of both signals. From among them, a signal of a frequency of (f _L + fi) / (N ₁ N ₂ ) is obtained. It is extracted by the BPF 15, sufficiently amplified by the amplifier 20, and then supplied to the switch Sw. The output fundamental frequency of the amplifier 20 is f ₀ / for the above reason.
Although the N _2, the f ₀ / N ₂ is equal to the basic division carrier frequency divider 28 in the SS modulator 1,
Spreading code generation circuit 4 for modulation when SS synchronization is established
8 becomes equal to the frequency of the clock signal supplied.

In order to detect the correlation points a and a'in the output waveform of the BPF 13 shown in FIG. 7A, the output of the error amplifier 19 in the angle demodulating PLL 41 is also used in this embodiment. , When the noise generated in the frequency band higher than the information frequency is detected from this angle demodulation output, FIG.
As shown in, the noise voltage is small at the correlation points a and a ′,
The switching operation of the switch Sw is performed similarly to the first embodiment 2a by utilizing the fact that the noise voltage becomes large in the uncorrelated portions b and b '. As a result, the control signal is stably detected without fluctuating due to the strength of the received electric field, and by switching from the terminal χ of the switch Sw to y by this control signal, the PNG 49
Since the clock signal supplied to the switch is equivalent to the clock signal at the time of modulation, the spreading code output from the PNG 49 changes from ρ (t) to P (t) when the switch Sw is switched.

The spread code P (t) is supplied to the mixer 9 via the LPF 29, where it is multiplied by the multiplied local oscillation signal E ₀ * cosωt from the multiplier 33 and then the multiplier 8 for despreading. And despreading is performed, and f _I (t) = (E *
_{E 0/2) sin {ω} i t + (Δf / fm) * sinpt} becomes converted to an intermediate frequency angle modulated wave (intermediate frequency signal), and then made further angle demodulation by PLL41, via the LPF30 Then, the demodulated information S '(t) is output from the output terminal Out2.

In the configuration of the third embodiment described above, the multiplication number of the frequency multiplier 33 is N ₁ instead of N ₂ , and the frequency division number of the frequency divider 25 is 1 / N ₁ instead. With / N ₂ , almost the same result is obtained. In that case, it goes without saying that the local oscillator 58 is configured to oscillate at a frequency lower than the oscillation frequency in the first and second embodiment devices 2a and 2b by the amount divided by N ₁ .

Next, a fourth embodiment of the SS demodulation device of the present invention will be described with reference to the block diagram of FIG. Also in FIG. 10, the same components as those of the first to third embodiment devices 2a to 2c shown in FIGS. 6, 8 and 9 are designated by the same reference numerals, and detailed description thereof will be omitted. The circuit configuration of the device 2d of the fourth embodiment is most similar to that of the device 2c of the third embodiment of FIG. 9 as is clear from a comparison of the drawings. The local oscillator 5 is configured so as to oscillate at a frequency lower than the oscillation frequency in the devices 2a and 2b by N _{1 according} to the second embodiment.
The frequency of the frequency multiplier 33 for multiplying the frequency f _L of the local oscillation signal from 8 is N ₁ instead of N ₂ . As a result, the frequency division number of the frequency divider 26 is changed from 1 / N ₁ N ₂ to 1 / N ₁ and the frequency divider 25 used in the device 2c of the third embodiment is not required, so that the circuit configuration is slightly simplified. To be done. Since the synchronization acquisition operation and the demodulation operation of the fourth embodiment device 2d are basically the same as those of the third embodiment device 2c and the like, detailed description thereof will be omitted.

The above-described third and fourth embodiment devices 2c,
Also in 2d, a multiplier may be used instead of the EX-OR circuit 22, for the same reason as in the first embodiment device 2a.

[0055]

As described above, according to the SS modulation and / or demodulation device of the present invention, the frequency-divided frequency of the angle-modulated output signal is used as the clock signal for generating the spread code, and the angle-modulated output signal is used. Is multiplied to obtain a predetermined carrier frequency and frequency deviation, and the carrier frequency and the spread code clock signal are synchronized with each other to perform SS modulation and / or SS demodulation. So
It has the following various features. A clock signal for generating a spread code for despreading in SS demodulation can be generated relatively easily using a PLL, a frequency divider, an EX-OR circuit (or a multiplier), a BPF, and the like. The synchronization holding after the synchronization acquisition can be easily performed by the PLL for the angle demodulation, which eliminates the need for the DLL for the synchronization holding, which is indispensable in the conventional device. Since a simple amplitude limiting amplifier is used in the intermediate frequency stage, the AGC required for SS reception can be eliminated, and SS modulation and demodulation can be realized with a relatively simple circuit configuration. The SS technology can be applied to wireless devices and the like.

If the EX-OR circuit in the clock signal generating means for demodulating the spread code for demodulation is replaced with a multiplier, a very high frequency multiplication process can be performed, and the VCO output and the local oscillator signal can be in the form of analog signals. Since it does not matter, binarization is not necessary. A means for generating a clock signal for demodulation spread code generation,
Both the local oscillation signal and the voltage control oscillation signal are 1 / (N ₁ N
_It is advantageous when the carrier frequency is relatively low if the frequency division required in ₂ ) is multiplied or the exclusive OR operation is performed and only the frequency components necessary for clock signal generation are extracted from this operation output. Is.

The clock signal generating means multiplies the local oscillation signal by the voltage control oscillation signal, extracts only the frequency component necessary for generating the clock signal from the obtained multiplication output signal, and further 1 / If the frequency is divided into (N ₁ N ₂ ), the usable carrier frequency range can be widened. A means for generating a clock signal for demodulation spread code generation,
The signal obtained by dividing the local oscillation signal into 1 / N ₁ or 1 / N ₂ and the signal obtained by dividing the voltage controlled oscillation signal into 1 / (N ₁ N ₂ ) are multiplied or exclusive A logical OR operation is performed to pass only the frequency component necessary for generating the clock signal from the operation output signal, and the local oscillator for outputting the local oscillation signal is set to have a frequency N higher than the required oscillation frequency. ₂
Or configured to oscillate only low frequency amount divided by N _1, further an output signal frequency of the local oscillator when having a frequency multiplier for multiplying the _doubled or N ₁ × N has a higher carrier frequency Even in the case, stable clock reproduction can be performed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a conventional representative SS modulator.

FIG. 2 is a block configuration diagram of a conventional representative SS demodulation device.

FIG. 3 is a block diagram of a DLL-type synchronization holding signal processing circuit that constitutes a conventional SS demodulation device.

FIG. 4 is a characteristic diagram for explaining a sync holding operation in a DLL type sync holding signal processing circuit.

FIG. 5 is a correlation characteristic diagram for explaining a sliding correlation type synchronous capturing operation.

FIG. 6 is an SS modulator and an SS demodulator of the present invention (first
(Embodiment) FIG.

FIG. 7 is a signal waveform diagram for explaining synchronization acquisition operation in the SS modulator of the present invention.

FIG. 8 is a block configuration diagram of a second embodiment of the SS demodulation device of the present invention.

FIG. 9 is a block configuration diagram of a third embodiment of the SS demodulation device of the present invention.

FIG. 10 is a block configuration diagram of a fourth embodiment of an SS demodulation device of the present invention.

[Explanation of symbols]

1 ... SS modulator, 2a-2d ... SS demodulator, 3-1
0 ... Multiplier, 11-15 ... Bandpass filter, 16-20 ... Amplifier, 21, 24 ... VCO (voltage controlled oscillator), 22 ...
EX-OR (exclusive OR) circuit, 23, 37 ... Loop filter, 25-28 ... Frequency divider, 29-31 ... Low-pass filter, 32 ... Synchronization acquisition control circuit, 33, 53 ... Multiplier, 4
1 ... PLL, 48, 49 ... PNG (spreading code generator),
52 ... Angle modulation circuit, 57-59 ... Local oscillator, A _1, A
₂ ... Antenna, Sw ... Switch.

Claims (9)

[Claims] 1. An angle modulation means for angle-modulating an information signal such as voice, and a frequency multiplication means for frequency-multiplying the obtained angle-modulated signal by a multiplication factor of 2 or more natural numbers N ₁ to obtain a multiplied angle-modulated wave. Dividing means for obtaining a clock signal by dividing the angle-modulated signal by a dividing number which is a natural number N ₂ of 2 or more, and spreading code generating means for generating a spreading code based on the obtained clock signal, A spread spectrum modulator of the synchronous type, comprising: spread spectrum modulation means for spreading and modulating the multiplied angle modulated wave with the obtained spread code to output a spread spectrum modulated wave. 2. A local oscillator for outputting a local oscillation signal, frequency conversion means for converting the demodulation spreading code to an intermediate frequency by the local oscillation signal, and the demodulation spreading code converted to the intermediate frequency for the spread spectrum. Despread demodulation means for despreading to obtain an angle modulated wave by multiplying the modulated wave, a phase locked loop for demodulating the obtained angle modulated wave to obtain an angle demodulated signal, and voltage control in the phase locked loop Clock signal generating means for generating a clock signal based on the voltage controlled oscillation signal output from the oscillator and the local oscillation signal, and a demodulation spreading code for generating the demodulation spreading code based on the obtained clock signal Synchronous spread spectrum recovery, which includes a generation means and a synchronization acquisition means for generating a control signal for synchronization acquisition from the angle demodulation signal and performing synchronization acquisition during spread spectrum demodulation. Apparatus. 3. The modulating section, an angle modulating means for angle-modulating an information signal such as voice, and a frequency multiplier for multiplying the obtained angle modulated signal by a natural number N ₁ of 2 or more to obtain a multiplied angle modulated wave. Means and a natural number N ₂ of 2 or more for the angle modulated signal.
A frequency division means for frequency division, a spreading code generation means for generating a spreading code based on the output of the frequency division means as a clock signal, and a spreading code for the above multiplying angle modulated wave by the obtained spreading code. And a spread spectrum modulation means for outputting a spread spectrum modulated wave, the demodulation section, a local oscillator for outputting a local oscillation signal, a frequency conversion means for converting the spread spectrum code for demodulation to an intermediate frequency by the local oscillation signal, Despreading demodulation means for despreading the spread spectrum modulated wave by multiplying the spread code converted to the intermediate frequency to obtain the angle modulated wave, and demodulating the obtained angle modulated wave to obtain the angle demodulated signal. A phase-locked loop to be obtained, clock signal generation means for generating a clock signal based on the voltage-controlled oscillation signal output from the voltage-controlled oscillator in the phase-locked loop, and the local oscillation signal, and the obtained clock signal. A demodulation spreading code generating means for generating the demodulation spreading code based on a lock signal, and a synchronization acquiring means for generating a synchronization acquisition control signal from the angle demodulation signal to perform synchronization acquisition during spread spectrum demodulation. A synchronous spread spectrum modulation / demodulation device equipped with the same. 4. A _first frequency divider for dividing the local oscillation signal by 1 / (N ₁ N ₂ ) to obtain a frequency-divided local oscillation signal, by means of a clock signal generating means for generating a spreading code for demodulation. A second frequency divider for dividing the voltage controlled oscillation signal to 1 / (N ₁ N ₂ ) to obtain a divided voltage controlled oscillation signal, and multiplication of both outputs of the first and second frequency dividers 3. The spectrum according to claim 2, which is composed of arithmetic means for performing an exclusive OR operation and a bandpass filter which passes only a frequency component necessary for generating a clock signal from an output signal of the arithmetic means. The spread spectrum demodulation device or the spread spectrum modulation demodulation device according to claim 3. 5. A means for generating a clock signal for generating a spread code for demodulation is required for generating a clock signal from a multiplier for multiplying a local oscillation signal and a voltage controlled oscillation signal, and an output signal of the multiplication means. 3. The spread spectrum demodulation device according to claim 2, wherein the spread spectrum demodulation device comprises a bandpass filter which allows passage of only frequency components and a frequency divider which divides an output signal of the bandpass filter into 1 / (N ₁ N ₂ ). Alternatively, the spread spectrum modulation / demodulation device according to claim 3. 6. A first frequency divider for obtaining a divided oscillation signal by dividing a local oscillation signal into 1 / N ₁ or 1 / N ₂ by means of a clock signal generating means for generating a spreading code for demodulation. A second frequency divider for dividing the voltage-controlled oscillation signal to 1 / (N ₁ N ₂ ) to obtain a divided voltage-controlled oscillation signal, and an output signal of both the first and second frequency dividers. Comprising arithmetic means for performing multiplication or exclusive OR operation, and a bandpass filter for passing only frequency components necessary for generating a clock signal from the output signal of the arithmetic means, and for outputting a local oscillation signal Of the local oscillator is oscillated at a frequency lower than the required oscillation frequency by N ₂ or N ₁ , and the frequency of the output signal of this local oscillator is multiplied by N ₂ or N _1. The spectrum spreader according to claim 2, further comprising a frequency multiplier for supplying the frequency to the frequency conversion means. Regulating device or spread spectrum modulation and demodulation apparatus according to claim 3. 7. A first frequency divider for obtaining a divided voltage controlled oscillation signal by dividing the voltage controlled oscillation signal into 1 / N ₁ by means of a clock signal generating means for generating a spread code for demodulation. Arithmetic means for performing multiplication or exclusive OR operation of the output signal of the frequency divider and the local oscillation signal; and a bandpass filter for passing only the frequency component necessary for generating the clock signal from the output signal of the arithmetic means. A second frequency divider for generating a clock signal by dividing the output signal of the band-pass filter by 1 / N ₂ , and a local oscillator for outputting a local oscillation signal having a required oscillation frequency. It is configured to oscillate a frequency that is lower than N ₁ by N ₁ , and the output signal frequency of this local oscillator is N
_The spread spectrum demodulation device according to claim 2 or the spread spectrum modulation and demodulation device according to claim 3, further comprising a frequency multiplier that frequency-multiplies by a factor of ₁ and supplies it to the frequency conversion means. 8. A synchronization acquisition signal generating means for generating a synchronization acquisition signal having a frequency slightly different from the frequency of the clock signal for generating the spread code for demodulation, and the synchronization acquisition signal when the synchronization acquisition is established. 8. A switch means for switching from a signal generating means to a generating means for the clock signal and outputting the clock signal, further comprising any one of claims 2 or 4 to 7.
4. The spread spectrum demodulation device according to claim 3 or the spread spectrum modulation and demodulation device according to claim 3. 9. The synchronization acquisition means detects a noise component having a frequency band higher than the frequency band of the information signal from an angle demodulation output demodulated in a phase locked loop to identify a correlation point and a non-correlation part. 9. The synchronous spread spectrum demodulation according to any one of claims 2 or 4 to 8, wherein the identification result is converted into a control signal and the switching means is switched to perform synchronization acquisition. An apparatus or a spread spectrum modulation / demodulation apparatus according to claim 3.