JPS61161079A - Synchronizing signal detection circuit for television video signal - Google Patents

Abstract

PURPOSE:To obtain a stable hold pulse even if the rising of a horizontal synchronizing pulse changes with time at the boundary between the NG and OK periods by using a hysteresis circuit having an NG counter and an OK counter. CONSTITUTION:When the horizontal synch pulse 15 is shifted so as to be positioned at the boundary between the OK and NG periods shown at A and B, the pulse 15 is introduced into CK's of both the NG counter 9 and the OK counter 10, so that the counters 9, 10 start to count up. At this time, when it is always the counter 10 that issues carrier wave signals 19 first, the output phase of the hold pulse 25 is not changed. Conversely, when it is the counter 9 that issues the carrier wave signal 18 first, the counters 9, 10 are cleared simultaneously, with the signal being introduced into an NG-OK pulse generating circuit 8. In the circuit 8, an inverting pulse is delayed for each H by 1H by signals 18. In this manner, NG pulse 23 and OH pulse 25 are as shown at D and E, respectively so that a strong and stable state is obtained against jittering of the pulse 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal detection circuit for television video signals, and particularly to a synchronization signal detection circuit using a hysteresis circuit using an OK counter and an NG counter.

[Conventional technology]

The video signal of the NTSC system is a four-field sequence video signal due to the phase relationship between the subcarrier signal and the horizontal synchronization signal.

A conventional synchronization signal detection circuit separates a vertical synchronization signal and a horizontal synchronization signal from an input video signal, and uses this and a subcarrier signal locked to the burst of the input video signal to detect the input video signal. It was a circuit that detected which of the four fields it hit.

[Problems to be solved]

The above-mentioned conventional synchronization signal detection circuit has the problem that even if the input signal changes and the relationship between the synchronization signals changes within one field, the detection is only performed at the beginning of the field, resulting in a slow response. . Further, since there is no circuit for countermeasures against zinc in the horizontal synchronization signal and vertical synchronization signal, there is a problem that the horizontal phase may change for each field.

[Means for solving problems]

The present invention solves the above problems, and includes a sync signal separation circuit that extracts a horizontal sync signal from a television video signal, a 3-58 MHz sync signal synchronized with a burst signal, and a sync signal with a frequency twice that of the sync signal. 7. A burst control onger that outputs a 16 MHz signal;
A vertical sync pulse generator, a horizontal sync pulse generator, a frame signal generator that generates a frame signal from the vertical sync pulse and horizontal sync pulse that are output from both generators, an NG/OK pulse generator, and an NG/OK pulse generator. It has a hysteresis circuit having a counter and an OK counter, and a hold circuit that generates a hold pulse from an OK pulse and a horizontal synchronizing pulse.

〔Example〕

Next, the embodiment will be described with reference to FIGS. 1 to 3.

FIG. 1 is a block diagram of an embodiment of a synchronization signal detection circuit for a television video signal according to the present invention, and FIG.
are time charts of the signals of the above circuit, and FIG. 3 is a diagram showing the phase relationship of the synchronization signals.

In FIG. 1, a synchronization signal separation circuit 1 generates a horizontal synchronization signal 12 from an input video signal 11. Horizontal synchronization signal 12
are vertical sync pulse generator 2 and horizontal sync pulse generator 4
is input. The vertical synchronization pulse generator 2 outputs seven vertical synchronization pulses L3 after 67H (H: horizontal scanning period, the same applies hereinafter) from the start of the vertical synchronization signal. The horizontal synchronizing pulse generator 4 outputs a horizontal synchronizing pulse 15 (see FIG. 2(C)) excluding the no-p H component.

The frame signal generator 3 detects whether the vertical synchronization pulse L3 and the horizontal synchronization pulse 15 match, and outputs a frame signal [4]. In the NTSC video signal,
Since both pulses 13 and 15 match for each field, this frame signal [4 causes the output of the input video signal to
You can know the DD/EVEN field.

A burst control onger (hereinafter referred to as BCO) 5 receives a 3.58 MHz synchronization signal 16 synchronized with the burst signal of the input video signal 11 and two of the synchronization signals 16.
Double synchronization signal 17 with double frequency (7, 16 & IHz)
Outputs . Using these two signals 1, the horizontal synchronizing pulse 15, and the carrier signal 18 from the hysteresis circuit 6, the NG/OK pulse generation circuit 8, the hysteresis circuit 6, and the hold circuit 7 generate a hold pulse 25. to occur.

In the NG/OK pulse generation circuit 8, the horizontal synchronizing pulse 15
A pulse that is inverted for each H level of the pulse 15 is synchronized with this signal (No. 8 16 EXCLSIV-O
AND the signal from which R is taken and the double synchronization signal 17,
NG pulse 23 (in Figure 2).

(see (g))). A signal obtained by inverting this signal is the OK pulse 24 (see Figure 2, (■)). The phase relationship of horizontal synchronizing pulse 15 with respect to NG pulse % and OK pulse 24 obtained by this is shown in Fig. 2 (5) ~
As shown in , the phase is not reversed by 180° for each H.

OK pulse 24c, hysteresis 00% 6 in ONG
It is input to the AND gate at the previous stage of the counter 9 and the OK counter 10, and serves to open either gate.

Now, when the phase relationship of the synchronization signal satisfies the television signal standard R8-17OA as shown in Figure 3, the horizontal synchronization pulse 150 phase with respect to OK pulse 24 and NG pulse B is changed as shown in Figure 2 When set, the rising edge signal of the horizontal synchronizing pulse 15 is input to the CK of the OK counter 10, and the OK counter 10 counts up.

If this state continues, the OK counter 10 is amplified every H, and when the counter value exceeds 7a-, the carrier wave signal 1
9 is output and passes through the NAND gate to both counters 9.
, clear 10.

After that, repeat the same operation.

Next, the horizontal synchronization pulse 15 moves, as shown in FIG. 2 (4).

If it is located at the boundary between the OK period and the NG period shown in (B) and is fluctuating over time, the horizontal synchronizing pulse 15 is input to the CK of both the NG counter 9 and the OK counter 10, and both Counters 9 and 10 start counting amplifiers. At this time, if the OK counter 10 always outputs the carrier wave signal 19 first, the output phase of the hold pulse 5 does not change. On the other hand, if the NG counter 9 outputs the carrier wave signal 18 first, both counters 9 and 10 are cleared at the same time, and this signal is further input to the NG/OK pulse generating circuit 8.

In the NG-OK pulse generation circuit 8, the carrier wave signal 18 generates an IH inversion pulse for each H. As a result, the NG pulse 23 generated from this circuit. OK pulse 2
4 is as shown in Figure 2 (■). Figure 0. Each phase of ■ is 140% compared to (A) and (B) in the same figure.
It will be shifted by n5ec. Therefore, the hold pulse 25 that is the output of the hold circuit 7 is also shifted by 140 naec. Once the pulse phase reaches the pulse phase of (2) in Figure 2 (2), the horizontal synchronizing pulse 1b comes to be located almost at the center of the OK period of the OK pulse 24, and is in a stable state that is strong against the jitter of the horizontal synchronizing pulse 15. Become.

〔effect〕

As explained above, the present invention allows the phase relationship of synchronization signals to be
By detecting in units of H, even if the phase relationship of the synchronization signal of the input video signal changes by 180 degrees, it is possible to respond to it after several H.
By using a hysteresis circuit with a K counter, a stable hold pulse can be obtained even if the rise of the horizontal synchronizing pulse fluctuates over time at the boundary between the COK period and the NG period (see Figure 2). It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a synchronization signal detection circuit for television video signals according to the present invention, FIG. FIG. 3 is a diagram showing a phase relationship of signals. ■...Sync signal separation circuit 2...Vertical sync pulse generator 3...Frame signal generator 4...Horizontal sync pulse generator 5...Burst control II: gr ncillator (BCO)

Claims (1)

[Claims] A synchronization signal separation circuit extracts the horizontal synchronization signal from the television video signal and a 3.58MHz synchronization signal synchronized with the burst signal.
synchronous signal and 7.16M with twice the frequency of the synchronous signal
A frame signal generator that generates a frame signal from a burst control oscillator that outputs an Hz signal, a vertical sync pulse generator, a horizontal sync pulse generator, and a vertical sync pulse and a horizontal sync pulse that are the outputs of both generators. Synchronization of television video signals, characterized in that it has a NG/OK pulse generator, a hysteresis circuit having an NG counter and an OK counter, and a hold circuit that generates a hold pulse from an OK pulse and a horizontal synchronizing pulse. Signal detection circuit.